Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20431

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

2677

1

T15

5

T16

1

T20

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18147

1

T7

2

T29

3

T36

1

auto[1]

4961

1

T15

5

T16

1

T18

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	297	1			T103	31		T108	26		T34	4
values[0]	13	1			T271	13		-	-		-	-
values[1]	495	1			T41	28		T106	1		T40	9
values[2]	530	1			T21	4		T24	1		T118	1
values[3]	693	1			T106	1		T42	22		T110	28
values[4]	381	1			T16	1		T22	23		T106	1
values[5]	670	1			T20	8		T116	15		T108	17
values[6]	621	1			T53	1		T148	10		T215	21
values[7]	648	1			T21	30		T109	5		T110	34
values[8]	2222	1			T15	5		T18	10		T23	22
values[9]	869	1			T19	33		T20	12		T21	35
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	528	1			T24	1		T41	28		T106	1
values[1]	559	1			T21	4		T109	5		T119	18
values[2]	629	1			T16	1		T42	22		T110	28
values[3]	459	1			T22	23		T106	2		T116	15
values[4]	585	1			T20	8		T104	1		T112	13
values[5]	640	1			T53	1		T110	12		T148	10
values[6]	2409	1			T18	10		T21	30		T23	22
values[7]	445	1			T15	5		T24	1		T101	6
values[8]	864	1			T19	33		T20	12		T21	35
values[9]	179	1			T108	26		T111	1		T171	21
minimum	15811	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T24	1		T50	10		T118	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	11		T106	1		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	1		T109	1		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T104	1		T182	1		T137	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	12		T111	1		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	1		T110	13		T153	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T22	12		T106	1		T116	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T106	1		T33	5		T59	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T104	1		T153	10		T121	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T20	1		T112	13		T113	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T53	1		T215	12		T216	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T110	10		T148	4		T217	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T18	10		T23	22		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T21	15		T35	4		T112	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T24	1		T101	6		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	1		T103	1		T58	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T19	18		T20	1		T21	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T21	11		T24	1		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T111	1		T171	5		T234	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T108	11		T259	1		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15585	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T40	9		T220	13		T277	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T50	9		T109	5		T150	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T41	17		T154	5		T296	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T21	3		T109	4		T119	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T182	8		T137	5		T171	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T42	10		T122	12		T114	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T110	15		T153	20		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T22	11		T108	5		T148	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T33	2		T59	2		T217	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T153	15		T121	2		T224	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T20	7		T175	9		T125	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T215	9		T216	15		T178	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T110	2		T148	6		T217	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T109	4		T110	10		T139	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T21	15		T35	4		T63	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T119	11		T148	13		T63	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T15	4		T103	2		T58	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T19	15		T20	11		T21	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T21	9		T107	14		T103	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T171	16		T221	15		T191	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T108	15		T259	10		T219	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T220	2		T284	9		T297	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T171	5		T126	3		T234	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T103	15		T108	11		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T271	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T50	10		T109	1		T150	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T41	11		T106	1		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T21	1		T24	1		T118	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T104	1		T182	1		T137	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	12		T122	13		T114	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T106	1		T110	13		T153	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	12		T106	1		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T16	1		T33	5		T59	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T116	15		T108	12		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T20	1		T112	13		T113	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T53	1		T215	12		T153	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T148	4		T217	11		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T109	1		T110	12		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T21	15		T110	10		T35	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1156	1			T18	10		T23	22		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	1		T103	1		T58	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T19	18		T20	1		T21	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T21	11		T24	1		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T171	16		T226	14		T221	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T103	16		T108	15		T34	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T271	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T50	9		T109	5		T150	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T41	17		T220	2		T154	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T21	3		T109	4		T119	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T182	8		T137	5		T171	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T42	10		T122	12		T114	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T110	15		T153	20		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T22	11		T148	6		T223	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T33	2		T59	2		T217	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T108	5		T121	2		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T20	7		T175	9		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T215	9		T153	15		T216	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T148	6		T217	6		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T109	4		T110	10		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T21	15		T110	2		T35	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	872	1			T119	11		T139	14		T148	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T15	4		T103	2		T58	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T19	15		T20	11		T21	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	9		T107	14		T182	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T24	1		T50	10		T118	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T41	18		T106	1		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T21	4		T109	5		T119	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T104	1		T182	9		T137	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	11		T111	1		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T16	1		T110	16		T153	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T22	12		T106	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T106	1		T33	6		T59	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T104	1		T153	16		T121	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	8		T112	1		T113	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T53	1		T215	10		T216	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T110	3		T148	7		T217	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T18	1		T23	3		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T21	16		T35	6		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T24	1		T101	1		T119	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	5		T103	3		T58	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T19	16		T20	12		T21	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T21	10		T24	1		T107	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T111	1		T171	17		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T108	16		T259	11		T219	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15719	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T40	1		T220	3		T277	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T50	9		T150	6		T121	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T41	10		T179	15		T154	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T179	14		T229	10		T230	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T137	5		T171	13		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T42	11		T122	12		T114	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T110	12		T153	17		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	11		T116	14		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T33	1		T59	2		T217	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T153	9		T121	3		T114	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T112	12		T113	26		T175	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T215	11		T216	13		T113	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T110	9		T148	3		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T18	9		T23	19		T166	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T21	14		T35	2		T112	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T101	5		T148	15		T63	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T58	1		T105	10		T216	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T19	17		T21	9		T41	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T21	10		T103	14		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T171	4		T234	10		T221	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T108	10		T235	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T146	4		T236	7		T253	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T40	8		T220	12		T284	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T171	17		T126	1		T234	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T103	17		T108	16		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T271	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T50	10		T109	6		T150	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T41	18		T106	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T21	4		T24	1		T118	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T104	1		T182	9		T137	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T42	11		T122	13		T114	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T106	1		T110	16		T153	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T22	12		T106	1		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T16	1		T33	6		T59	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T116	1		T108	6		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	8		T112	1		T113	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T53	1		T215	10		T153	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	7		T217	7		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T109	5		T110	11		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T21	16		T110	3		T35	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T18	1		T23	3		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	5		T103	3		T58	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T19	16		T20	12		T21	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T21	10		T24	1		T107	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T171	4		T126	2		T234	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T103	14		T108	10		T34	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T271	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T50	9		T150	6		T125	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	10		T40	8		T220	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T121	14		T122	10		T229	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T137	5		T171	2		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T42	11		T122	12		T114	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T110	12		T153	17		T171	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T22	11		T148	5		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T33	1		T59	2		T217	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T116	14		T108	11		T121	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T112	12		T113	26		T175	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T215	11		T153	9		T216	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T148	3		T217	10		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T110	11		T233	11		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T21	14		T110	9		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	861	1			T18	9		T23	19		T166	34
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T58	1		T112	8		T105	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T19	17		T21	9		T41	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T21	10		T105	8		T233	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33