Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20235

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

2873

1

T15

5

T16

1

T20

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18261

1

T7

2

T29

3

T36

1

auto[1]

4847

1

T15

5

T16

1

T18

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	205	1			T24	1		T111	1		T216	27
values[0]	23	1			T156	1		T242	1		T243	1
values[1]	449	1			T15	5		T116	15		T108	17
values[2]	595	1			T106	1		T50	19		T110	12
values[3]	591	1			T16	1		T19	33		T20	20
values[4]	681	1			T21	20		T24	1		T41	16
values[5]	577	1			T42	22		T33	7		T111	1
values[6]	592	1			T106	1		T53	1		T54	35
values[7]	596	1			T21	15		T106	1		T103	3
values[8]	428	1			T21	4		T24	1		T41	28
values[9]	2702	1			T18	10		T21	30		T23	22
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	454	1			T116	15		T108	17		T112	9
values[1]	570	1			T50	19		T110	12		T59	9
values[2]	691	1			T16	1		T19	33		T20	20
values[3]	647	1			T21	20		T24	1		T109	6
values[4]	582	1			T42	22		T33	7		T111	1
values[5]	588	1			T106	1		T53	1		T54	35
values[6]	2332	1			T18	10		T21	19		T23	22
values[7]	493	1			T24	1		T58	4		T104	1
values[8]	840	1			T21	30		T107	7		T103	31
values[9]	110	1			T24	1		T111	1		T216	27
minimum	15801	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T108	12		T221	28		T249	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T116	15		T112	9		T223	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T50	10		T110	10		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T59	7		T215	12		T153	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T19	18		T20	1		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T16	1		T20	1		T22	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T24	1		T109	1		T110	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	11		T111	1		T105	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T111	1		T113	13		T122	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T42	12		T33	5		T148	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T106	1		T182	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T53	1		T54	17		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T18	10		T23	22		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T21	11		T41	11		T101	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T24	1		T58	3		T222	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T104	1		T148	16		T220	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T107	1		T108	11		T110	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T21	15		T103	15		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T111	1		T229	11		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T24	1		T216	11		T179	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15564	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T15	1		T221	3		T222	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T108	5		T221	27		T249	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T223	1		T122	9		T245	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T50	9		T110	2		T182	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T59	2		T215	9		T153	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T19	15		T20	11		T109	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	7		T22	11		T41	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T109	5		T110	10		T148	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	9		T232	16		T61	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T122	12		T226	14		T183	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T42	10		T33	2		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T182	11		T228	2		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T54	18		T107	14		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T35	4		T139	14		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T21	8		T41	17		T103	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T58	1		T222	2		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T148	13		T220	2		T216	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T107	6		T108	15		T110	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T21	15		T103	16		T109	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T229	3		T244	2		T172	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T216	16		T298	11		T246	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T15	4		T221	2		T222	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T111	1		T217	6		T234	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T24	1		T216	11		T245	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T156	1		T243	1		T299	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T242	1		T300	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T108	12		T177	11		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T15	1		T116	15		T112	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T106	1		T50	10		T110	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T59	7		T215	12		T153	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T19	18		T20	1		T40	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T16	1		T20	1		T22	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T24	1		T109	1		T110	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T21	11		T41	14		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T111	1		T216	14		T113	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T42	12		T33	5		T148	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T106	1		T182	1		T122	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T53	1		T54	17		T107	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T106	1		T136	1		T233	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T21	10		T103	1		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T24	1		T35	4		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T21	1		T41	11		T101	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T18	10		T23	22		T25	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T21	15		T103	15		T109	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T217	5		T154	5		T172	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T216	16		T245	4		T125	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T299	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T108	5		T177	16		T221	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T15	4		T122	9		T245	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T50	9		T110	2		T182	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T59	2		T215	9		T153	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T19	15		T20	11		T109	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	7		T22	11		T224	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T109	5		T110	10		T148	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	9		T41	2		T232	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T216	15		T177	1		T226	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T42	10		T33	2		T148	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T182	11		T122	12		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T54	18		T107	14		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T121	2		T189	10		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T21	5		T103	2		T119	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T35	4		T222	2		T274	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T21	3		T41	17		T220	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T107	6		T108	15		T58	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T21	15		T103	16		T109	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T108	6		T221	29		T249	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T116	1		T112	1		T223	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T50	10		T110	3		T182	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T59	7		T215	10		T153	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	16		T20	12		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T16	1		T20	8		T22	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T24	1		T109	6		T110	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T21	10		T111	1		T105	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T111	1		T113	1		T122	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T42	11		T33	6		T148	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T106	1		T182	12		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T53	1		T54	19		T107	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T18	1		T23	3		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T21	10		T41	18		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T24	1		T58	3		T222	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T104	1		T148	14		T220	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T107	7		T108	16		T110	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T21	16		T103	17		T109	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T111	1		T229	4		T244	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T24	1		T216	17		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15721	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T15	5		T221	3		T222	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T108	11		T221	26		T249	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T116	14		T112	8		T122	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T50	9		T110	9		T237	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T59	2		T215	11		T153	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T19	17		T40	8		T63	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	11		T41	13		T112	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T110	11		T148	5		T216	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T21	10		T105	10		T234	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T113	12		T122	12		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T42	11		T33	1		T148	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T233	3		T228	2		T171	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T54	16		T34	1		T112	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T18	9		T23	19		T166	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T21	9		T41	10		T101	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T58	1		T222	9		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T148	15		T220	12		T216	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T108	10		T110	12		T153	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	14		T103	14		T150	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T229	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T216	10		T179	15		T146	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T177	10		T279	3		T301	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T221	2		T222	9		T62	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T111	1		T217	6		T234	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T24	1		T216	17		T245	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T156	1		T243	1		T299	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T242	1		T300	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T108	6		T177	17		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	5		T116	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T106	1		T50	10		T110	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T59	7		T215	10		T153	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	16		T20	12		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	1		T20	8		T22	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T24	1		T109	6		T110	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T21	10		T41	3		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T111	1		T216	16		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T42	11		T33	6		T148	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T106	1		T182	12		T122	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T53	1		T54	19		T107	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T106	1		T136	1		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T21	6		T103	3		T119	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T24	1		T35	6		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T21	4		T41	18		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T18	1		T23	3		T25	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	16		T103	17		T109	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T217	5		T234	7		T154	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T216	10		T125	13		T60	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T108	11		T177	10		T221	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T116	14		T112	8		T122	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T50	9		T110	9		T221	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T59	2		T215	11		T153	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T19	17		T40	8		T63	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	11		T112	10		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T110	11		T148	5		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	10		T41	13		T105	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T216	13		T113	12		T226	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T42	11		T33	1		T148	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T122	12		T228	2		T171	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T54	16		T34	1		T112	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T233	3		T121	3		T189	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T21	9		T151	2		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T35	2		T222	9		T274	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T41	10		T101	5		T220	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T18	9		T23	19		T166	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T21	14		T103	14		T148	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33