Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6878	1			T13	1		T18	50		T19	7
testmodes[AdcCtrlTestmodeNormal]	5544	1			T13	9		T16	1		T17	1
testmodes[AdcCtrlTestmodeLowpower]	5919	1			T13	9		T14	1		T15	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3699	1			T18	14		T19	2		T21	86
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1684	1			T18	18		T19	5		T21	35
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1385	1			T13	1		T18	18		T21	41
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1686	1			T13	1		T18	14		T19	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2065	1			T13	3		T18	17		T19	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1459	1			T13	4		T18	23		T21	30
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1374	1			T18	22		T21	34		T22	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1451	1			T13	5		T18	19		T21	36
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2843	1			T13	4		T15	1		T18	30