Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20798

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

4834

1

T13

10

T14

7

T15

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20266

1

T6

1

T7

2

T26

1

auto[1]

5366

1

T13

10

T14

7

T15

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	36	1			T220	16		T221	1		T222	1
values[1]	545	1			T16	16		T38	10		T56	11
values[2]	686	1			T102	10		T133	10		T109	5
values[3]	646	1			T17	1		T20	18		T40	5
values[4]	593	1			T13	10		T41	10		T102	2
values[5]	687	1			T24	11		T39	6		T55	13
values[6]	600	1			T58	1		T43	29		T108	1
values[7]	718	1			T223	3		T131	23		T118	1
values[8]	606	1			T118	5		T50	7		T132	1
values[9]	3071	1			T14	7		T15	29		T23	3
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	637	1			T16	16		T38	10		T56	11
values[1]	2693	1			T14	7		T15	29		T17	1
values[2]	557	1			T20	18		T102	2		T40	5
values[3]	756	1			T13	10		T41	10		T43	1
values[4]	637	1			T24	11		T43	29		T39	6
values[5]	600	1			T58	1		T108	1		T131	23
values[6]	699	1			T223	3		T39	5		T134	17
values[7]	578	1			T118	5		T50	7		T132	1
values[8]	803	1			T24	4		T107	12		T43	17
values[9]	179	1			T133	11		T123	9		T158	13
minimum	17493	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T16	1		T38	3		T56	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T110	15		T111	1		T197	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T133	10		T119	1		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1287	1			T14	7		T15	29		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T40	4		T225	2		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T20	9		T102	2		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T41	7		T43	1		T148	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	3		T146	11		T118	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T43	15		T39	3		T55	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T24	1		T109	3		T110	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T58	1		T108	1		T131	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T118	1		T51	13		T168	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T223	3		T39	3		T227	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T134	9		T228	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T50	4		T40	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T118	1		T132	1		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T24	1		T107	1		T43	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T108	1		T132	1		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T133	11		T123	9		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T138	1		T229	8		T184	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17295	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T230	12		T231	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T16	15		T38	7		T232	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T110	11		T197	4		T122	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T126	1		T134	9		T233	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1021	1			T25	26		T102	5		T115	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T40	1		T225	1		T148	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	9		T154	16		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T41	3		T148	6		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	7		T118	12		T110	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	14		T39	3		T55	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T24	10		T235	10		T126	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T131	12		T112	10		T236	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T51	10		T124	11		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T39	2		T227	16		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T134	8		T228	2		T127	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	3		T40	1		T151	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T118	4		T239	11		T240	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T24	3		T107	11		T43	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T235	17		T125	1		T114	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T158	12		T154	11		T241	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T229	2		T231	12		T242	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T230	12		T231	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T220	1		T222	1		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	1		T243	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	1		T38	3		T56	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T40	9		T110	15		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T133	10		T119	2		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T102	5		T109	5		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	4		T225	2		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	1		T20	9		T152	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T41	7		T43	1		T148	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	3		T102	2		T146	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T39	3		T55	6		T56	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T24	1		T109	3		T110	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T58	1		T43	15		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T51	13		T126	13		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T223	3		T131	11		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T118	1		T168	11		T124	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T50	4		T40	1		T152	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T118	1		T132	1		T123	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T24	1		T107	1		T43	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1293	1			T14	7		T15	29		T23	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T220	15		T140	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T243	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	15		T38	7		T232	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T110	11		T122	16		T172	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T126	1		T233	7		T201	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T102	5		T111	9		T197	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T40	1		T225	1		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T20	9		T237	1		T154	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T41	3		T148	7		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T13	7		T118	12		T135	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T39	3		T55	7		T56	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T24	10		T110	18		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T43	14		T112	10		T151	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T51	10		T126	12		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T131	12		T39	2		T227	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T124	11		T127	11		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T50	3		T40	1		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T118	4		T114	14		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T24	3		T107	11		T43	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1065	1			T25	26		T115	21		T54	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	16		T38	8		T56	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T110	12		T111	1		T197	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T133	1		T119	1		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1358	1			T14	1		T15	2		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T40	2		T225	2		T148	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	10		T102	2		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T41	6		T43	1		T148	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	9		T146	1		T118	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T43	15		T39	4		T55	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	11		T109	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T58	1		T108	1		T131	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T118	1		T51	11		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T223	1		T39	3		T227	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T134	9		T228	3		T127	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T50	4		T40	2		T151	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T118	5		T132	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T24	4		T107	12		T43	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T108	1		T132	1		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T133	1		T123	1		T158	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T138	1		T229	9		T184	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17460	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T230	13		T231	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T38	2		T56	10		T136	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T110	14		T197	1		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T133	9		T126	2		T134	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	950	1			T14	6		T15	27		T102	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T40	3		T225	1		T245	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T20	8		T154	16		T234	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T41	4		T148	9		T198	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T13	1		T146	10		T118	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T43	14		T39	2		T55	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T109	2		T110	9		T235	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T131	10		T112	9		T236	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T51	12		T168	10		T124	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T223	2		T39	2		T227	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T134	8		T246	2		T247	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	3		T152	12		T136	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T123	12		T239	8		T240	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T43	9		T38	2		T56	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T235	14		T125	8		T114	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T133	10		T123	8		T154	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T229	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T230	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	9	39	81.25	9

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T220	16		T222	1		T140	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T221	1		T243	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T16	16		T38	8		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	1		T110	12		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T133	1		T119	2		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T102	8		T109	1		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	2		T225	2		T151	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T17	1		T20	10		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	6		T43	1		T148	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	9		T102	2		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T39	4		T55	8		T56	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T24	11		T109	1		T110	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T58	1		T43	15		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	11		T126	13		T237	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T223	1		T131	13		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T118	1		T168	1		T124	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T50	4		T40	2		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T118	5		T132	1		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T24	4		T107	12		T43	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1426	1			T14	1		T15	2		T23	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T38	2		T56	10		T136	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T40	8		T110	14		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T133	9		T126	2		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T102	2		T109	4		T111	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T40	3		T225	1		T134	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T20	8		T152	6		T154	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	4		T148	9		T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T13	1		T146	10		T118	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T39	2		T55	5		T56	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T109	2		T110	23		T122	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T43	14		T112	9		T191	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T51	12		T126	12		T246	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T223	2		T131	10		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T168	10		T124	12		T175	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T50	3		T152	12		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T123	12		T114	12		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T43	9		T38	2		T56	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	932	1			T14	6		T15	27		T59	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22542

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

3090

1

T20

18

T24

15

T58

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20173

1

T6

1

T7

2

T26

1

auto[1]

5459

1

T14

7

T15

29

T16

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T248	19		T249	1		-	-
values[0]	50	1			T108	1		T152	7		T154	23
values[1]	578	1			T38	9		T56	11		T133	11
values[2]	609	1			T13	10		T24	4		T102	2
values[3]	448	1			T43	29		T132	1		T133	11
values[4]	625	1			T41	10		T43	18		T108	1
values[5]	654	1			T20	18		T38	10		T118	1
values[6]	589	1			T17	1		T108	1		T40	2
values[7]	712	1			T58	1		T118	5		T40	5
values[8]	663	1			T24	11		T223	3		T131	23
values[9]	3240	1			T14	7		T15	29		T16	16
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	690	1			T13	10		T24	4		T102	2
values[1]	667	1			T118	24		T40	9		T110	59
values[2]	500	1			T41	10		T43	29		T133	11
values[3]	651	1			T43	18		T108	1		T50	7
values[4]	530	1			T17	1		T20	18		T38	10
values[5]	681	1			T40	2		T119	1		T111	19
values[6]	2735	1			T14	7		T15	29		T23	3
values[7]	602	1			T16	16		T24	11		T102	10
values[8]	948	1			T107	12		T55	13		T56	12
values[9]	166	1			T173	1		T250	11		T251	2
minimum	17462	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	3		T56	11		T133	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T24	1		T102	2		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T118	12		T40	9		T110	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T110	15		T119	1		T197	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T41	7		T133	11		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T43	15		T158	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T43	11		T39	3		T56	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T108	1		T50	4		T109	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T17	1		T38	3		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T20	9		T108	1		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	1		T119	1		T111	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T113	1		T198	6		T152	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T14	7		T15	29		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T58	1		T146	11		T110	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	1		T102	5		T223	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T24	1		T131	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T225	2		T119	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T107	1		T55	6		T56	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T251	1		T248	1		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T173	1		T250	3		T253	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17304	1			T13	17		T18	176		T19	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	7		T148	6		T154	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T24	3		T38	6		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T118	12		T110	11		T124	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T110	18		T197	4		T254	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T41	3		T151	15		T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T43	14		T158	12		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T43	7		T39	2		T56	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T50	3		T135	10		T240	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T38	7		T112	10		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T20	9		T39	3		T122	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T40	1		T111	9		T236	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T228	5		T191	6		T244	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T25	26		T115	21		T118	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T220	15		T255	2		T256	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T16	15		T102	5		T51	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T24	10		T131	12		T235	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T225	1		T151	14		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T107	11		T55	7		T56	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T251	1		T248	9		T252	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T250	8		T257	17		T258	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	1		T7	2		T26	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T248	2		T249	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T152	7		T154	12		T259	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T108	1		T260	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T56	11		T133	11		T148	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T38	3		T123	9		T227	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	3		T118	12		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T24	1		T102	2		T110	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T132	1		T133	11		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T43	15		T197	4		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T41	7		T43	11		T56	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T108	1		T109	3		T122	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T38	3		T118	1		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T20	9		T50	4		T39	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	1		T40	1		T195	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T108	1		T122	12		T198	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T118	1		T40	4		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T58	1		T149	1		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T223	3		T113	1		T261	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T24	1		T131	11		T146	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T14	7		T15	29		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T107	1		T55	6		T56	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T248	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T154	11		T259	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T148	6		T126	12		T137	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T38	6		T227	9		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	7		T118	12		T110	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T24	3		T110	18		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T232	7		T262	11		T185	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T43	14		T197	4		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T41	3		T43	7		T56	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T135	10		T201	8		T263	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T38	7		T39	2		T112	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T20	9		T50	3		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T40	1		T154	11		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T122	16		T244	12		T251	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T118	4		T40	1		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T228	5		T233	7		T220	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T114	14		T191	9		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T24	10		T131	12		T235	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T16	15		T25	26		T102	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T107	11		T55	7		T56	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1