Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20728

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

4904

1

T13

10

T14

7

T15

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20245

1

T6

1

T7

2

T26

1

auto[1]

5387

1

T13

10

T14

7

T15

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	165	1			T108	1		T154	21		T247	46
values[0]	41	1			T286	22		T222	1		T140	10
values[1]	541	1			T16	16		T102	10		T38	10
values[2]	652	1			T40	9		T133	10		T109	5
values[3]	623	1			T17	1		T20	18		T102	2
values[4]	635	1			T13	10		T41	10		T43	1
values[5]	667	1			T24	11		T39	6		T55	13
values[6]	634	1			T58	1		T43	29		T108	1
values[7]	717	1			T223	3		T131	23		T118	1
values[8]	594	1			T118	5		T50	7		T132	1
values[9]	2919	1			T14	7		T15	29		T23	3
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	579	1			T16	16		T102	10		T56	11
values[1]	2694	1			T14	7		T15	29		T17	1
values[2]	537	1			T20	18		T102	2		T40	5
values[3]	797	1			T13	10		T41	10		T43	1
values[4]	618	1			T24	11		T43	29		T39	6
values[5]	572	1			T58	1		T108	1		T131	23
values[6]	713	1			T223	3		T51	23		T39	5
values[7]	547	1			T118	5		T50	7		T132	1
values[8]	908	1			T24	4		T107	12		T43	17
values[9]	106	1			T38	9		T133	11		T158	13
minimum	17561	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	1		T56	11		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T102	5		T110	15		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T225	2		T119	1		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1301	1			T14	7		T15	29		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T40	4		T245	7		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	9		T102	2		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T41	7		T43	1		T148	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	3		T146	11		T118	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T43	15		T39	3		T55	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T24	1		T109	3		T110	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T58	1		T108	1		T131	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T118	1		T168	11		T124	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T223	3		T39	3		T227	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T51	13		T228	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T50	4		T40	1		T152	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T118	1		T132	1		T123	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T24	1		T107	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	10		T108	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T38	3		T133	11		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T242	1		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17328	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T182	1		T172	7		T286	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T16	15		T197	4		T232	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T102	5		T110	11		T122	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T225	1		T126	1		T134	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1043	1			T25	26		T115	21		T54	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T40	1		T335	16		T336	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T20	9		T154	16		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T41	3		T148	7		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	7		T118	12		T110	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	14		T39	3		T55	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T24	10		T235	10		T126	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	12		T112	10		T236	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T124	11		T137	9		T232	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T39	2		T227	16		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	10		T228	2		T127	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T50	3		T40	1		T277	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T118	4		T151	15		T134	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T24	3		T107	11		T56	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T43	7		T235	17		T125	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T38	6		T158	12		T241	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T242	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T172	8		T286	17		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T154	10		T247	24		T194	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T108	1		T288	16		T286	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T222	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T286	5		T140	1		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T16	1		T38	3		T56	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T102	5		T110	15		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T119	2		T197	4		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T40	9		T133	10		T109	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	4		T225	2		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	1		T20	9		T102	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T41	7		T43	1		T148	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	3		T146	11		T118	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T39	3		T55	6		T56	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T24	1		T109	3		T110	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T58	1		T43	15		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	13		T126	13		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T223	3		T131	11		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T118	1		T168	11		T124	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T50	4		T40	1		T152	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T118	1		T132	1		T123	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T24	1		T107	1		T38	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1301	1			T14	7		T15	29		T23	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T154	11		T247	22		T278	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T286	5		T310	14		T334	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T286	17		T140	9		T243	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T16	15		T38	7		T232	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T102	5		T110	11		T122	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T197	4		T126	1		T201	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T111	9		T124	13		T237	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T40	1		T225	1		T134	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T20	9		T154	16		T240	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T41	3		T148	7		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T13	7		T118	12		T135	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T39	3		T55	7		T56	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T24	10		T110	18		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	14		T112	10		T236	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T51	10		T126	12		T237	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T131	12		T39	2		T227	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T124	11		T127	11		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T50	3		T40	1		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T118	4		T134	8		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T24	3		T107	11		T38	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1093	1			T25	26		T43	7		T115	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	16		T56	1		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T102	8		T110	12		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T225	2		T119	1		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1379	1			T14	1		T15	2		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T40	2		T245	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	10		T102	2		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T41	6		T43	1		T148	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	9		T146	1		T118	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T43	15		T39	4		T55	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T24	11		T109	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T58	1		T108	1		T131	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T118	1		T168	1		T124	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T223	1		T39	3		T227	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T51	11		T228	3		T127	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T50	4		T40	2		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T118	5		T132	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T24	4		T107	12		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T43	8		T108	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T38	7		T133	1		T158	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T242	10		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17484	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T182	1		T172	14		T286	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T56	10		T197	1		T136	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T102	2		T110	14		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T225	1		T126	2		T134	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	965	1			T14	6		T15	27		T59	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T40	3		T245	6		T200	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T20	8		T154	16		T234	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T41	4		T148	9		T198	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T13	1		T146	10		T118	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T43	14		T39	2		T55	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T109	2		T110	9		T235	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T131	10		T112	9		T236	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T168	10		T124	12		T246	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T223	2		T39	2		T227	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	12		T240	9		T247	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T50	3		T152	12		T136	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T123	12		T134	8		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T56	13		T133	10		T123	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T43	9		T235	14		T125	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T38	2		T133	10		T241	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T38	2		T130	3		T337	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T172	1		T286	4		T320	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T154	12		T247	24		T194	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T108	1		T288	1		T286	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T222	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T286	18		T140	10		T243	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	16		T38	8		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T102	8		T110	12		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T119	2		T197	7		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T40	1		T133	1		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	2		T225	2		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T17	1		T20	10		T102	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T41	6		T43	1		T148	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	9		T146	1		T118	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T39	4		T55	8		T56	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T24	11		T109	1		T110	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T58	1		T43	15		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	11		T126	13		T237	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T223	1		T131	13		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T118	1		T168	1		T124	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T50	4		T40	2		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T118	5		T132	1		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T24	4		T107	12		T38	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1454	1			T14	1		T15	2		T23	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T154	9		T247	22		T278	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T288	15		T286	7		T334	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T286	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T38	2		T56	10		T136	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T102	2		T110	14		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T197	1		T126	2		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	8		T133	9		T109	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T40	3		T225	1		T134	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T20	8		T152	6		T154	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	4		T148	9		T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T13	1		T146	10		T118	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	2		T55	5		T56	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T109	2		T110	23		T122	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T43	14		T112	9		T236	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T51	12		T126	12		T246	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T223	2		T131	10		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T168	10		T124	12		T175	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	3		T152	12		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T123	12		T134	8		T239	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T38	2		T56	13		T133	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	940	1			T14	6		T15	27		T59	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27