Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22461

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

3171

1

T13

10

T16

16

T24

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20502

1

T6

1

T7

2

T26

1

auto[1]

5130

1

T13

10

T14

7

T15

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T51	23		T173	1		T338	1
values[0]	51	1			T339	6		T340	17		T231	9
values[1]	614	1			T13	10		T223	3		T38	9
values[2]	495	1			T43	17		T50	7		T132	1
values[3]	701	1			T102	10		T108	1		T55	13
values[4]	624	1			T108	1		T40	5		T119	1
values[5]	2820	1			T14	7		T15	29		T23	3
values[6]	595	1			T24	11		T58	1		T43	29
values[7]	471	1			T16	16		T102	2		T107	12
values[8]	579	1			T17	1		T24	4		T41	10
values[9]	1213	1			T20	18		T43	1		T39	6
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	772	1			T13	10		T43	17		T38	9
values[1]	613	1			T223	3		T50	7		T110	33
values[2]	617	1			T102	10		T108	1		T55	13
values[3]	2702	1			T14	7		T15	29		T23	3
values[4]	694	1			T108	1		T131	23		T118	5
values[5]	595	1			T24	11		T58	1		T43	29
values[6]	468	1			T16	16		T102	2		T107	12
values[7]	575	1			T17	1		T24	4		T41	10
values[8]	896	1			T20	18		T43	1		T51	23
values[9]	210	1			T114	27		T240	19		T173	1
minimum	17490	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T148	10		T113	1		T245	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	3		T43	10		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T223	3		T110	15		T245	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T50	4		T112	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T108	1		T225	2		T123	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T102	5		T55	6		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T14	7		T15	29		T23	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T119	1		T123	13		T126	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T108	1		T131	11		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T56	6		T124	17		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T109	5		T197	4		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	1		T58	1		T43	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T107	1		T108	1		T109	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	1		T102	2		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T17	1		T41	7		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T24	1		T148	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T20	9		T43	1		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T56	11		T40	9		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T306	10		T283	3		T241	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T114	13		T240	10		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17305	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T341	13		T231	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T148	6		T135	16		T201	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	7		T43	7		T38	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T110	18		T137	9		T172	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T50	3		T237	11		T236	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T225	1		T228	5		T239	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T102	5		T55	7		T111	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T25	26		T115	21		T38	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T126	1		T250	13		T285	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T131	12		T118	4		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T56	6		T124	13		T252	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T197	4		T137	5		T238	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T24	10		T43	14		T56	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T107	11		T234	2		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T16	15		T134	8		T254	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	3		T39	3		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T24	3		T148	1		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T20	9		T51	10		T124	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T158	12		T235	27		T237	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T267	3		T166	16		T342	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T114	14		T240	9		T343	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T341	13		T231	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T51	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T173	1		T338	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T344	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T339	5		T340	13		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T223	3		T148	10		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	3		T38	3		T118	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T110	15		T228	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T43	10		T50	4		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T108	1		T225	2		T123	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T102	5		T55	6		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T108	1		T40	4		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T119	1		T111	10		T123	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T14	7		T15	29		T23	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T56	20		T124	17		T126	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	11		T39	3		T197	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T24	1		T58	1		T43	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T107	1		T108	1		T109	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	1		T102	2		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	1		T41	7		T146	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T24	1		T148	1		T168	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T20	9		T43	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T56	11		T40	9		T109	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T51	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T339	1		T340	4		T231	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T148	6		T135	16		T201	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	7		T38	6		T118	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T110	18		T228	5		T137	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T43	7		T50	3		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T225	1		T239	11		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T102	5		T55	7		T151	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T40	1		T151	14		T336	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T111	9		T151	9		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T25	26		T115	21		T38	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T56	8		T124	13		T126	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	12		T39	2		T197	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T24	10		T43	14		T110	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T107	11		T234	2		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T16	15		T345	1		T283	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T41	3		T40	1		T153	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T24	3		T148	1		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T20	9		T39	3		T124	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T158	12		T235	27		T114	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T148	7		T113	1		T245	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	9		T43	8		T38	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T223	1		T110	19		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T50	4		T112	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T108	1		T225	2		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T102	8		T55	8		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T14	1		T15	2		T23	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T119	1		T123	1		T126	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T108	1		T131	13		T118	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T56	7		T124	14		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T109	1		T197	7		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T24	11		T58	1		T43	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T107	12		T108	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	16		T102	2		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	1		T41	6		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T24	4		T148	2		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T20	10		T43	1		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T56	1		T40	1		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T306	1		T283	1		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T114	15		T240	10		T173	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17445	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T341	14		T231	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T148	9		T245	6		T135	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T43	9		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T223	2		T110	14		T245	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T50	3		T236	15		T264	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T225	1		T123	8		T239	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T102	2		T55	5		T111	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T14	6		T15	27		T59	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T123	12		T126	2		T287	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T131	10		T39	2		T40	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T56	5		T124	16		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T109	4		T197	1		T152	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T43	14		T56	13		T110	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T109	2		T110	9		T234	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T134	8		T265	12		T254	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T41	4		T146	10		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T168	10		T282	9		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T20	8		T51	12		T133	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T56	10		T40	8		T235	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T306	9		T283	2		T241	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T114	12		T240	9		T343	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T346	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T341	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T51	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T173	1		T338	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T344	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T339	5		T340	5		T231	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T223	1		T148	7		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	9		T38	7		T118	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T110	19		T228	6		T137	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T43	8		T50	4		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T108	1		T225	2		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T102	8		T55	8		T151	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T108	1		T40	2		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T119	1		T111	10		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1428	1			T14	1		T15	2		T23	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T56	10		T124	14		T126	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T131	13		T39	3		T197	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T24	11		T58	1		T43	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T107	12		T108	1		T109	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	16		T102	2		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T17	1		T41	6		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T24	4		T148	2		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T20	10		T43	1		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T56	1		T40	1		T109	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T51	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T344	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T339	1		T340	12		T347	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T223	2		T148	9		T245	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	1		T38	2		T118	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T110	14		T172	1		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T43	9		T50	3		T200	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T225	1		T123	8		T245	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T102	2		T55	5		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T40	3		T129	16		T199	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T111	9		T123	12		T125	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T14	6		T15	27		T59	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T56	18		T124	16		T126	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T131	10		T39	2		T197	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T43	14		T110	14		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T109	6		T234	1		T240	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T136	13		T265	12		T283	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T41	4		T146	10		T110	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T168	10		T134	8		T282	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T20	8		T39	2		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T56	10		T40	8		T235	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27