Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22749

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

2883

1

T13

10

T17

1

T24

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20300

1

T6

1

T7

2

T26

1

auto[1]

5332

1

T13

10

T14

7

T15

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	277	1			T108	1		T118	24		T225	3
values[0]	28	1			T282	10		T270	6		T323	11
values[1]	528	1			T13	10		T16	16		T108	1
values[2]	762	1			T43	17		T133	10		T119	1
values[3]	682	1			T102	10		T119	1		T197	8
values[4]	2583	1			T14	7		T15	29		T20	18
values[5]	611	1			T17	1		T38	10		T133	22
values[6]	621	1			T102	2		T51	23		T40	5
values[7]	627	1			T108	1		T50	7		T109	8
values[8]	556	1			T41	10		T38	9		T118	5
values[9]	913	1			T43	1		T146	11		T56	28
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	515	1			T13	10		T16	16		T108	1
values[1]	724	1			T43	17		T133	10		T119	1
values[2]	644	1			T24	15		T102	10		T119	1
values[3]	2648	1			T14	7		T15	29		T20	18
values[4]	612	1			T17	1		T133	11		T151	16
values[5]	683	1			T102	2		T51	23		T40	5
values[6]	535	1			T38	9		T108	1		T50	7
values[7]	622	1			T41	10		T43	1		T118	5
values[8]	898	1			T108	1		T146	11		T118	24
values[9]	96	1			T127	12		T155	1		T348	1
minimum	17655	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T16	1		T39	3		T55	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T13	3		T108	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T133	10		T160	1		T152	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T43	10		T119	1		T168	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	1		T102	5		T197	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T24	1		T119	1		T227	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T14	7		T15	29		T20	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T43	15		T118	1		T40	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T151	1		T126	13		T154	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T17	1		T133	11		T136	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T102	2		T40	4		T109	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	13		T134	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T38	3		T108	1		T109	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T50	4		T111	10		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T56	25		T132	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T41	7		T43	1		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T108	1		T110	15		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T146	11		T118	12		T56	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T127	1		T349	1		T178	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T155	1		T348	1		T327	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17322	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T131	11		T234	3		T238	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T16	15		T39	2		T55	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T13	7		T158	12		T235	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T126	1		T135	6		T244	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T43	7		T112	10		T154	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T24	3		T102	5		T197	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T24	10		T227	16		T264	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T20	9		T25	26		T107	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T43	14		T237	11		T254	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T151	15		T126	12		T154	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T277	1		T251	8		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	1		T110	18		T148	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T51	10		T228	2		T247	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T38	6		T135	10		T237	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T50	3		T111	9		T151	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T56	2		T228	5		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T41	3		T118	4		T39	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T110	11		T153	12		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T118	12		T56	6		T225	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T127	11		T349	1		T318	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T327	10		T293	13		T350	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T131	12		T234	2		T238	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T108	1		T198	6		T154	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T118	12		T225	2		T266	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T329	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T282	10		T270	6		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	1		T39	3		T55	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	3		T108	1		T131	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T133	10		T123	13		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T43	10		T119	1		T112	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T102	5		T197	4		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T119	1		T168	11		T227	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T14	7		T15	29		T20	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T24	1		T43	15		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T38	3		T133	11		T245	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T17	1		T133	11		T136	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T102	2		T40	4		T110	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T51	13		T134	1		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T108	1		T109	8		T110	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T50	4		T111	10		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T38	3		T56	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	7		T118	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T56	14		T109	1		T110	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T43	1		T146	11		T56	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T154	11		T201	8		T345	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T118	12		T225	1		T266	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T323	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	15		T39	2		T55	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T13	7		T131	12		T158	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T122	16		T126	1		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	7		T112	10		T235	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T102	5		T197	4		T114	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T227	16		T183	11		T263	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T20	9		T24	3		T25	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T24	10		T43	14		T254	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T38	7		T154	16		T220	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T237	11		T251	8		T229	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T40	1		T110	18		T148	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T51	10		T228	2		T247	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T125	1		T135	10		T237	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T50	3		T111	9		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T38	6		T227	9		T233	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	3		T118	4		T39	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T56	2		T110	11		T228	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T56	6		T151	9		T134	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T16	16		T39	3		T55	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T13	9		T108	1		T158	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T133	1		T160	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	8		T119	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T24	4		T102	8		T197	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	11		T119	1		T227	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T14	1		T15	2		T20	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T43	15		T118	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T151	16		T126	13		T154	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T17	1		T133	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T102	2		T40	2		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T51	11		T134	1		T228	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T38	7		T108	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T50	4		T111	10		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T56	4		T132	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T41	6		T43	1		T118	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T108	1		T110	12		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T146	1		T118	13		T56	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T127	12		T349	2		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T155	1		T348	1		T327	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17489	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T131	13		T234	4		T238	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	2		T55	5		T123	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	1		T235	13		T282	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T133	9		T152	12		T245	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	9		T168	10		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T102	2		T197	1		T114	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T227	16		T246	10		T265	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T14	6		T15	27		T20	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T43	14		T40	8		T122	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T126	12		T154	16		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T133	10		T136	13		T277	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T40	3		T109	2		T110	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T51	12		T136	11		T247	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T38	2		T109	4		T135	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T50	3		T111	9		T191	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T56	23		T227	9		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	4		T39	2		T124	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T110	14		T198	5		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T146	10		T118	11		T56	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T178	14		T179	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T327	8		T179	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T152	6		T175	2		T351	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T131	10		T234	1		T238	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T108	1		T198	1		T154	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T118	13		T225	2		T266	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T329	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T282	1		T270	1		T323	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T16	16		T39	3		T55	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	9		T108	1		T131	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T133	1		T123	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T43	8		T119	1		T112	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T102	8		T197	7		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T119	1		T168	1		T227	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T14	1		T15	2		T20	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	11		T43	15		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T38	8		T133	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	1		T133	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T102	2		T40	2		T110	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T51	11		T134	1		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T108	1		T109	2		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T50	4		T111	10		T151	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T38	7		T56	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	6		T118	5		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T56	3		T109	1		T110	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T43	1		T146	1		T56	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T198	5		T154	9		T201	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T118	11		T225	1		T266	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T282	9		T270	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T39	2		T55	5		T152	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T13	1		T131	10		T234	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T133	9		T123	12		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T43	9		T112	9		T198	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T102	2		T197	1		T245	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T168	10		T227	16		T246	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T14	6		T15	27		T20	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T43	14		T40	8		T122	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	2		T133	10		T245	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T133	10		T136	13		T251	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T40	3		T110	14		T123	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T51	12		T136	11		T247	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T109	6		T110	9		T125	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T50	3		T111	9		T322	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	2		T56	10		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	4		T39	2		T124	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T56	13		T110	14		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T146	10		T56	5		T134	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27