Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22312

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

3320

1

T13

10

T16

16

T17

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20010

1

T6

1

T7

2

T26

1

auto[1]

5622

1

T14

7

T15

29

T16

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	191	1			T39	5		T119	1		T149	1
values[0]	51	1			T110	10		T294	2		T293	14
values[1]	708	1			T102	10		T108	1		T55	13
values[2]	2603	1			T14	7		T15	29		T23	3
values[3]	765	1			T16	16		T131	23		T56	16
values[4]	725	1			T118	1		T50	7		T132	1
values[5]	667	1			T41	10		T223	3		T39	6
values[6]	456	1			T13	10		T17	1		T20	18
values[7]	559	1			T102	2		T107	12		T43	18
values[8]	702	1			T43	29		T38	10		T51	23
values[9]	761	1			T24	15		T38	9		T146	11
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	747	1			T102	10		T108	1		T110	10
values[1]	2631	1			T14	7		T15	29		T23	3
values[2]	708	1			T16	16		T56	16		T132	1
values[3]	738	1			T118	1		T50	7		T132	1
values[4]	608	1			T20	18		T41	10		T223	3
values[5]	416	1			T13	10		T17	1		T43	17
values[6]	682	1			T102	2		T107	12		T43	1
values[7]	591	1			T43	29		T38	10		T51	23
values[8]	759	1			T24	15		T38	9		T146	11
values[9]	112	1			T39	5		T119	1		T264	25
minimum	17640	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T102	5		T160	1		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T108	1		T110	10		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T14	7		T15	29		T23	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T131	11		T109	3		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T148	1		T198	15		T235	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T16	1		T56	14		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T50	4		T226	1		T245	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T118	1		T132	1		T110	30
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T39	3		T237	1		T282	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T20	9		T41	7		T223	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T43	10		T108	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	3		T17	1		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T102	2		T109	1		T197	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T107	1		T43	1		T40	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T111	10		T127	1		T247	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T43	15		T38	3		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T38	3		T118	12		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T24	2		T146	11		T149	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T39	3		T264	13		T199	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T119	1		T289	1		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17349	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T56	6		T336	1		T252	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T102	5		T201	8		T263	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T172	8		T254	1		T286	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T25	26		T115	21		T54	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T131	12		T112	10		T124	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T148	1		T235	17		T154	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	15		T56	2		T225	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T50	3		T277	1		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T110	29		T114	14		T227	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T39	3		T237	1		T165	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T20	9		T41	3		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T43	7		T137	3		T285	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	7		T118	4		T122	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T197	4		T153	12		T154	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T107	11		T158	12		T126	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T111	9		T247	3		T277	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	14		T38	7		T51	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T38	6		T118	12		T235	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T24	13		T151	14		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T39	2		T264	12		T291	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T289	16		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T56	6		T336	1		T252	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T39	3		T165	1		T199	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T119	1		T149	1		T239	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T293	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T110	10		T294	1		T297	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T102	5		T55	6		T109	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T108	1		T56	6		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T14	7		T15	29		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T109	3		T224	1		T124	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T148	1		T198	15		T235	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T16	1		T131	11		T56	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	4		T226	1		T246	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T118	1		T132	1		T110	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	3		T245	3		T237	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T41	7		T223	3		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T108	1		T132	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	3		T17	1		T20	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T102	2		T43	10		T197	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T107	1		T43	1		T40	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T109	1		T111	10		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T43	15		T38	3		T51	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T38	3		T118	12		T56	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	2		T146	11		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T39	2		T165	2		T323	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T239	11		T273	1		T230	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T293	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T294	1		T297	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T102	5		T55	7		T240	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T56	6		T172	8		T286	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T25	26		T115	21		T54	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T124	13		T125	1		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T148	1		T235	17		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	15		T131	12		T56	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T50	3		T277	1		T175	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T110	29		T151	9		T124	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	3		T237	1		T137	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T41	3		T151	15		T232	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T137	3		T285	6		T255	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	7		T20	9		T118	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T43	7		T197	4		T153	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T107	11		T158	12		T228	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T111	9		T277	1		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T43	14		T38	7		T51	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T38	6		T118	12		T235	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T24	13		T151	14		T228	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T102	8		T160	1		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T108	1		T110	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T14	1		T15	2		T23	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T131	13		T109	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T148	2		T198	1		T235	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T16	16		T56	3		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T50	4		T226	1		T245	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T118	1		T132	1		T110	31
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	4		T237	2		T282	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T20	10		T41	6		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T43	8		T108	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	9		T17	1		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T102	2		T109	1		T197	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T107	12		T43	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T111	10		T127	1		T247	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T43	15		T38	8		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T38	7		T118	13		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T24	15		T146	1		T149	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T39	3		T264	13		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T119	1		T289	17		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17472	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T56	7		T336	2		T252	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T102	2		T201	8		T265	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T110	9		T195	3		T136	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T14	6		T15	27		T59	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T131	10		T109	2		T112	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T198	14		T235	14		T154	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T56	13		T225	1		T124	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	3		T245	2		T246	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T110	28		T152	12		T114	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T39	2		T282	9		T287	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T20	8		T41	4		T223	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T43	9		T298	9		T255	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	1		T123	20		T122	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T197	1		T153	10		T154	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T40	8		T133	10		T198	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T111	9		T247	2		T277	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T43	14		T38	2		T51	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T38	2		T118	11		T56	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T146	10		T168	10		T239	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T39	2		T264	12		T199	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T55	5		T109	4		T122	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T56	5		T302	5		T296	24

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T39	3		T165	3		T199	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T119	1		T149	1		T239	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T293	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T110	1		T294	2		T297	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T102	8		T55	8		T109	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T108	1		T56	7		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T14	1		T15	2		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T109	1		T224	1		T124	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T148	2		T198	1		T235	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T16	16		T131	13		T56	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T50	4		T226	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T118	1		T132	1		T110	31
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	4		T245	1		T237	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T41	6		T223	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T108	1		T132	1		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	9		T17	1		T20	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T102	2		T43	8		T197	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T107	12		T43	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T109	1		T111	10		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T43	15		T38	8		T51	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T38	7		T118	13		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T24	15		T146	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T39	2		T199	7		T257	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T239	8		T230	11		T341	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T110	9		T297	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T102	2		T55	5		T109	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T56	5		T195	3		T136	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	945	1			T14	6		T15	27		T59	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T109	2		T124	16		T125	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T198	14		T235	14		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T131	10		T56	13		T225	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T50	3		T246	2		T277	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T110	28		T124	12		T152	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T39	2		T245	2		T282	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T41	4		T223	2		T133	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T287	10		T298	9		T255	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	1		T20	8		T40	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T43	9		T197	1		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	8		T133	10		T198	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T111	9		T277	1		T229	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T43	14		T38	2		T51	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T38	2		T118	11		T56	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T146	10		T168	10		T136	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27