Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22523

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

3109

1

T13

10

T16

16

T17

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20247

1

T6

1

T7

2

T26

1

auto[1]

5385

1

T13

10

T14

7

T15

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	391	1			T51	23		T40	9		T235	32
values[0]	41	1			T340	17		T231	9		T344	15
values[1]	631	1			T13	10		T38	9		T118	25
values[2]	481	1			T223	3		T43	17		T50	7
values[3]	700	1			T102	10		T108	1		T55	13
values[4]	644	1			T38	10		T108	1		T132	1
values[5]	2795	1			T14	7		T15	29		T23	3
values[6]	592	1			T24	11		T58	1		T43	29
values[7]	501	1			T16	16		T102	2		T107	12
values[8]	564	1			T17	1		T24	4		T41	10
values[9]	848	1			T20	18		T43	1		T39	6
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	578	1			T13	10		T223	3		T43	17
values[1]	583	1			T50	7		T225	3		T110	33
values[2]	644	1			T102	10		T108	1		T55	13
values[3]	2739	1			T14	7		T15	29		T23	3
values[4]	682	1			T108	1		T131	23		T118	5
values[5]	554	1			T24	11		T58	1		T43	29
values[6]	510	1			T16	16		T102	2		T107	12
values[7]	512	1			T17	1		T24	4		T41	10
values[8]	1023	1			T20	18		T43	1		T146	11
values[9]	129	1			T240	19		T173	1		T306	10
minimum	17678	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T223	3		T38	3		T148	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	3		T43	10		T118	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T50	4		T225	2		T110	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T112	1		T134	1		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T102	5		T108	1		T123	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T55	6		T111	10		T151	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T14	7		T15	29		T23	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T119	1		T125	9		T126	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T108	1		T118	1		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T131	11		T56	6		T124	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T24	1		T109	5		T197	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T58	1		T43	15		T56	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T107	1		T108	1		T109	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T16	1		T102	2		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T41	7		T39	3		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T17	1		T24	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T20	9		T43	1		T146	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T56	11		T40	9		T133	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T306	10		T283	3		T342	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T240	10		T173	1		T352	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17356	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T322	14		T263	1		T353	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T38	6		T148	6		T135	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	7		T43	7		T118	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T50	3		T225	1		T110	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T237	11		T264	12		T284	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T102	5		T126	12		T154	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	7		T111	9		T151	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T25	26		T115	21		T38	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T125	1		T126	1		T250	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T118	4		T39	2		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T131	12		T56	6		T124	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T24	10		T197	4		T137	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T43	14		T56	2		T110	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T107	11		T234	2		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T16	15		T134	8		T238	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	3		T39	3		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T24	3		T148	1		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T20	9		T51	10		T154	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T158	12		T235	27		T124	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T342	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T240	9		T267	3		T343	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T220	6		T129	12		T256	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T51	13		T247	11		T306	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	9		T235	15		T265	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T344	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T340	13		T231	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T38	3		T118	1		T148	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	3		T118	12		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T223	3		T50	4		T110	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T43	10		T112	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T102	5		T108	1		T225	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T55	6		T151	1		T239	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T38	3		T108	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T119	1		T111	10		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T14	7		T15	29		T23	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T56	6		T124	17		T126	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T24	1		T197	4		T152	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T58	1		T43	15		T131	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T107	1		T108	1		T109	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T102	2		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	7		T146	11		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	1		T24	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T20	9		T43	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T56	11		T133	11		T109	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T51	10		T247	11		T301	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T235	17		T251	8		T130	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T340	4		T231	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T38	6		T148	6		T254	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	7		T118	12		T135	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T50	3		T110	18		T135	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T43	7		T237	11		T251	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T102	5		T225	1		T228	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T55	7		T151	15		T239	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T38	7		T151	14		T126	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T111	9		T151	9		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T25	26		T115	21		T118	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T56	6		T124	13		T126	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T24	10		T197	4		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	14		T131	12		T56	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T107	11		T234	2		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T16	15		T238	2		T345	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T41	3		T40	1		T153	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T24	3		T148	1		T134	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T20	9		T39	3		T154	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T158	12		T235	10		T124	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T223	1		T38	7		T148	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	9		T43	8		T118	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T50	4		T225	2		T110	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T112	1		T134	1		T237	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T102	8		T108	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T55	8		T111	10		T151	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T14	1		T15	2		T23	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T119	1		T125	2		T126	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T108	1		T118	5		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T131	13		T56	7		T124	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T24	11		T109	1		T197	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T58	1		T43	15		T56	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T107	12		T108	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	16		T102	2		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	6		T39	4		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T17	1		T24	4		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T20	10		T43	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T56	1		T40	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T306	1		T283	1		T342	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T240	10		T173	1		T352	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17462	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T322	1		T263	1		T353	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T223	2		T38	2		T148	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	1		T43	9		T118	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T50	3		T225	1		T110	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T264	12		T200	1		T230	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T102	2		T123	8		T126	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T55	5		T111	9		T239	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T14	6		T15	27		T59	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T125	8		T126	2		T287	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T39	2		T40	3		T112	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T131	10		T56	5		T124	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T109	4		T197	1		T152	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T43	14		T56	13		T110	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T109	2		T234	1		T240	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	8		T265	12		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T41	4		T39	2		T168	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T110	9		T282	9		T176	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T20	8		T146	10		T51	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T56	10		T40	8		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T306	9		T283	2		T354	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T240	9		T267	1		T343	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T245	6		T271	14		T355	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T322	13		T129	10		T256	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T51	11		T247	12		T306	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	1		T235	18		T265	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T344	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T340	5		T231	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T38	7		T118	1		T148	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	9		T118	13		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T223	1		T50	4		T110	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T43	8		T112	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T102	8		T108	1		T225	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T55	8		T151	16		T239	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T38	8		T108	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T119	1		T111	10		T151	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T14	1		T15	2		T23	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T56	7		T124	14		T126	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T24	11		T197	7		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T58	1		T43	15		T131	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T107	12		T108	1		T109	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	16		T102	2		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T41	6		T146	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T17	1		T24	4		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T20	10		T43	1		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T56	1		T133	1		T109	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T51	12		T247	10		T306	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T40	8		T235	14		T265	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T344	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T340	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T38	2		T148	9		T245	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	1		T118	11		T133	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T223	2		T50	3		T110	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T43	9		T200	1		T230	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T102	2		T225	1		T123	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T55	5		T239	8		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T38	2		T133	10		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T111	9		T125	8		T232	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T14	6		T15	27		T59	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T56	5		T124	16		T126	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T197	1		T152	12		T287	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T43	14		T131	10		T56	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T109	6		T234	1		T240	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T136	13		T265	12		T238	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T41	4		T146	10		T168	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T110	9		T134	8		T282	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	8		T39	2		T152	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T56	10		T133	10		T198	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27