Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22464

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

3168

1

T13

10

T17

1

T20

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20013

1

T6

1

T7

2

T26

1

auto[1]

5619

1

T14

7

T15

29

T16

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	304	1			T108	1		T158	13		T162	1
values[0]	22	1			T289	17		T274	5		-	-
values[1]	489	1			T102	10		T118	1		T39	5
values[2]	405	1			T108	1		T132	2		T109	5
values[3]	582	1			T24	11		T102	2		T56	16
values[4]	598	1			T55	13		T132	1		T119	1
values[5]	667	1			T13	10		T223	3		T43	1
values[6]	556	1			T16	16		T108	1		T39	6
values[7]	804	1			T43	29		T38	19		T118	5
values[8]	2798	1			T14	7		T15	29		T17	1
values[9]	963	1			T58	1		T107	12		T146	11
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	453	1			T102	10		T118	1		T39	5
values[1]	532	1			T108	1		T132	1		T109	5
values[2]	498	1			T24	11		T102	2		T56	16
values[3]	635	1			T55	13		T56	12		T132	1
values[4]	643	1			T13	10		T16	16		T223	3
values[5]	623	1			T38	19		T108	1		T39	6
values[6]	2742	1			T14	7		T15	29		T23	3
values[7]	812	1			T17	1		T20	18		T24	4
values[8]	989	1			T107	12		T108	1		T146	11
values[9]	101	1			T158	13		T224	1		T235	24
minimum	17604	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T102	5		T118	1		T39	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T132	1		T261	1		T114	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T108	1		T132	1		T197	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T109	5		T124	17		T152	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T24	1		T56	14		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T102	2		T175	3		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T55	6		T56	6		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T112	10		T134	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	1		T43	1		T110	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	3		T223	3		T118	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	3		T39	3		T133	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	3		T108	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T14	7		T15	29		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T131	11		T118	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T24	1		T43	10		T109	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T17	1		T20	9		T58	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T50	4		T160	1		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T107	1		T108	1		T146	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T158	1		T235	14		T136	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T224	1		T279	1		T179	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17329	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T237	1		T275	1		T220	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T102	5		T39	2		T148	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T114	14		T233	7		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T197	4		T126	12		T277	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T124	13		T244	12		T256	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T24	10		T56	2		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T175	9		T254	1		T264	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T55	7		T56	6		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T112	10		T240	16		T254	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	15		T110	11		T122	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	7		T118	12		T148	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T38	7		T39	3		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T38	6		T151	14		T124	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T25	26		T43	14		T115	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T131	12		T118	4		T135	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T24	3		T43	7		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T20	9		T41	3		T51	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T50	3		T235	17		T153	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T107	11		T225	1		T125	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T158	12		T235	10		T272	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T279	3		T242	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T237	11		T220	14		T176	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T158	1		T235	14		T136	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T108	1		T162	1		T134	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T289	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T274	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T102	5		T118	1		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T261	1		T114	13		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T108	1		T132	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T132	1		T109	5		T152	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T24	1		T56	14		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T102	2		T124	17		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T55	6		T132	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T112	10		T240	15		T254	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T43	1		T56	6		T110	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	3		T223	3		T118	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T16	1		T39	3		T133	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T108	1		T111	1		T123	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T43	15		T38	3		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T38	3		T118	1		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T14	7		T15	29		T23	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T17	1		T20	9		T41	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T50	4		T119	1		T111	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T58	1		T107	1		T146	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T158	12		T235	10		T187	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T134	8		T279	3		T165	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T289	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T274	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T102	5		T39	2		T148	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T114	14		T237	11		T233	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T236	10		T191	6		T251	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T244	12		T129	12		T257	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T24	10		T56	2		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T124	13		T175	9		T254	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T55	7		T134	9		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T112	10		T240	16		T254	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T56	6		T110	11		T122	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	7		T118	12		T201	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	15		T39	3		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T148	1		T124	11		T135	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	14		T38	7		T110	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T38	6		T118	4		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T24	3		T25	26		T43	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	9		T41	3		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T50	3		T111	9		T235	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T107	11		T51	10		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T102	8		T118	1		T39	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T132	1		T261	1		T114	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T108	1		T132	1		T197	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T109	1		T124	14		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T24	11		T56	3		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T102	2		T175	10		T254	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T55	8		T56	7		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T112	11		T134	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	16		T43	1		T110	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	9		T223	1		T118	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T38	8		T39	4		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T38	7		T108	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T14	1		T15	2		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T131	13		T118	5		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T24	4		T43	8		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	1		T20	10		T58	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T50	4		T160	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T107	12		T108	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T158	13		T235	11		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T224	1		T279	4		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17484	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T237	12		T275	1		T220	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T102	2		T39	2		T148	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T114	12		T282	9		T233	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T197	1		T126	12		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T109	4		T124	16		T152	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T56	13		T133	10		T134	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T175	2		T264	14		T266	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T55	5		T56	5		T154	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T112	9		T240	14		T254	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T110	14		T122	11		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	1		T223	2		T118	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T38	2		T39	2		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T38	2		T123	12		T124	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T14	6		T15	27		T59	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T131	10		T135	3		T239	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	9		T109	2		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T20	8		T41	4		T51	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T50	3		T122	11		T235	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T146	10		T56	10		T40	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T235	13		T136	7		T272	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T179	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T244	12		T300	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T220	7		T176	13		T356	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T158	13		T235	11		T136	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T108	1		T162	1		T134	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T289	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T274	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T102	8		T118	1		T39	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T261	1		T114	15		T237	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T108	1		T132	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T132	1		T109	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T24	11		T56	3		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T102	2		T124	14		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T55	8		T132	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T112	11		T240	17		T254	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T43	1		T56	7		T110	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	9		T223	1		T118	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T16	16		T39	4		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T108	1		T111	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T43	15		T38	8		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T38	7		T118	5		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T14	1		T15	2		T23	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T17	1		T20	10		T41	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T50	4		T119	1		T111	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T58	1		T107	12		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T235	13		T136	7		T278	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T134	8		T322	13		T283	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T274	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T102	2		T39	2		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T114	12		T282	9		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T245	6		T246	10		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T109	4		T152	6		T195	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T56	13		T133	10		T197	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T124	16		T175	2		T200	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T55	5		T134	5		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T112	9		T240	14		T254	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T56	5		T110	14		T122	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	1		T223	2		T118	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	2		T133	9		T238	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T123	12		T124	12		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T43	14		T38	2		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	2		T135	3		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T14	6		T15	27		T59	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T20	8		T41	4		T131	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	3		T111	9		T122	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T146	10		T51	12		T56	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27