Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1		T13	9	T56	1	T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1		T24	4	T102	2	T38	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1		T118	13	T40	1	T110	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1		T110	19	T119	1	T197	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1		T41	6	T133	1	T151	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1		T43	15	T158	13	T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1		T43	9	T39	3	T56	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1		T108	1	T50	4	T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1		T17	1	T38	8	T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1		T20	10	T108	1	T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1		T40	2	T119	1	T111	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1		T113	1	T198	1	T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1		T14	1	T15	2	T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1		T58	1	T146	1	T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1		T16	16	T102	8	T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1		T24	11	T131	13	T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1		T225	2	T119	1	T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1		T107	12	T55	8	T56	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1		T251	2	T248	10	T252	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1		T173	1	T250	9	T253	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17455	1		T6	1	T7	2	T26	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1		T13	1	T56	10	T133	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1		T38	2	T123	8	T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1		T118	11	T40	8	T110	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1		T110	14	T197	1	T254	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1		T41	4	T133	10	T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1		T43	14	T122	11	T201	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1		T43	9	T39	2	T56	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1		T50	3	T109	2	T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1		T38	2	T112	9	T136	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1		T20	8	T39	2	T122	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1		T111	9	T236	15	T264	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1		T198	5	T152	12	T191	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	965	1		T14	6	T15	27	T59	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1		T146	10	T110	9	T265	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1		T102	2	T223	2	T51	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1		T131	10	T168	10	T235	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1		T225	1	T234	1	T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1		T55	5	T56	5	T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1		T199	7	T266	12	T267	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1		T250	2	T257	11	T268	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1		T259	7	-	-	-	-

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1		T248	19	T249	1	-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1		T152	1	T154	12	T259	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1		T108	1	T260	1	-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1		T56	1	T133	1	T148	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1		T38	7	T123	1	T227	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1		T13	9	T118	13	T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1		T24	4	T102	2	T110	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1		T132	1	T133	1	T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1		T43	15	T197	7	T158	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1		T41	6	T43	9	T56	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1		T108	1	T109	1	T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1		T38	8	T118	1	T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1		T20	10	T50	4	T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1		T17	1	T40	2	T195	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1		T108	1	T122	17	T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1		T118	5	T40	2	T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1		T58	1	T149	1	T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1		T223	1	T113	1	T261	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1		T24	11	T131	13	T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1557	1		T14	1	T15	2	T16	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1		T107	12	T55	8	T56	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1		T6	1	T7	2	T26	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1		T152	6	T154	11	T259	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1		T56	10	T133	10	T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1		T38	2	T123	8	T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1		T13	1	T118	11	T40	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1		T110	14	T269	1	T270	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1		T133	10	T232	7	T185	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1		T43	14	T197	1	T238	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1		T41	4	T43	9	T56	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1		T109	2	T122	11	T135	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1		T38	2	T39	2	T112	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1		T20	8	T50	3	T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1		T154	9	T236	15	T192	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1		T122	11	T198	5	T245	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1		T40	3	T111	9	T134	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1		T152	12	T233	11	T271	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1		T223	2	T114	12	T191	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1		T131	10	T146	10	T110	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1		T14	6	T15	27	T102	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1		T55	5	T56	5	T133	9

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

T26

auto[1]

auto[0]

3448

T13

T14

T15