Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22352

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

3280

1

T13

10

T17

1

T20

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20100

1

T6

1

T7

2

T26

1

auto[1]

5532

1

T14

7

T15

29

T16

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T272	26		-	-		-	-
values[0]	18	1			T137	10		T273	3		T274	5
values[1]	475	1			T102	10		T108	1		T118	1
values[2]	468	1			T132	2		T109	5		T112	1
values[3]	486	1			T24	11		T102	2		T56	16
values[4]	549	1			T55	13		T132	1		T119	1
values[5]	767	1			T13	10		T223	3		T43	1
values[6]	555	1			T16	16		T108	1		T118	5
values[7]	769	1			T43	29		T38	19		T39	6
values[8]	2836	1			T14	7		T15	29		T17	1
values[9]	1239	1			T58	1		T41	10		T107	12
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	608	1			T102	10		T118	1		T39	5
values[1]	527	1			T108	1		T109	5		T197	8
values[2]	514	1			T24	11		T102	2		T56	16
values[3]	648	1			T43	1		T118	24		T55	13
values[4]	670	1			T13	10		T16	16		T223	3
values[5]	596	1			T38	19		T108	1		T39	6
values[6]	2736	1			T14	7		T15	29		T23	3
values[7]	787	1			T17	1		T20	18		T24	4
values[8]	914	1			T107	12		T108	1		T146	11
values[9]	186	1			T225	3		T158	13		T122	12
minimum	17446	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T102	5		T118	1		T39	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T132	1		T261	1		T114	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T108	1		T197	4		T126	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T109	5		T112	1		T124	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T24	1		T56	14		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T102	2		T152	7		T175	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T43	1		T55	6		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T118	12		T112	10		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	1		T56	6		T110	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	3		T223	3		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T38	3		T39	3		T133	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T38	3		T108	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T14	7		T15	29		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T131	11		T118	1		T133	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T24	1		T43	10		T109	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	1		T20	9		T58	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T50	4		T235	15		T245	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T107	1		T108	1		T146	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T158	1		T235	14		T136	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T225	2		T122	12		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T275	1		T276	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T102	5		T39	2		T148	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T114	14		T237	11		T233	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T197	4		T126	12		T277	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T124	13		T244	12		T256	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T24	10		T56	2		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T175	9		T254	1		T264	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T55	7		T237	1		T277	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T118	12		T112	10		T154	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	15		T56	6		T110	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	7		T148	1		T135	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	7		T39	3		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T38	6		T151	14		T124	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T25	26		T43	14		T115	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T131	12		T118	4		T135	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	3		T43	7		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T20	9		T41	3		T51	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T50	3		T235	17		T153	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T107	11		T125	1		T126	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T158	12		T235	10		T278	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T225	1		T279	3		T280	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T272	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T137	1		T273	2		T274	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T102	5		T108	1		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T261	1		T114	13		T237	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T132	1		T245	7		T195	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T132	1		T109	5		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T24	1		T56	14		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T102	2		T124	17		T175	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T55	6		T132	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T134	1		T240	15		T254	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T43	1		T56	6		T110	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	3		T223	3		T118	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T16	1		T133	10		T238	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T108	1		T118	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T43	15		T38	3		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	3		T133	11		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T14	7		T15	29		T23	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T17	1		T20	9		T131	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T119	1		T111	10		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T58	1		T41	7		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T272	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T137	9		T273	1		T274	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T102	5		T39	2		T148	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T114	14		T237	11		T233	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T277	1		T236	10		T191	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T244	12		T129	12		T266	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T24	10		T56	2		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T124	13		T175	9		T254	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T55	7		T134	9		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T240	16		T254	11		T264	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T56	6		T110	11		T122	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	7		T118	12		T112	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T16	15		T238	2		T281	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T118	4		T148	1		T124	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	14		T38	7		T39	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T38	6		T151	14		T239	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T24	3		T25	26		T43	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T20	9		T131	12		T135	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T111	9		T158	12		T235	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T41	3		T107	11		T51	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T102	8		T118	1		T39	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T132	1		T261	1		T114	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T108	1		T197	7		T126	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T109	1		T112	1		T124	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T24	11		T56	3		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T102	2		T152	1		T175	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T43	1		T55	8		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T118	13		T112	11		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T16	16		T56	7		T110	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	9		T223	1		T148	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T38	8		T39	4		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T38	7		T108	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T14	1		T15	2		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T131	13		T118	5		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T24	4		T43	8		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T17	1		T20	10		T58	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T50	4		T235	18		T245	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T107	12		T108	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T158	13		T235	11		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T225	2		T122	1		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T275	1		T276	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T102	2		T39	2		T148	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T114	12		T282	9		T233	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T197	1		T126	12		T195	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T109	4		T124	16		T244	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T56	13		T133	10		T134	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T152	6		T175	2		T264	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T55	5		T277	1		T265	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T118	11		T112	9		T154	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T56	5		T110	14		T122	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	1		T223	2		T135	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T38	2		T39	2		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T38	2		T123	12		T124	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T14	6		T15	27		T59	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T131	10		T133	10		T135	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T43	9		T109	2		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	8		T41	4		T51	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T50	3		T235	14		T245	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T146	10		T56	10		T40	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T235	13		T136	7		T278	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T225	1		T122	11		T280	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T272	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T137	10		T273	3		T274	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T102	8		T108	1		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T261	1		T114	15		T237	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T132	1		T245	1		T195	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T132	1		T109	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T24	11		T56	3		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T102	2		T124	14		T175	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T55	8		T132	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T134	1		T240	17		T254	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T43	1		T56	7		T110	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T13	9		T223	1		T118	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	16		T133	1		T238	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T108	1		T118	5		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	15		T38	8		T39	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T38	7		T133	1		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T14	1		T15	2		T23	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	1		T20	10		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T119	1		T111	10		T158	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	422	1			T58	1		T41	6		T107	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T272	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T274	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T102	2		T39	2		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T114	12		T233	11		T220	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T245	6		T195	3		T246	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T109	4		T152	6		T282	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T56	13		T133	10		T197	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T124	16		T175	2		T200	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T55	5		T134	5		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T240	14		T254	10		T264	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T56	5		T110	14		T122	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T223	2		T118	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T133	9		T238	12		T283	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T123	12		T124	12		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T43	14		T38	2		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T38	2		T133	10		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T14	6		T15	27		T59	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T20	8		T131	10		T135	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T111	9		T235	27		T245	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T41	4		T146	10		T51	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27