Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22556

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

3076

1

T20

18

T24

15

T58

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20188

1

T6

1

T7

2

T26

1

auto[1]

5444

1

T14

7

T15

29

T16

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	291	1			T225	3		T148	2		T151	15
values[1]	547	1			T38	9		T108	1		T56	11
values[2]	669	1			T13	10		T24	4		T102	2
values[3]	449	1			T43	29		T132	1		T133	11
values[4]	652	1			T41	10		T43	18		T108	1
values[5]	639	1			T20	18		T38	10		T118	1
values[6]	541	1			T17	1		T108	1		T119	1
values[7]	734	1			T58	1		T146	11		T118	5
values[8]	679	1			T24	11		T223	3		T131	23
values[9]	2987	1			T14	7		T15	29		T16	16
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	528	1			T13	10		T24	4		T102	2
values[1]	639	1			T118	24		T40	9		T110	59
values[2]	499	1			T41	10		T43	29		T133	11
values[3]	631	1			T43	18		T108	1		T50	7
values[4]	621	1			T17	1		T20	18		T38	10
values[5]	627	1			T119	1		T111	19		T113	1
values[6]	2664	1			T14	7		T15	29		T23	3
values[7]	748	1			T16	16		T24	11		T102	10
values[8]	947	1			T107	12		T55	13		T56	12
values[9]	102	1			T173	1		T250	11		T248	10
minimum	17626	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	3		T56	11		T133	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T24	1		T102	2		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T118	12		T40	9		T110	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T110	15		T197	4		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T41	7		T133	11		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T43	15		T119	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T43	11		T39	3		T56	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T108	1		T50	4		T109	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T17	1		T38	3		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T20	9		T108	1		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T119	1		T111	10		T195	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T113	1		T198	6		T152	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T14	7		T15	29		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T58	1		T146	11		T110	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T16	1		T102	5		T223	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T24	1		T131	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T225	2		T119	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T107	1		T55	6		T56	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T248	1		T252	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T173	1		T250	3		T199	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17329	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T108	1		T247	13		T238	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	7		T148	6		T154	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T24	3		T38	6		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T118	12		T110	11		T124	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T110	18		T197	4		T254	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T41	3		T151	15		T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T43	14		T158	12		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	7		T39	2		T56	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T50	3		T135	10		T283	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T38	7		T112	10		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T20	9		T39	3		T122	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T111	9		T236	13		T264	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T228	5		T244	12		T251	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T25	26		T115	21		T118	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T135	6		T220	6		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T16	15		T102	5		T51	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T24	10		T131	12		T235	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T225	1		T151	14		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T107	11		T55	7		T56	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T248	9		T252	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T250	8		T267	3		T257	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T247	11		T238	9		T284	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T225	2		T151	1		T228	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T148	1		T154	17		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T56	11		T133	11		T148	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	3		T108	1		T123	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	3		T118	12		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T24	1		T102	2		T110	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T132	1		T133	11		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T43	15		T119	1		T197	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T41	7		T43	11		T56	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T108	1		T50	4		T122	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T38	3		T118	1		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T20	9		T39	3		T109	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T17	1		T119	1		T195	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T108	1		T122	12		T198	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T118	1		T40	5		T111	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T58	1		T146	11		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T223	3		T113	1		T114	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T24	1		T131	11		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T14	7		T15	29		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T107	1		T55	6		T56	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T225	1		T151	14		T228	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T148	1		T154	16		T165	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T148	6		T154	11		T137	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T38	6		T227	9		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	7		T118	12		T110	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T24	3		T110	18		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T232	7		T262	11		T185	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T43	14		T197	4		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T41	3		T43	7		T56	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T50	3		T135	10		T201	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	7		T39	2		T112	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T20	9		T39	3		T127	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T154	11		T236	13		T285	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T122	16		T244	12		T251	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T118	4		T40	2		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T135	6		T228	5		T129	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T114	14		T254	11		T191	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T24	10		T131	12		T235	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T16	15		T25	26		T102	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T107	11		T55	7		T56	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	9		T56	1		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T24	4		T102	2		T38	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T118	13		T40	1		T110	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T110	19		T197	7		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	6		T133	1		T151	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T43	15		T119	1		T158	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T43	9		T39	3		T56	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T108	1		T50	4		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	1		T38	8		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T20	10		T108	1		T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T119	1		T111	10		T195	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T113	1		T198	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T14	1		T15	2		T23	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T58	1		T146	1		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	16		T102	8		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T24	11		T131	13		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T225	2		T119	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T107	12		T55	8		T56	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T248	10		T252	7		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T173	1		T250	9		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17506	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T108	1		T247	12		T238	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T13	1		T56	10		T133	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T38	2		T123	8		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T118	11		T40	8		T110	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T110	14		T197	1		T254	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T41	4		T133	10		T134	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T43	14		T122	11		T201	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T43	9		T39	2		T56	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T50	3		T109	2		T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	2		T112	9		T136	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T20	8		T39	2		T122	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T111	9		T236	15		T264	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T198	5		T152	12		T244	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T14	6		T15	27		T59	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T146	10		T110	9		T135	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T102	2		T223	2		T51	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	10		T168	10		T235	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T225	1		T234	1		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T55	5		T56	5		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T250	2		T199	7		T267	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T152	6		T278	2		T259	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T247	12		T238	7		T200	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T225	2		T151	15		T228	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T148	2		T154	17		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T56	1		T133	1		T148	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T38	7		T108	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	9		T118	13		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T24	4		T102	2		T110	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T132	1		T133	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T43	15		T119	1		T197	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T41	6		T43	9		T56	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T108	1		T50	4		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	8		T118	1		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T20	10		T39	4		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T17	1		T119	1		T195	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T108	1		T122	17		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T118	5		T40	4		T111	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T58	1		T146	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T223	1		T113	1		T114	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T24	11		T131	13		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T14	1		T15	2		T16	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T107	12		T55	8		T56	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T225	1		T264	14		T286	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T154	16		T271	14		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T56	10		T133	10		T148	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T38	2		T123	8		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	1		T118	11		T40	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T110	14		T250	13		T269	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T133	10		T232	7		T185	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T43	14		T197	1		T238	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T41	4		T43	9		T56	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T50	3		T122	11		T135	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T38	2		T39	2		T112	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T20	8		T39	2		T109	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T154	9		T236	15		T192	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T122	11		T198	5		T245	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T40	3		T111	9		T134	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T146	10		T152	12		T135	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T223	2		T114	12		T287	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T131	10		T110	9		T168	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T14	6		T15	27		T102	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T55	5		T56	5		T133	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27