Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22658

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

2974

1

T20

18

T58

1

T102

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19742

1

T6

1

T7

2

T26

1

auto[1]

5890

1

T13

3

T14

7

T15

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	462	1			T13	3		T18	3		T21	7
values[0]	69	1			T227	33		T299	11		T300	15
values[1]	500	1			T20	18		T108	1		T132	1
values[2]	2628	1			T14	7		T15	29		T23	3
values[3]	617	1			T17	1		T102	2		T43	17
values[4]	610	1			T108	1		T50	7		T51	23
values[5]	551	1			T13	10		T24	11		T151	16
values[6]	696	1			T41	10		T43	29		T131	23
values[7]	595	1			T58	1		T223	3		T118	1
values[8]	771	1			T43	1		T38	9		T118	24
values[9]	1098	1			T16	16		T24	4		T102	10
minimum	17035	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	591	1			T20	18		T108	1		T132	1
values[1]	2634	1			T14	7		T15	29		T23	3
values[2]	735	1			T17	1		T102	2		T43	17
values[3]	537	1			T13	10		T108	1		T51	23
values[4]	651	1			T24	11		T43	29		T39	6
values[5]	585	1			T41	10		T131	23		T133	10
values[6]	700	1			T58	1		T223	3		T118	25
values[7]	733	1			T43	1		T38	9		T39	5
values[8]	813	1			T16	16		T24	4		T102	10
values[9]	163	1			T56	12		T133	11		T123	9
minimum	17490	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T109	1		T119	1		T136	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T20	9		T108	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T14	7		T15	29		T23	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T108	1		T148	1		T126	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T17	1		T43	10		T50	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T102	2		T38	3		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	3		T119	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T108	1		T51	13		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	1		T39	3		T110	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T43	15		T261	1		T239	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	7		T109	3		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T131	11		T133	10		T110	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T223	3		T118	12		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T58	1		T118	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T132	1		T40	9		T111	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	1		T38	3		T39	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T16	1		T24	1		T102	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	1		T111	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T56	6		T133	11		T286	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T123	9		T235	14		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17323	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T180	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T191	9		T256	7		T302	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T20	9		T112	10		T134	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T25	26		T107	11		T115	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T148	1		T126	12		T135	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T43	7		T50	3		T56	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T38	7		T118	4		T225	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	7		T237	1		T247	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T51	10		T124	11		T232	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	10		T39	3		T110	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T43	14		T239	11		T254	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	3		T158	12		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T131	12		T137	3		T286	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T118	12		T151	14		T201	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T126	1		T237	11		T277	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T111	9		T122	16		T277	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	6		T39	2		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T16	15		T24	3		T102	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	1		T114	14		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T56	6		T286	3		T165	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T235	10		T301	3		T177	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	1		T7	2		T26	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	440	1			T13	3		T18	3		T21	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T227	17		T299	11		T303	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T300	15		T304	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T109	1		T122	12		T136	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T20	9		T108	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T14	7		T15	29		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T108	1		T148	1		T112	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T17	1		T43	10		T146	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T102	2		T38	3		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T50	4		T56	11		T40	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T108	1		T51	13		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	3		T24	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T224	1		T261	1		T239	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T41	7		T39	3		T110	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T43	15		T131	11		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T223	3		T109	3		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T58	1		T118	1		T197	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T118	12		T132	1		T40	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T43	1		T38	3		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T16	1		T24	1		T102	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T40	1		T111	1		T123	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16885	1			T13	14		T18	173		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T286	3		T165	2		T188	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T227	16		T303	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T191	9		T176	15		T256	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T20	9		T134	9		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T25	26		T107	11		T115	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T148	1		T112	10		T126	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T43	7		T56	2		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T38	7		T118	4		T225	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T50	3		T40	1		T237	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T51	10		T254	11		T305	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	7		T24	10		T151	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T239	11		T232	7		T283	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T41	3		T39	3		T110	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T43	14		T131	12		T254	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T158	12		T151	14		T240	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T197	4		T126	1		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T118	12		T111	9		T277	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T38	6		T39	2		T148	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T16	15		T24	3		T102	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T40	1		T235	10		T114	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T109	1		T119	1		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T20	10		T108	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T14	1		T15	2		T23	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T108	1		T148	2		T126	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T17	1		T43	8		T50	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T102	2		T38	8		T118	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	9		T119	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T108	1		T51	11		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T24	11		T39	4		T110	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	15		T261	1		T239	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T41	6		T109	1		T158	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T131	13		T133	1		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T223	1		T118	13		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T58	1		T118	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T132	1		T40	1		T111	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	1		T38	7		T39	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T16	16		T24	4		T102	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T40	2		T111	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T56	7		T133	1		T286	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T123	1		T235	11		T301	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17462	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T180	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T136	11		T191	12		T264	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T20	8		T112	9		T134	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T14	6		T15	27		T59	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T126	12		T135	11		T195	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T43	9		T50	3		T56	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T38	2		T225	1		T198	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T13	1		T152	6		T247	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T51	12		T124	12		T232	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	2		T110	14		T134	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T43	14		T239	8		T306	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T41	4		T109	2		T125	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T131	10		T133	9		T110	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T223	2		T118	11		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T126	2		T277	1		T265	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T40	8		T111	9		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T38	2		T39	2		T197	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T102	2		T55	5		T133	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T114	12		T154	9		T244	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T56	5		T133	10		T286	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T123	8		T235	13		T296	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T122	11		T227	16		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	435	1			T13	3		T18	3		T21	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T227	17		T299	1		T303	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T300	1		T304	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T109	1		T122	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T20	10		T108	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T14	1		T15	2		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T108	1		T148	2		T112	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T17	1		T43	8		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T102	2		T38	8		T118	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T50	4		T56	1		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T108	1		T51	11		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	9		T24	11		T151	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T224	1		T261	1		T239	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T41	6		T39	4		T110	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T43	15		T131	13		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T223	1		T109	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T58	1		T118	1		T197	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T118	13		T132	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	1		T38	7		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T16	16		T24	4		T102	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T40	2		T111	1		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17035	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T286	3		T307	13		T188	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T227	16		T299	10		T303	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T300	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T122	11		T136	11		T191	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T20	8		T134	5		T136	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T14	6		T15	27		T59	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T112	9		T198	14		T126	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T43	9		T146	10		T56	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T38	2		T225	1		T124	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T50	3		T56	10		T40	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T51	12		T245	2		T287	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T13	1		T134	8		T154	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T239	8		T232	7		T306	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	4		T39	2		T110	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T43	14		T131	10		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T223	2		T109	2		T198	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T197	1		T126	2		T129	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T118	11		T40	8		T111	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T38	2		T39	2		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T102	2		T55	5		T56	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T123	8		T235	13		T114	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27