Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22116

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

3516

1

T13

10

T16

16

T24

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20112

1

T6

1

T7

2

T26

1

auto[1]

5520

1

T13

10

T14

7

T15

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T308	15		-	-		-	-
values[0]	32	1			T309	1		T310	15		T311	7
values[1]	664	1			T17	1		T20	18		T43	17
values[2]	722	1			T43	30		T132	1		T119	1
values[3]	655	1			T13	10		T24	4		T38	19
values[4]	489	1			T50	7		T109	5		T122	12
values[5]	2526	1			T14	7		T15	29		T23	3
values[6]	657	1			T16	16		T118	24		T39	6
values[7]	553	1			T118	1		T56	16		T40	9
values[8]	781	1			T24	11		T118	5		T132	2
values[9]	1094	1			T102	2		T107	12		T108	1
minimum	17444	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	817	1			T17	1		T20	18		T43	29
values[1]	703	1			T43	18		T131	23		T132	1
values[2]	664	1			T24	4		T38	19		T108	1
values[3]	2482	1			T13	10		T14	7		T15	29
values[4]	560	1			T41	10		T102	10		T223	3
values[5]	657	1			T16	16		T118	25		T39	6
values[6]	541	1			T56	16		T40	9		T133	10
values[7]	875	1			T24	11		T118	5		T132	2
values[8]	762	1			T107	12		T39	5		T55	13
values[9]	121	1			T102	2		T108	1		T110	10
minimum	17450	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	1		T20	9		T146	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T43	15		T51	13		T133	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T43	1		T132	1		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T43	10		T131	11		T225	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T24	1		T38	6		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T123	13		T122	12		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T14	7		T15	29		T23	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	3		T58	1		T50	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T102	5		T151	1		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T41	7		T223	3		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T118	1		T109	3		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	1		T118	12		T39	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T56	14		T198	6		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	9		T133	10		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T118	1		T133	11		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T24	1		T132	2		T234	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T39	3		T55	6		T110	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T107	1		T56	11		T111	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T102	2		T108	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T110	10		T264	4		T271	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T292	1		T312	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T20	9		T56	6		T111	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T43	14		T51	10		T122	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T112	10		T237	1		T236	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T43	7		T131	12		T225	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T24	3		T38	13		T263	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T235	17		T227	9		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T25	26		T115	21		T54	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	7		T50	3		T247	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T102	5		T151	15		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T41	3		T40	2		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T124	11		T240	10		T175	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	15		T118	12		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T56	2		T277	1		T313	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T235	10		T126	12		T240	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T118	4		T158	12		T124	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T24	10		T234	2		T254	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T39	2		T55	7		T110	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T107	11		T237	11		T314	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T137	2		T172	8		T315	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T316	2		T317	8		T318	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T292	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T308	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T309	1		T319	1		T320	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T310	1		T311	1		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T17	1		T20	9		T146	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T43	10		T131	11		T51	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	1		T132	1		T197	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T43	15		T119	1		T148	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T24	1		T38	6		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	3		T225	2		T123	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T109	5		T321	1		T251	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T50	4		T122	12		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T14	7		T15	29		T23	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T58	1		T41	7		T223	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T109	3		T149	1		T124	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T16	1		T118	12		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T118	1		T56	14		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T40	9		T133	10		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T118	1		T133	11		T198	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T24	1		T132	2		T261	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T102	2		T108	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T107	1		T56	11		T110	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17294	1			T13	17		T18	176		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T308	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T319	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T310	14		T311	6		T292	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	9		T56	6		T111	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T43	7		T131	12		T51	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T197	4		T112	10		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T43	14		T148	6		T122	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T24	3		T38	13		T114	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	7		T225	1		T235	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T251	8		T165	4		T257	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T50	3		T127	11		T232	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T25	26		T102	5		T115	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T41	3		T40	1		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T124	11		T254	1		T310	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T16	15		T118	12		T39	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T56	2		T158	12		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T235	10		T126	12		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T118	4		T124	13		T240	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T24	10		T234	2		T240	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T39	2		T55	7		T110	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T107	11		T237	11		T286	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T17	1		T20	10		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T43	15		T51	11		T133	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T43	1		T132	1		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T43	8		T131	13		T225	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	4		T38	15		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T123	1		T122	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T14	1		T15	2		T23	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	9		T58	1		T50	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T102	8		T151	16		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T41	6		T223	1		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T118	1		T109	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T16	16		T118	13		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T56	3		T198	1		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T40	1		T133	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T118	5		T133	1		T158	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T24	11		T132	2		T234	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T39	3		T55	8		T110	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T107	12		T56	1		T111	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T102	2		T108	1		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T110	1		T264	1		T271	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T292	3		T312	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T20	8		T146	10		T56	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T43	14		T51	12		T133	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T112	9		T236	10		T238	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T43	9		T131	10		T225	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T38	4		T263	2		T280	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T123	12		T122	11		T235	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T14	6		T15	27		T59	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	1		T50	3		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T102	2		T245	6		T195	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T41	4		T223	2		T40	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T109	2		T124	12		T240	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T118	11		T39	2		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T56	13		T198	5		T277	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	8		T133	9		T235	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T133	10		T124	16		T136	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T234	1		T322	6		T254	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T39	2		T55	5		T110	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T56	10		T152	12		T314	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T172	1		T179	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T110	9		T264	3		T271	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T312	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T308	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T309	1		T319	3		T320	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T310	15		T311	7		T292	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T17	1		T20	10		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T43	8		T131	13		T51	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T43	1		T132	1		T197	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T43	15		T119	1		T148	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T24	4		T38	15		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	9		T225	2		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T109	1		T321	1		T251	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T50	4		T122	1		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T14	1		T15	2		T23	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T58	1		T41	6		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T109	1		T149	1		T124	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T16	16		T118	13		T39	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T118	1		T56	3		T158	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	1		T133	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T118	5		T133	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	11		T132	2		T261	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T102	2		T108	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T107	12		T56	1		T110	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T6	1		T7	2		T26	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T320	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T20	8		T146	10		T56	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	9		T131	10		T51	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T197	1		T112	9		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T43	14		T148	9		T122	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	4		T114	12		T238	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	1		T225	1		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T109	4		T251	3		T257	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T50	3		T122	11		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T14	6		T15	27		T102	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T41	4		T223	2		T198	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T109	2		T124	12		T245	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T118	11		T39	2		T40	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T56	13		T240	3		T175	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	8		T133	9		T235	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T133	10		T198	5		T124	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T234	1		T240	9		T322	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T39	2		T55	5		T110	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T56	10		T110	9		T152	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27