Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25632

1

T6

1

T7

2

T26

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22572

1

T6

1

T7

2

T26

1

auto[ADC_CTRL_FILTER_COND_OUT]

3060

1

T20

18

T24

4

T102

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19800

1

T6

1

T7

2

T26

1

auto[1]

5832

1

T13

13

T14

7

T15

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21789

1

T13

20

T14

7

T15

29

auto[1]

3843

1

T6

1

T7

2

T26

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	769	1			T13	3		T18	3		T21	7
values[0]	42	1			T227	33		T303	9		-	-
values[1]	457	1			T20	18		T108	1		T132	1
values[2]	2670	1			T14	7		T15	29		T23	3
values[3]	649	1			T17	1		T102	2		T43	17
values[4]	540	1			T38	10		T108	1		T50	7
values[5]	638	1			T13	10		T24	11		T112	1
values[6]	709	1			T41	10		T43	29		T131	23
values[7]	591	1			T58	1		T223	3		T118	1
values[8]	748	1			T43	1		T38	9		T118	24
values[9]	784	1			T16	16		T24	4		T55	13
minimum	17035	1			T6	1		T7	2		T26	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	389	1			T20	18		T119	1		T134	15
values[1]	2704	1			T14	7		T15	29		T23	3
values[2]	690	1			T17	1		T102	2		T43	17
values[3]	538	1			T13	10		T108	1		T50	7
values[4]	671	1			T24	11		T43	29		T110	26
values[5]	624	1			T41	10		T131	23		T39	6
values[6]	651	1			T58	1		T223	3		T118	25
values[7]	702	1			T43	1		T38	9		T39	5
values[8]	902	1			T16	16		T24	4		T102	10
values[9]	116	1			T56	12		T235	24		T286	7
minimum	17645	1			T6	1		T7	2		T26	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

3448

1

T13

1

T14

6

T15

27

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T153	11		T155	1		T191	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T20	9		T119	1		T134	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T14	7		T15	29		T23	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T107	1		T108	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T17	1		T43	10		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T102	2		T118	1		T56	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	3		T50	4		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T108	1		T51	13		T56	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	1		T134	9		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	15		T110	15		T261	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T41	7		T39	3		T109	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T131	11		T133	10		T110	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T58	1		T223	3		T118	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T118	1		T119	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T43	1		T132	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T38	3		T39	3		T40	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T16	1		T102	5		T55	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	1		T110	15		T111	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T56	6		T235	14		T286	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T186	1		T177	1		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17385	1			T13	17		T18	176		T19	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T108	1		T109	1		T275	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T153	12		T191	9		T243	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T20	9		T134	9		T252	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T25	26		T115	21		T54	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T107	11		T148	1		T112	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	7		T38	7		T225	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T118	4		T56	2		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	7		T50	3		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	10		T237	1		T236	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T24	10		T134	8		T220	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	14		T110	11		T239	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T41	3		T39	3		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T131	12		T151	14		T137	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T118	12		T247	11		T201	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T126	1		T237	11		T277	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T122	16		T277	1		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T38	6		T39	2		T111	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T16	15		T102	5		T55	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T24	3		T110	18		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T56	6		T235	10		T286	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T177	12		T293	13		T296	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	1		T7	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T185	1		T330	6		T331	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	511	1			T13	3		T18	3		T21	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T154	10		T244	16		T251	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T227	17		T303	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T132	1		T122	12		T136	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	9		T108	1		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T14	7		T15	29		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T107	1		T108	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T17	1		T43	10		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T102	2		T118	1		T56	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T38	3		T50	4		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T108	1		T51	13		T56	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	3		T24	1		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T224	1		T261	1		T239	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T41	7		T39	3		T109	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	15		T131	11		T133	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T58	1		T223	3		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T118	1		T119	1		T197	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T43	1		T118	12		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T38	3		T39	3		T40	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T16	1		T55	6		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T24	1		T110	15		T111	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16885	1			T13	14		T18	173		T19	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T102	5		T56	6		T235	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T154	11		T244	12		T251	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T227	16		T303	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T153	12		T191	9		T332	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T20	9		T134	9		T252	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T25	26		T115	21		T54	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T107	11		T148	1		T112	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T43	7		T225	1		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T118	4		T56	2		T235	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T38	7		T50	3		T240	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T51	10		T40	1		T236	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	7		T24	10		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T239	11		T237	1		T232	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T41	3		T39	3		T158	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	14		T131	12		T110	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T247	11		T139	11		T185	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T197	4		T151	14		T126	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T118	12		T277	1		T201	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	6		T39	2		T111	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T16	15		T55	7		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	3		T110	18		T127	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	1		T7	2		T26	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T153	13		T155	1		T191	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T20	10		T119	1		T134	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T14	1		T15	2		T23	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T107	12		T108	1		T148	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T17	1		T43	8		T38	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T102	2		T118	5		T56	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	9		T50	4		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T108	1		T51	11		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T24	11		T134	9		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	15		T110	12		T261	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T41	6		T39	4		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T131	13		T133	1		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T58	1		T223	1		T118	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T118	1		T119	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T43	1		T132	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T38	7		T39	3		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T16	16		T102	8		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T24	4		T110	19		T111	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T56	7		T235	11		T286	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T186	1		T177	13		T293	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17504	1			T6	1		T7	2		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T108	1		T109	1		T275	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T153	10		T191	12		T249	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T20	8		T134	5		T136	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T14	6		T15	27		T59	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T112	9		T126	12		T135	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T43	9		T38	2		T225	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T56	13		T40	3		T198	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T13	1		T50	3		T152	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T51	12		T56	10		T236	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T134	8		T271	14		T255	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T43	14		T110	14		T239	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T41	4		T39	2		T109	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T131	10		T133	9		T110	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T223	2		T118	11		T198	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T126	2		T277	1		T265	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T122	11		T277	1		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T38	2		T39	2		T40	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T102	2		T55	5		T133	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T110	14		T154	9		T244	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T56	5		T235	13		T286	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T296	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T122	11		T227	16		T136	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T287	5		T185	15		T330	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	487	1			T13	3		T18	3		T21	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T154	12		T244	13		T251	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T227	17		T303	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T132	1		T122	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T20	10		T108	1		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T14	1		T15	2		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T107	12		T108	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T17	1		T43	8		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T102	2		T118	5		T56	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T38	8		T50	4		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T108	1		T51	11		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	9		T24	11		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T224	1		T261	1		T239	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T41	6		T39	4		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T43	15		T131	13		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T58	1		T223	1		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T118	1		T119	1		T197	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	1		T118	13		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T38	7		T39	3		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T16	16		T55	8		T40	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T24	4		T110	19		T111	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17035	1			T6	1		T7	2		T26	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T102	2		T56	5		T133	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T154	9		T244	15		T251	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T227	16		T303	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T122	11		T136	13		T153	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T20	8		T134	5		T136	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T14	6		T15	27		T59	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T112	9		T126	12		T195	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T43	9		T225	1		T172	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T56	13		T198	14		T235	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T38	2		T50	3		T152	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T51	12		T56	10		T40	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	1		T134	8		T154	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T239	8		T232	7		T306	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T41	4		T39	2		T109	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	14		T131	10		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T223	2		T198	5		T245	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T197	1		T126	2		T129	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T118	11		T277	1		T201	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T38	2		T39	2		T40	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T55	5		T133	10		T109	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T110	14		T286	7		T229	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22184

1

T6

1

T7

2

T26

1

auto[1]

auto[0]

3448

1

T13

1

T14

6

T15

27