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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.47 98.98 95.70 100.00 100.00 98.18 98.64 90.77


Total test records in report: 915
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T780 /workspace/coverage/default/33.adc_ctrl_filters_polled.1343306463 Jan 14 01:37:01 PM PST 24 Jan 14 01:56:15 PM PST 24 489023018887 ps
T781 /workspace/coverage/default/28.adc_ctrl_stress_all.2154668113 Jan 14 01:36:20 PM PST 24 Jan 14 01:38:01 PM PST 24 42198524765 ps
T782 /workspace/coverage/default/37.adc_ctrl_fsm_reset.2444603435 Jan 14 01:37:53 PM PST 24 Jan 14 01:47:39 PM PST 24 110612351534 ps
T783 /workspace/coverage/default/9.adc_ctrl_stress_all.3200347842 Jan 14 01:34:03 PM PST 24 Jan 14 01:41:02 PM PST 24 369414491215 ps
T231 /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1387732326 Jan 14 01:33:40 PM PST 24 Jan 14 01:45:41 PM PST 24 323335287520 ps
T784 /workspace/coverage/default/42.adc_ctrl_alert_test.2603422568 Jan 14 01:38:52 PM PST 24 Jan 14 01:38:54 PM PST 24 427868999 ps
T785 /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2524792109 Jan 14 01:35:20 PM PST 24 Jan 14 01:38:53 PM PST 24 171506981301 ps
T786 /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1850029511 Jan 14 01:38:11 PM PST 24 Jan 14 01:39:09 PM PST 24 322953100248 ps
T787 /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1034846754 Jan 14 01:36:04 PM PST 24 Jan 14 01:37:14 PM PST 24 52212268095 ps
T788 /workspace/coverage/default/35.adc_ctrl_fsm_reset.2579232918 Jan 14 01:37:39 PM PST 24 Jan 14 01:44:13 PM PST 24 78333548699 ps
T789 /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.817995896 Jan 14 01:33:57 PM PST 24 Jan 14 01:40:40 PM PST 24 332329398395 ps
T303 /workspace/coverage/default/1.adc_ctrl_filters_both.3678919724 Jan 14 01:33:41 PM PST 24 Jan 14 01:54:15 PM PST 24 499401085040 ps
T315 /workspace/coverage/default/34.adc_ctrl_filters_interrupt.937228318 Jan 14 01:37:20 PM PST 24 Jan 14 01:39:17 PM PST 24 334107018958 ps
T790 /workspace/coverage/default/24.adc_ctrl_poweron_counter.1117349322 Jan 14 01:35:33 PM PST 24 Jan 14 01:35:43 PM PST 24 3736226898 ps
T218 /workspace/coverage/default/27.adc_ctrl_fsm_reset.2127336708 Jan 14 01:36:15 PM PST 24 Jan 14 01:42:31 PM PST 24 74954659982 ps
T791 /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3157605386 Jan 14 01:34:35 PM PST 24 Jan 14 01:55:06 PM PST 24 500020566533 ps
T792 /workspace/coverage/default/5.adc_ctrl_stress_all.2161152808 Jan 14 01:33:46 PM PST 24 Jan 14 01:34:33 PM PST 24 42456432999 ps
T793 /workspace/coverage/default/22.adc_ctrl_fsm_reset.3589420743 Jan 14 01:35:08 PM PST 24 Jan 14 01:45:22 PM PST 24 112942194343 ps
T794 /workspace/coverage/default/47.adc_ctrl_lowpower_counter.4271918285 Jan 14 01:39:40 PM PST 24 Jan 14 01:40:33 PM PST 24 39458530357 ps
T795 /workspace/coverage/default/40.adc_ctrl_smoke.3932592114 Jan 14 01:38:19 PM PST 24 Jan 14 01:38:31 PM PST 24 5828016970 ps
T796 /workspace/coverage/default/23.adc_ctrl_fsm_reset.2903502173 Jan 14 01:35:13 PM PST 24 Jan 14 01:46:02 PM PST 24 128094557882 ps
T797 /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.908588367 Jan 14 01:37:44 PM PST 24 Jan 14 01:42:22 PM PST 24 496912164221 ps
T258 /workspace/coverage/default/7.adc_ctrl_filters_interrupt.985111634 Jan 14 01:33:58 PM PST 24 Jan 14 01:39:03 PM PST 24 486802130391 ps
T319 /workspace/coverage/default/43.adc_ctrl_stress_all.3103423007 Jan 14 01:39:09 PM PST 24 Jan 14 01:53:15 PM PST 24 262738005291 ps
T798 /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1159240136 Jan 14 01:36:45 PM PST 24 Jan 14 01:54:40 PM PST 24 492700530626 ps
T799 /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.375166612 Jan 14 01:34:21 PM PST 24 Jan 14 01:37:33 PM PST 24 225831726259 ps
T800 /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.651101466 Jan 14 01:37:54 PM PST 24 Jan 14 01:44:07 PM PST 24 159430626373 ps
T190 /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1601551505 Jan 14 01:38:16 PM PST 24 Jan 14 01:39:46 PM PST 24 340647078570 ps
T801 /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4039174085 Jan 14 01:36:14 PM PST 24 Jan 14 01:37:00 PM PST 24 41364625886 ps
T329 /workspace/coverage/default/42.adc_ctrl_filters_polled.1922338360 Jan 14 01:38:46 PM PST 24 Jan 14 01:45:27 PM PST 24 167801930300 ps
T802 /workspace/coverage/default/17.adc_ctrl_filters_polled.1189451595 Jan 14 01:34:22 PM PST 24 Jan 14 01:40:29 PM PST 24 330818507532 ps
T803 /workspace/coverage/default/21.adc_ctrl_clock_gating.1124782034 Jan 14 01:35:01 PM PST 24 Jan 14 01:36:21 PM PST 24 329743400944 ps
T804 /workspace/coverage/default/37.adc_ctrl_alert_test.274019419 Jan 14 01:38:02 PM PST 24 Jan 14 01:38:04 PM PST 24 400040797 ps
T805 /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1579266497 Jan 14 01:33:29 PM PST 24 Jan 14 01:52:46 PM PST 24 485706889360 ps
T320 /workspace/coverage/default/40.adc_ctrl_filters_wakeup.354280041 Jan 14 01:38:18 PM PST 24 Jan 14 01:56:11 PM PST 24 493834201658 ps
T351 /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3070129668 Jan 14 01:38:47 PM PST 24 Jan 14 01:39:22 PM PST 24 38683684787 ps
T806 /workspace/coverage/default/39.adc_ctrl_filters_both.542474645 Jan 14 01:38:15 PM PST 24 Jan 14 01:59:57 PM PST 24 540217254736 ps
T807 /workspace/coverage/default/27.adc_ctrl_alert_test.438319197 Jan 14 01:36:18 PM PST 24 Jan 14 01:36:19 PM PST 24 438987207 ps
T808 /workspace/coverage/default/35.adc_ctrl_lowpower_counter.878624153 Jan 14 01:37:35 PM PST 24 Jan 14 01:38:02 PM PST 24 43087403117 ps
T809 /workspace/coverage/default/6.adc_ctrl_poweron_counter.2247970488 Jan 14 01:33:56 PM PST 24 Jan 14 01:34:02 PM PST 24 2742470142 ps
T810 /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3416400514 Jan 14 01:33:41 PM PST 24 Jan 14 01:36:34 PM PST 24 331213778687 ps
T811 /workspace/coverage/default/32.adc_ctrl_filters_both.1825409416 Jan 14 01:37:01 PM PST 24 Jan 14 01:47:00 PM PST 24 499015039037 ps
T812 /workspace/coverage/default/23.adc_ctrl_alert_test.1293694653 Jan 14 01:35:16 PM PST 24 Jan 14 01:35:17 PM PST 24 489407854 ps
T813 /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3937867879 Jan 14 01:37:44 PM PST 24 Jan 14 01:40:43 PM PST 24 493825071382 ps
T814 /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.562232077 Jan 14 01:40:01 PM PST 24 Jan 14 01:40:53 PM PST 24 326182264489 ps
T815 /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2436102977 Jan 14 01:36:16 PM PST 24 Jan 14 01:47:53 PM PST 24 325963354228 ps
T331 /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2904295655 Jan 14 01:38:34 PM PST 24 Jan 14 01:55:27 PM PST 24 495577779695 ps
T347 /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1563377291 Jan 14 01:33:56 PM PST 24 Jan 14 01:36:45 PM PST 24 140700860038 ps
T816 /workspace/coverage/default/36.adc_ctrl_fsm_reset.2544953752 Jan 14 01:37:51 PM PST 24 Jan 14 01:42:02 PM PST 24 66315116237 ps
T817 /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3908608027 Jan 14 01:35:34 PM PST 24 Jan 14 01:35:49 PM PST 24 23047156376 ps
T818 /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1518007056 Jan 14 01:40:07 PM PST 24 Jan 14 01:47:46 PM PST 24 397829168339 ps
T819 /workspace/coverage/default/48.adc_ctrl_poweron_counter.1107142628 Jan 14 01:39:55 PM PST 24 Jan 14 01:40:07 PM PST 24 4123310672 ps
T820 /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2940702843 Jan 14 01:34:35 PM PST 24 Jan 14 01:34:44 PM PST 24 32521847783 ps
T821 /workspace/coverage/default/41.adc_ctrl_alert_test.1326364438 Jan 14 01:38:46 PM PST 24 Jan 14 01:38:48 PM PST 24 412203432 ps
T822 /workspace/coverage/default/14.adc_ctrl_fsm_reset.3148850685 Jan 14 01:34:10 PM PST 24 Jan 14 01:41:08 PM PST 24 136804572329 ps
T363 /workspace/coverage/default/0.adc_ctrl_stress_all.3752595112 Jan 14 01:33:31 PM PST 24 Jan 14 01:50:32 PM PST 24 304337972123 ps
T334 /workspace/coverage/default/33.adc_ctrl_filters_both.1536467404 Jan 14 01:37:13 PM PST 24 Jan 14 01:40:27 PM PST 24 336461339028 ps
T823 /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.84312440 Jan 14 01:38:59 PM PST 24 Jan 14 01:58:00 PM PST 24 490860083201 ps
T824 /workspace/coverage/default/45.adc_ctrl_poweron_counter.22696824 Jan 14 01:39:21 PM PST 24 Jan 14 01:39:31 PM PST 24 3413830327 ps
T295 /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4094847437 Jan 14 01:34:35 PM PST 24 Jan 14 01:54:13 PM PST 24 490791626575 ps
T328 /workspace/coverage/default/30.adc_ctrl_filters_polled.623875134 Jan 14 01:36:36 PM PST 24 Jan 14 01:41:15 PM PST 24 492771792090 ps
T825 /workspace/coverage/default/24.adc_ctrl_stress_all.680254767 Jan 14 01:35:36 PM PST 24 Jan 14 01:36:57 PM PST 24 33891284553 ps
T826 /workspace/coverage/default/16.adc_ctrl_fsm_reset.4230103945 Jan 14 01:34:27 PM PST 24 Jan 14 01:39:54 PM PST 24 85630559252 ps
T827 /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3486783241 Jan 14 01:34:00 PM PST 24 Jan 14 01:38:55 PM PST 24 491332933032 ps
T828 /workspace/coverage/default/38.adc_ctrl_fsm_reset.655704855 Jan 14 01:38:12 PM PST 24 Jan 14 01:43:55 PM PST 24 93382368632 ps
T829 /workspace/coverage/default/28.adc_ctrl_poweron_counter.1528914396 Jan 14 01:36:14 PM PST 24 Jan 14 01:36:17 PM PST 24 3699271009 ps
T830 /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1912162510 Jan 14 01:39:51 PM PST 24 Jan 14 01:43:19 PM PST 24 167175325941 ps
T831 /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.4234797286 Jan 14 01:34:51 PM PST 24 Jan 14 01:36:16 PM PST 24 164401590182 ps
T832 /workspace/coverage/default/0.adc_ctrl_clock_gating.3001350146 Jan 14 01:33:23 PM PST 24 Jan 14 01:38:14 PM PST 24 506526500023 ps
T833 /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1876757228 Jan 14 01:34:23 PM PST 24 Jan 14 01:48:53 PM PST 24 497500254559 ps
T834 /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4079537700 Jan 14 01:39:57 PM PST 24 Jan 14 01:41:13 PM PST 24 32780874400 ps
T835 /workspace/coverage/default/39.adc_ctrl_fsm_reset.152103554 Jan 14 01:38:17 PM PST 24 Jan 14 01:43:22 PM PST 24 102141415075 ps
T836 /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2076852426 Jan 14 01:35:10 PM PST 24 Jan 14 01:36:17 PM PST 24 27462506981 ps
T350 /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1693652588 Jan 14 01:33:56 PM PST 24 Jan 14 01:36:48 PM PST 24 179374113478 ps
T364 /workspace/coverage/default/44.adc_ctrl_stress_all.3621630707 Jan 14 01:39:06 PM PST 24 Jan 14 01:48:16 PM PST 24 298781969835 ps
T837 /workspace/coverage/default/22.adc_ctrl_alert_test.3299957390 Jan 14 01:35:08 PM PST 24 Jan 14 01:35:11 PM PST 24 288611103 ps
T838 /workspace/coverage/default/5.adc_ctrl_fsm_reset.3116646078 Jan 14 01:33:49 PM PST 24 Jan 14 01:41:08 PM PST 24 120537874638 ps
T839 /workspace/coverage/default/1.adc_ctrl_smoke.1444834222 Jan 14 01:33:29 PM PST 24 Jan 14 01:33:37 PM PST 24 6019816818 ps
T840 /workspace/coverage/default/45.adc_ctrl_clock_gating.1398237045 Jan 14 01:39:16 PM PST 24 Jan 14 01:44:40 PM PST 24 335704325326 ps
T841 /workspace/coverage/default/26.adc_ctrl_stress_all.203896574 Jan 14 01:36:08 PM PST 24 Jan 14 01:36:25 PM PST 24 14775379022 ps
T842 /workspace/coverage/default/5.adc_ctrl_poweron_counter.2743124658 Jan 14 01:33:45 PM PST 24 Jan 14 01:33:50 PM PST 24 3499073281 ps
T843 /workspace/coverage/default/21.adc_ctrl_poweron_counter.1235345742 Jan 14 01:34:54 PM PST 24 Jan 14 01:34:58 PM PST 24 4613002941 ps
T844 /workspace/coverage/default/31.adc_ctrl_poweron_counter.886495581 Jan 14 01:36:47 PM PST 24 Jan 14 01:36:55 PM PST 24 5130219430 ps
T845 /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1097458405 Jan 14 01:34:23 PM PST 24 Jan 14 01:35:41 PM PST 24 338770575551 ps
T846 /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.983442754 Jan 14 01:38:53 PM PST 24 Jan 14 01:39:54 PM PST 24 167882220839 ps
T847 /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2368893648 Jan 14 01:35:15 PM PST 24 Jan 14 01:38:31 PM PST 24 495077509062 ps
T848 /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.4291738315 Jan 14 01:33:52 PM PST 24 Jan 14 01:39:50 PM PST 24 164168178192 ps
T849 /workspace/coverage/default/12.adc_ctrl_filters_interrupt.508800509 Jan 14 01:34:02 PM PST 24 Jan 14 01:46:29 PM PST 24 323997678271 ps
T312 /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1346177087 Jan 14 01:35:41 PM PST 24 Jan 14 01:40:45 PM PST 24 503581197435 ps
T850 /workspace/coverage/default/46.adc_ctrl_fsm_reset.1967577743 Jan 14 01:39:32 PM PST 24 Jan 14 01:47:15 PM PST 24 118344996408 ps
T851 /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.893114809 Jan 14 01:34:34 PM PST 24 Jan 14 01:38:04 PM PST 24 497742999316 ps
T852 /workspace/coverage/default/46.adc_ctrl_stress_all.1425459720 Jan 14 01:39:32 PM PST 24 Jan 14 01:43:30 PM PST 24 196854911796 ps
T853 /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2027831326 Jan 14 01:33:45 PM PST 24 Jan 14 01:42:53 PM PST 24 497250065113 ps
T854 /workspace/coverage/default/38.adc_ctrl_alert_test.182710967 Jan 14 01:38:13 PM PST 24 Jan 14 01:38:15 PM PST 24 360838962 ps
T296 /workspace/coverage/default/23.adc_ctrl_filters_both.804974394 Jan 14 01:35:12 PM PST 24 Jan 14 01:36:37 PM PST 24 343576644081 ps
T308 /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4013574483 Jan 14 01:34:10 PM PST 24 Jan 14 01:37:18 PM PST 24 325030477012 ps
T855 /workspace/coverage/default/21.adc_ctrl_alert_test.3792028540 Jan 14 01:35:08 PM PST 24 Jan 14 01:35:10 PM PST 24 323341213 ps
T856 /workspace/coverage/default/11.adc_ctrl_fsm_reset.2726974262 Jan 14 01:34:04 PM PST 24 Jan 14 01:41:51 PM PST 24 106439236223 ps
T857 /workspace/coverage/default/9.adc_ctrl_smoke.3898425057 Jan 14 01:33:52 PM PST 24 Jan 14 01:33:56 PM PST 24 5884250425 ps
T858 /workspace/coverage/default/31.adc_ctrl_stress_all.767685219 Jan 14 01:36:53 PM PST 24 Jan 14 01:41:53 PM PST 24 102136513924 ps
T859 /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2136604006 Jan 14 01:34:02 PM PST 24 Jan 14 01:35:38 PM PST 24 38979697514 ps
T860 /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2140136110 Jan 14 01:34:04 PM PST 24 Jan 14 01:39:00 PM PST 24 500605719109 ps
T861 /workspace/coverage/default/26.adc_ctrl_smoke.3788043390 Jan 14 01:35:51 PM PST 24 Jan 14 01:36:07 PM PST 24 5757059611 ps
T242 /workspace/coverage/default/15.adc_ctrl_stress_all.3689770257 Jan 14 01:34:21 PM PST 24 Jan 14 01:41:10 PM PST 24 342000582819 ps
T304 /workspace/coverage/default/37.adc_ctrl_stress_all.2279413644 Jan 14 01:38:01 PM PST 24 Jan 14 01:48:13 PM PST 24 497797258171 ps
T862 /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2172083755 Jan 14 01:34:03 PM PST 24 Jan 14 01:35:38 PM PST 24 161360657642 ps
T344 /workspace/coverage/default/44.adc_ctrl_filters_wakeup.45872033 Jan 14 01:39:09 PM PST 24 Jan 14 01:40:23 PM PST 24 161449024418 ps
T863 /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1881765652 Jan 14 01:35:07 PM PST 24 Jan 14 01:35:52 PM PST 24 148840747573 ps
T864 /workspace/coverage/default/2.adc_ctrl_filters_both.262861595 Jan 14 01:33:43 PM PST 24 Jan 14 01:52:23 PM PST 24 490815066355 ps
T297 /workspace/coverage/default/22.adc_ctrl_stress_all.3602621318 Jan 14 01:35:09 PM PST 24 Jan 14 01:48:56 PM PST 24 379993098711 ps
T865 /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3676220035 Jan 14 01:34:10 PM PST 24 Jan 14 01:34:27 PM PST 24 26012206488 ps
T866 /workspace/coverage/default/41.adc_ctrl_clock_gating.1700438111 Jan 14 01:38:37 PM PST 24 Jan 14 01:43:28 PM PST 24 485534680993 ps
T867 /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2808770263 Jan 14 01:36:15 PM PST 24 Jan 14 01:40:38 PM PST 24 109483958575 ps
T868 /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2535864755 Jan 14 01:39:00 PM PST 24 Jan 14 01:40:57 PM PST 24 87147187996 ps
T869 /workspace/coverage/default/47.adc_ctrl_clock_gating.1732940561 Jan 14 01:39:40 PM PST 24 Jan 14 01:42:27 PM PST 24 164270972077 ps
T870 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3780760881 Jan 14 01:03:02 PM PST 24 Jan 14 01:03:04 PM PST 24 338051366 ps
T871 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2281958887 Jan 14 01:02:28 PM PST 24 Jan 14 01:02:29 PM PST 24 633610145 ps
T91 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.541008558 Jan 14 01:02:51 PM PST 24 Jan 14 01:02:53 PM PST 24 547927566 ps
T872 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1789221847 Jan 14 01:03:00 PM PST 24 Jan 14 01:03:02 PM PST 24 428262255 ps
T873 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3252963192 Jan 14 01:02:12 PM PST 24 Jan 14 01:02:51 PM PST 24 53490501723 ps
T874 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3833386383 Jan 14 01:03:03 PM PST 24 Jan 14 01:03:06 PM PST 24 528862427 ps
T875 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3946736968 Jan 14 01:02:37 PM PST 24 Jan 14 01:02:45 PM PST 24 2348484640 ps
T876 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2532199355 Jan 14 01:03:02 PM PST 24 Jan 14 01:03:05 PM PST 24 287574400 ps
T877 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2441804740 Jan 14 01:02:23 PM PST 24 Jan 14 01:02:25 PM PST 24 764766959 ps
T878 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3770600863 Jan 14 01:02:42 PM PST 24 Jan 14 01:02:45 PM PST 24 415309001 ps
T879 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2657846201 Jan 14 01:02:28 PM PST 24 Jan 14 01:02:30 PM PST 24 541459740 ps
T880 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2425683242 Jan 14 01:02:51 PM PST 24 Jan 14 01:02:56 PM PST 24 4342723694 ps
T881 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1440732623 Jan 14 01:02:28 PM PST 24 Jan 14 01:02:32 PM PST 24 1134948609 ps
T882 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1450196218 Jan 14 01:02:27 PM PST 24 Jan 14 01:02:29 PM PST 24 307733158 ps
T883 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2912433201 Jan 14 01:02:45 PM PST 24 Jan 14 01:02:52 PM PST 24 5003418580 ps
T884 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1719616974 Jan 14 01:03:08 PM PST 24 Jan 14 01:03:10 PM PST 24 398273624 ps
T885 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.736764174 Jan 14 01:02:21 PM PST 24 Jan 14 01:02:24 PM PST 24 779383444 ps
T886 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2270018338 Jan 14 01:02:39 PM PST 24 Jan 14 01:02:44 PM PST 24 594821855 ps
T887 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3666634432 Jan 14 01:02:39 PM PST 24 Jan 14 01:02:43 PM PST 24 465046497 ps
T888 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1422540217 Jan 14 01:02:59 PM PST 24 Jan 14 01:03:01 PM PST 24 1992379013 ps
T889 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2831622175 Jan 14 01:02:54 PM PST 24 Jan 14 01:02:55 PM PST 24 350381598 ps
T890 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2202301340 Jan 14 01:02:51 PM PST 24 Jan 14 01:02:54 PM PST 24 330181734 ps
T92 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4255142515 Jan 14 01:02:39 PM PST 24 Jan 14 01:02:44 PM PST 24 418700126 ps
T891 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.757724648 Jan 14 01:02:03 PM PST 24 Jan 14 01:02:17 PM PST 24 8718621050 ps
T892 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.347842996 Jan 14 01:03:00 PM PST 24 Jan 14 01:03:01 PM PST 24 302533664 ps
T893 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4217976741 Jan 14 01:02:26 PM PST 24 Jan 14 01:02:40 PM PST 24 4654784664 ps
T894 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1272040503 Jan 14 01:02:44 PM PST 24 Jan 14 01:02:47 PM PST 24 528271566 ps
T895 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.280772338 Jan 14 01:02:50 PM PST 24 Jan 14 01:02:53 PM PST 24 723455895 ps
T896 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4162997661 Jan 14 01:02:29 PM PST 24 Jan 14 01:02:31 PM PST 24 531677616 ps
T897 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3742549969 Jan 14 01:02:16 PM PST 24 Jan 14 01:02:21 PM PST 24 2313543935 ps
T898 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2297716500 Jan 14 01:02:27 PM PST 24 Jan 14 01:02:29 PM PST 24 409424839 ps
T899 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1723473817 Jan 14 01:03:03 PM PST 24 Jan 14 01:03:06 PM PST 24 492021202 ps
T900 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3883892717 Jan 14 01:02:57 PM PST 24 Jan 14 01:02:59 PM PST 24 498646029 ps
T901 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1097923958 Jan 14 01:02:53 PM PST 24 Jan 14 01:02:56 PM PST 24 4931422208 ps
T902 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1885524780 Jan 14 01:02:39 PM PST 24 Jan 14 01:02:43 PM PST 24 485826566 ps
T903 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.628345397 Jan 14 01:02:52 PM PST 24 Jan 14 01:02:55 PM PST 24 649664533 ps
T904 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1902726410 Jan 14 01:03:03 PM PST 24 Jan 14 01:03:05 PM PST 24 316091520 ps
T905 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2540537994 Jan 14 01:02:29 PM PST 24 Jan 14 01:02:33 PM PST 24 5156174910 ps
T906 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1566497395 Jan 14 01:02:58 PM PST 24 Jan 14 01:03:00 PM PST 24 504627149 ps
T907 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3440076631 Jan 14 01:02:12 PM PST 24 Jan 14 01:02:15 PM PST 24 787814459 ps
T908 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1244151080 Jan 14 01:02:54 PM PST 24 Jan 14 01:02:56 PM PST 24 441335884 ps
T909 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1289795293 Jan 14 01:02:46 PM PST 24 Jan 14 01:02:49 PM PST 24 942930013 ps
T910 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.672823142 Jan 14 01:02:56 PM PST 24 Jan 14 01:02:59 PM PST 24 504055686 ps
T911 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1528141856 Jan 14 01:02:23 PM PST 24 Jan 14 01:02:31 PM PST 24 8691829489 ps
T912 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1946850231 Jan 14 01:02:49 PM PST 24 Jan 14 01:02:53 PM PST 24 469612260 ps
T93 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.183119895 Jan 14 01:02:51 PM PST 24 Jan 14 01:02:54 PM PST 24 516815241 ps
T913 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4107731021 Jan 14 01:03:01 PM PST 24 Jan 14 01:03:03 PM PST 24 394057397 ps
T99 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3416566770 Jan 14 01:02:28 PM PST 24 Jan 14 01:02:30 PM PST 24 433370831 ps
T914 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2236169872 Jan 14 01:02:40 PM PST 24 Jan 14 01:02:44 PM PST 24 528246780 ps
T915 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2181177406 Jan 14 01:02:41 PM PST 24 Jan 14 01:02:45 PM PST 24 2208037326 ps

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1260087707
Short name T6
Test name
Test status
Simulation time 604454951 ps
CPU time 0.7 seconds
Started Jan 14 01:02:26 PM PST 24
Finished Jan 14 01:02:27 PM PST 24
Peak memory 200396 kb
Host smart-8bcef5ab-ba44-4d7c-a673-6ea07c7793e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260087707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1260087707
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3037199966
Short name T4
Test name
Test status
Simulation time 4767342196 ps
CPU time 2.46 seconds
Started Jan 14 01:02:38 PM PST 24
Finished Jan 14 01:02:45 PM PST 24
Peak memory 200788 kb
Host smart-ec763dfd-e624-4783-a9a2-208222c141f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037199966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3037199966
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2290020389
Short name T13
Test name
Test status
Simulation time 61041405050 ps
CPU time 69.55 seconds
Started Jan 14 01:34:52 PM PST 24
Finished Jan 14 01:36:02 PM PST 24
Peak memory 209668 kb
Host smart-bc4c6112-9870-4c3d-a3ff-8fe4c804b411
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290020389 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2290020389
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2491025323
Short name T43
Test name
Test status
Simulation time 601374033596 ps
CPU time 1544.84 seconds
Started Jan 14 01:34:00 PM PST 24
Finished Jan 14 01:59:46 PM PST 24
Peak memory 209512 kb
Host smart-851f37fe-2957-4732-86e5-fa93f5d77a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491025323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2491025323
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3338067008
Short name T102
Test name
Test status
Simulation time 223891790058 ps
CPU time 394.17 seconds
Started Jan 14 01:37:51 PM PST 24
Finished Jan 14 01:44:27 PM PST 24
Peak memory 209512 kb
Host smart-5837ee8a-d3f4-40de-ab2e-88a3a19511b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338067008 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3338067008
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3692828056
Short name T240
Test name
Test status
Simulation time 500994219324 ps
CPU time 131.05 seconds
Started Jan 14 01:33:43 PM PST 24
Finished Jan 14 01:35:55 PM PST 24
Peak memory 200908 kb
Host smart-44e1652b-8cab-4c26-871d-26240b56da2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692828056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3692828056
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1493783016
Short name T56
Test name
Test status
Simulation time 496260454017 ps
CPU time 1080.53 seconds
Started Jan 14 01:39:41 PM PST 24
Finished Jan 14 01:57:49 PM PST 24
Peak memory 200948 kb
Host smart-30553af0-a023-4b60-ae11-8dbd52e6110f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493783016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1493783016
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2179006211
Short name T108
Test name
Test status
Simulation time 485454536348 ps
CPU time 136.94 seconds
Started Jan 14 01:34:17 PM PST 24
Finished Jan 14 01:36:35 PM PST 24
Peak memory 200996 kb
Host smart-fe126f36-8684-45f2-8ce4-ab21cfcbdb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179006211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2179006211
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2605317648
Short name T32
Test name
Test status
Simulation time 4342350938 ps
CPU time 5.68 seconds
Started Jan 14 01:02:51 PM PST 24
Finished Jan 14 01:02:57 PM PST 24
Peak memory 200780 kb
Host smart-c514feb3-2b96-4b5d-855d-1d66fb71bd05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605317648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2605317648
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2007601459
Short name T110
Test name
Test status
Simulation time 496502146478 ps
CPU time 530.35 seconds
Started Jan 14 01:34:20 PM PST 24
Finished Jan 14 01:43:11 PM PST 24
Peak memory 200776 kb
Host smart-e3a1b81d-d56c-4e30-929d-1e4f060815ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007601459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2007601459
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.4197838369
Short name T151
Test name
Test status
Simulation time 480124264883 ps
CPU time 192.25 seconds
Started Jan 14 01:33:39 PM PST 24
Finished Jan 14 01:36:52 PM PST 24
Peak memory 200924 kb
Host smart-7dc35fd4-f4ca-4695-8a68-90dd97b2c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197838369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.4197838369
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1478873032
Short name T244
Test name
Test status
Simulation time 485037304113 ps
CPU time 550.03 seconds
Started Jan 14 01:36:05 PM PST 24
Finished Jan 14 01:45:16 PM PST 24
Peak memory 200860 kb
Host smart-6fa7abb2-e1a2-4b89-b4d8-60e32aaa0260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478873032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1478873032
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1063032374
Short name T283
Test name
Test status
Simulation time 493971985144 ps
CPU time 261.36 seconds
Started Jan 14 01:33:53 PM PST 24
Finished Jan 14 01:38:15 PM PST 24
Peak memory 200912 kb
Host smart-54a1f097-b359-413e-97ab-c79588b3b030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063032374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1063032374
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.183516600
Short name T35
Test name
Test status
Simulation time 551057165 ps
CPU time 3.23 seconds
Started Jan 14 01:02:19 PM PST 24
Finished Jan 14 01:02:22 PM PST 24
Peak memory 210004 kb
Host smart-1de79300-709d-4c66-a24c-c5209b3f47b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183516600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.183516600
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1186590105
Short name T14
Test name
Test status
Simulation time 170451199940 ps
CPU time 379.2 seconds
Started Jan 14 01:33:41 PM PST 24
Finished Jan 14 01:40:01 PM PST 24
Peak memory 200952 kb
Host smart-e02e99b5-d9d9-47e1-8670-2a639e6d0669
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186590105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1186590105
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2148917085
Short name T154
Test name
Test status
Simulation time 494934974786 ps
CPU time 1124.34 seconds
Started Jan 14 01:38:16 PM PST 24
Finished Jan 14 01:57:01 PM PST 24
Peak memory 200840 kb
Host smart-400fefd6-7db2-4985-8634-fcbea83252a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148917085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2148917085
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.480625816
Short name T264
Test name
Test status
Simulation time 491496466508 ps
CPU time 988.04 seconds
Started Jan 14 01:38:29 PM PST 24
Finished Jan 14 01:54:57 PM PST 24
Peak memory 200884 kb
Host smart-079ba4d5-d4bb-4cc5-a7db-8479a9f95422
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480625816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.480625816
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1845942766
Short name T237
Test name
Test status
Simulation time 331157410957 ps
CPU time 760.65 seconds
Started Jan 14 01:38:51 PM PST 24
Finished Jan 14 01:51:32 PM PST 24
Peak memory 200928 kb
Host smart-b93d7b10-15c7-4e16-9b04-410505985e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845942766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1845942766
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.412292123
Short name T238
Test name
Test status
Simulation time 492614815579 ps
CPU time 507.96 seconds
Started Jan 14 01:33:51 PM PST 24
Finished Jan 14 01:42:19 PM PST 24
Peak memory 200896 kb
Host smart-bbab70ac-c249-46ad-8703-baeafcaf5640
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412292123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.412292123
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2757757037
Short name T40
Test name
Test status
Simulation time 559939555232 ps
CPU time 177.55 seconds
Started Jan 14 01:34:19 PM PST 24
Finished Jan 14 01:37:17 PM PST 24
Peak memory 200892 kb
Host smart-288db68c-d539-46a6-bb76-a97a7a7340f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757757037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2757757037
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.682158013
Short name T85
Test name
Test status
Simulation time 26932984329 ps
CPU time 104.79 seconds
Started Jan 14 01:02:15 PM PST 24
Finished Jan 14 01:04:01 PM PST 24
Peak memory 200812 kb
Host smart-4ccdc737-396f-497e-afb1-0bb1d6b468c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682158013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.682158013
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2618822799
Short name T126
Test name
Test status
Simulation time 323818312948 ps
CPU time 685.97 seconds
Started Jan 14 01:34:02 PM PST 24
Finished Jan 14 01:45:28 PM PST 24
Peak memory 200876 kb
Host smart-09ff73f3-90aa-4a8f-a3b0-59496c9657e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618822799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2618822799
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.921185421
Short name T327
Test name
Test status
Simulation time 507259747088 ps
CPU time 284.95 seconds
Started Jan 14 01:36:19 PM PST 24
Finished Jan 14 01:41:04 PM PST 24
Peak memory 200960 kb
Host smart-e22a12e8-ae68-4df9-a300-20297c4109d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921185421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.921185421
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2447283817
Short name T46
Test name
Test status
Simulation time 7992005696 ps
CPU time 6.08 seconds
Started Jan 14 01:33:46 PM PST 24
Finished Jan 14 01:33:53 PM PST 24
Peak memory 217232 kb
Host smart-e42d19b8-1fa5-4070-9e68-e1e790fbedc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447283817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2447283817
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.372325120
Short name T322
Test name
Test status
Simulation time 505492317695 ps
CPU time 305.48 seconds
Started Jan 14 01:34:48 PM PST 24
Finished Jan 14 01:39:54 PM PST 24
Peak memory 200860 kb
Host smart-4d4e517d-e187-440a-9bf3-81241c56204d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372325120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.372325120
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.732415041
Short name T235
Test name
Test status
Simulation time 333452881776 ps
CPU time 412.01 seconds
Started Jan 14 01:34:37 PM PST 24
Finished Jan 14 01:41:34 PM PST 24
Peak memory 200928 kb
Host smart-b398c203-db90-4224-b101-9d0de5625440
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732415041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.732415041
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1144611931
Short name T38
Test name
Test status
Simulation time 337720047331 ps
CPU time 638.89 seconds
Started Jan 14 01:37:16 PM PST 24
Finished Jan 14 01:47:57 PM PST 24
Peak memory 201000 kb
Host smart-b3129672-d1f1-45c3-9714-70961a5e9c3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144611931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1144611931
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4206243634
Short name T251
Test name
Test status
Simulation time 326397628804 ps
CPU time 364.02 seconds
Started Jan 14 01:37:51 PM PST 24
Finished Jan 14 01:43:56 PM PST 24
Peak memory 200796 kb
Host smart-a5f84b23-fd8c-4108-9e38-e47d2631f9ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206243634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4206243634
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1496214498
Short name T185
Test name
Test status
Simulation time 333334835272 ps
CPU time 135.67 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:36:13 PM PST 24
Peak memory 200868 kb
Host smart-0812732e-2072-46e3-97bb-fac25566d915
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496214498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1496214498
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1723892532
Short name T228
Test name
Test status
Simulation time 326025904950 ps
CPU time 685.36 seconds
Started Jan 14 01:35:16 PM PST 24
Finished Jan 14 01:46:42 PM PST 24
Peak memory 200952 kb
Host smart-f37d7942-1b08-49f2-9436-523c242dbf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723892532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1723892532
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1387732326
Short name T231
Test name
Test status
Simulation time 323335287520 ps
CPU time 721.17 seconds
Started Jan 14 01:33:40 PM PST 24
Finished Jan 14 01:45:41 PM PST 24
Peak memory 200908 kb
Host smart-fd81537b-522c-476f-8184-c1667c703fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387732326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1387732326
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3678919724
Short name T303
Test name
Test status
Simulation time 499401085040 ps
CPU time 1232.71 seconds
Started Jan 14 01:33:41 PM PST 24
Finished Jan 14 01:54:15 PM PST 24
Peak memory 200968 kb
Host smart-f1c102d0-ce84-46d7-9dbf-6599df7bd80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678919724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3678919724
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.158277159
Short name T286
Test name
Test status
Simulation time 493253903806 ps
CPU time 1127.92 seconds
Started Jan 14 01:38:46 PM PST 24
Finished Jan 14 01:57:34 PM PST 24
Peak memory 200972 kb
Host smart-6254f6d8-d54f-40d8-96cb-547aa902afd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158277159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.158277159
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1812518916
Short name T323
Test name
Test status
Simulation time 162236597408 ps
CPU time 367.59 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:39:52 PM PST 24
Peak memory 200760 kb
Host smart-c38babef-ebf9-4c4a-9e87-7dea3c142038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812518916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1812518916
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.779474695
Short name T41
Test name
Test status
Simulation time 275696079555 ps
CPU time 467.52 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:41:45 PM PST 24
Peak memory 209560 kb
Host smart-e2c74818-bec1-4340-b108-accae8bc2f00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779474695 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.779474695
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2113585933
Short name T179
Test name
Test status
Simulation time 490678850925 ps
CPU time 177.51 seconds
Started Jan 14 01:33:57 PM PST 24
Finished Jan 14 01:36:56 PM PST 24
Peak memory 200896 kb
Host smart-f599a410-6551-4870-829d-1fe91a9abe7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113585933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2113585933
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.4187377571
Short name T250
Test name
Test status
Simulation time 501006041474 ps
CPU time 571.43 seconds
Started Jan 14 01:34:06 PM PST 24
Finished Jan 14 01:43:39 PM PST 24
Peak memory 200872 kb
Host smart-03073f47-c73b-45e8-bd2c-b8688c8f3dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187377571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.4187377571
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2666558768
Short name T289
Test name
Test status
Simulation time 323849351231 ps
CPU time 699.86 seconds
Started Jan 14 01:33:57 PM PST 24
Finished Jan 14 01:45:38 PM PST 24
Peak memory 200880 kb
Host smart-8e237f75-259c-4c3c-bacd-c1f7423dd62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666558768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2666558768
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1929949380
Short name T245
Test name
Test status
Simulation time 344600773501 ps
CPU time 397.26 seconds
Started Jan 14 01:34:33 PM PST 24
Finished Jan 14 01:41:13 PM PST 24
Peak memory 200864 kb
Host smart-e30e64bf-4de0-42d9-a235-accdebb3fae5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929949380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1929949380
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3690986029
Short name T272
Test name
Test status
Simulation time 167314235877 ps
CPU time 104.02 seconds
Started Jan 14 01:34:47 PM PST 24
Finished Jan 14 01:36:32 PM PST 24
Peak memory 200936 kb
Host smart-9d57aa62-4524-4b21-b328-153e5ced34df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690986029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3690986029
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1931293144
Short name T137
Test name
Test status
Simulation time 495789775506 ps
CPU time 1188.73 seconds
Started Jan 14 01:36:00 PM PST 24
Finished Jan 14 01:55:49 PM PST 24
Peak memory 200956 kb
Host smart-75148854-c9ea-42fc-8169-1484613e3e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931293144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1931293144
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1533654926
Short name T155
Test name
Test status
Simulation time 502418535373 ps
CPU time 569.99 seconds
Started Jan 14 01:38:00 PM PST 24
Finished Jan 14 01:47:30 PM PST 24
Peak memory 201020 kb
Host smart-eef69178-58f2-4691-9cec-a48741e0be44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533654926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1533654926
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3689770257
Short name T242
Test name
Test status
Simulation time 342000582819 ps
CPU time 407.84 seconds
Started Jan 14 01:34:21 PM PST 24
Finished Jan 14 01:41:10 PM PST 24
Peak memory 200852 kb
Host smart-152322e3-08e2-477e-a013-e0e197153ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689770257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3689770257
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2797132155
Short name T310
Test name
Test status
Simulation time 336492985869 ps
CPU time 204.78 seconds
Started Jan 14 01:37:02 PM PST 24
Finished Jan 14 01:40:29 PM PST 24
Peak memory 200948 kb
Host smart-9cdff08f-74b9-44b0-8156-5fcc3cecdfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797132155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2797132155
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3313633868
Short name T220
Test name
Test status
Simulation time 493936032725 ps
CPU time 351.84 seconds
Started Jan 14 01:34:08 PM PST 24
Finished Jan 14 01:40:06 PM PST 24
Peak memory 200932 kb
Host smart-f4a06686-6cae-4e40-96a9-360a8d96a081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313633868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3313633868
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4013574483
Short name T308
Test name
Test status
Simulation time 325030477012 ps
CPU time 184.07 seconds
Started Jan 14 01:34:10 PM PST 24
Finished Jan 14 01:37:18 PM PST 24
Peak memory 201036 kb
Host smart-7e32f989-7f89-4173-8c81-3794ddf3a638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013574483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.4013574483
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2780857244
Short name T247
Test name
Test status
Simulation time 498438439235 ps
CPU time 301.86 seconds
Started Jan 14 01:34:48 PM PST 24
Finished Jan 14 01:39:51 PM PST 24
Peak memory 200952 kb
Host smart-3e71a2bc-806f-4afd-8842-03fa4776df89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780857244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2780857244
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1154002132
Short name T248
Test name
Test status
Simulation time 326590844845 ps
CPU time 421.44 seconds
Started Jan 14 01:34:37 PM PST 24
Finished Jan 14 01:41:44 PM PST 24
Peak memory 200948 kb
Host smart-4bbe7fb5-fad7-4428-89f5-a76e029bd119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154002132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1154002132
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2199937688
Short name T209
Test name
Test status
Simulation time 138055213958 ps
CPU time 454.18 seconds
Started Jan 14 01:34:12 PM PST 24
Finished Jan 14 01:41:49 PM PST 24
Peak memory 201300 kb
Host smart-4aa8670d-3817-436e-902f-8ecb247d870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199937688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2199937688
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3761575891
Short name T168
Test name
Test status
Simulation time 171206314079 ps
CPU time 100.69 seconds
Started Jan 14 01:36:04 PM PST 24
Finished Jan 14 01:37:45 PM PST 24
Peak memory 200872 kb
Host smart-93dac4c0-d3b2-4d21-9d44-0efbbc246536
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761575891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3761575891
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1622511760
Short name T177
Test name
Test status
Simulation time 323869819640 ps
CPU time 51.65 seconds
Started Jan 14 01:38:48 PM PST 24
Finished Jan 14 01:39:40 PM PST 24
Peak memory 200960 kb
Host smart-8e1718a6-7a5c-4a35-8895-e5d8c508e013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622511760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1622511760
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.45872033
Short name T344
Test name
Test status
Simulation time 161449024418 ps
CPU time 72.83 seconds
Started Jan 14 01:39:09 PM PST 24
Finished Jan 14 01:40:23 PM PST 24
Peak memory 200384 kb
Host smart-67269bb0-b69a-4eb5-ad05-7b6d24155cf7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45872033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_w
akeup.45872033
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3970366885
Short name T63
Test name
Test status
Simulation time 539867251 ps
CPU time 2.77 seconds
Started Jan 14 01:02:40 PM PST 24
Finished Jan 14 01:02:45 PM PST 24
Peak memory 208992 kb
Host smart-6c1d04cc-d238-4eac-ac39-dd13599c860c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970366885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3970366885
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3708077879
Short name T51
Test name
Test status
Simulation time 166144615852 ps
CPU time 194.5 seconds
Started Jan 14 01:36:37 PM PST 24
Finished Jan 14 01:39:59 PM PST 24
Peak memory 200880 kb
Host smart-df6aca2f-5ca0-4cb8-b071-41eef15bf589
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708077879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3708077879
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3512403699
Short name T274
Test name
Test status
Simulation time 68187713436 ps
CPU time 144.74 seconds
Started Jan 14 01:33:45 PM PST 24
Finished Jan 14 01:36:10 PM PST 24
Peak memory 209140 kb
Host smart-d8962c20-a4bc-4baf-8c6a-0ca3865cfee1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512403699 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3512403699
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1081428933
Short name T427
Test name
Test status
Simulation time 326106641893 ps
CPU time 734.8 seconds
Started Jan 14 01:34:02 PM PST 24
Finished Jan 14 01:46:18 PM PST 24
Peak memory 200824 kb
Host smart-3cb22239-cfb3-403b-84c3-3a8ef48c8657
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081428933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1081428933
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1964680557
Short name T152
Test name
Test status
Simulation time 327873011144 ps
CPU time 175.66 seconds
Started Jan 14 01:34:06 PM PST 24
Finished Jan 14 01:37:03 PM PST 24
Peak memory 200956 kb
Host smart-a445a694-3e4f-4806-9bff-8dde74d9a31b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964680557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1964680557
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1767021149
Short name T213
Test name
Test status
Simulation time 117413250156 ps
CPU time 688.2 seconds
Started Jan 14 01:33:41 PM PST 24
Finished Jan 14 01:45:10 PM PST 24
Peak memory 201396 kb
Host smart-6b98c0a0-e87a-452c-991f-f75b9c465f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767021149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1767021149
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1922338360
Short name T329
Test name
Test status
Simulation time 167801930300 ps
CPU time 400.8 seconds
Started Jan 14 01:38:46 PM PST 24
Finished Jan 14 01:45:27 PM PST 24
Peak memory 200924 kb
Host smart-4e2caef1-86fb-4ad7-9a3f-e6c90d7ac4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922338360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1922338360
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2311289485
Short name T30
Test name
Test status
Simulation time 454188035 ps
CPU time 0.91 seconds
Started Jan 14 01:33:53 PM PST 24
Finished Jan 14 01:33:54 PM PST 24
Peak memory 200692 kb
Host smart-4fae3e81-89df-4354-bdcc-55623d1dc221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311289485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2311289485
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3121687295
Short name T66
Test name
Test status
Simulation time 8037267459 ps
CPU time 6.85 seconds
Started Jan 14 01:02:41 PM PST 24
Finished Jan 14 01:02:49 PM PST 24
Peak memory 200728 kb
Host smart-469b7288-5e4e-4fb0-8104-41ce3e67b070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121687295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3121687295
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1567159558
Short name T369
Test name
Test status
Simulation time 502439157 ps
CPU time 1.14 seconds
Started Jan 14 01:03:06 PM PST 24
Finished Jan 14 01:03:08 PM PST 24
Peak memory 200224 kb
Host smart-ab232749-4947-4273-826e-df7f68fcc1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567159558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1567159558
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2497851518
Short name T230
Test name
Test status
Simulation time 162641228121 ps
CPU time 37.77 seconds
Started Jan 14 01:34:15 PM PST 24
Finished Jan 14 01:34:56 PM PST 24
Peak memory 200996 kb
Host smart-3e156404-b84a-4f00-b92f-3415a90440c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497851518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2497851518
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2316000127
Short name T216
Test name
Test status
Simulation time 146257935437 ps
CPU time 536.01 seconds
Started Jan 14 01:34:58 PM PST 24
Finished Jan 14 01:43:56 PM PST 24
Peak memory 201368 kb
Host smart-e5b2122a-0536-433e-ac69-d45ac8755f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316000127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2316000127
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3602621318
Short name T297
Test name
Test status
Simulation time 379993098711 ps
CPU time 826.89 seconds
Started Jan 14 01:35:09 PM PST 24
Finished Jan 14 01:48:56 PM PST 24
Peak memory 211572 kb
Host smart-4c12036c-999c-4a9f-8c25-77d1b933637b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602621318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3602621318
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1346177087
Short name T312
Test name
Test status
Simulation time 503581197435 ps
CPU time 304.1 seconds
Started Jan 14 01:35:41 PM PST 24
Finished Jan 14 01:40:45 PM PST 24
Peak memory 200960 kb
Host smart-86e883e9-2053-461f-a499-3868ae94b7de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346177087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1346177087
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2167412448
Short name T302
Test name
Test status
Simulation time 510605825014 ps
CPU time 215.91 seconds
Started Jan 14 01:36:18 PM PST 24
Finished Jan 14 01:39:54 PM PST 24
Peak memory 200964 kb
Host smart-18fc1f0e-2de0-44e8-856a-35c908ab90f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167412448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2167412448
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2376147232
Short name T317
Test name
Test status
Simulation time 330004255795 ps
CPU time 828.42 seconds
Started Jan 14 01:36:21 PM PST 24
Finished Jan 14 01:50:10 PM PST 24
Peak memory 200840 kb
Host smart-463a6e7f-aca9-4b0f-bf0c-f5f1fd162732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376147232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2376147232
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.499008467
Short name T267
Test name
Test status
Simulation time 130996812874 ps
CPU time 134.72 seconds
Started Jan 14 01:36:36 PM PST 24
Finished Jan 14 01:38:59 PM PST 24
Peak memory 217344 kb
Host smart-404b3ad2-3d93-4fa3-86c1-69dcdd295fb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499008467 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.499008467
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.4099024159
Short name T243
Test name
Test status
Simulation time 330514565777 ps
CPU time 750.61 seconds
Started Jan 14 01:37:37 PM PST 24
Finished Jan 14 01:50:09 PM PST 24
Peak memory 200848 kb
Host smart-600b5986-dce7-4f87-bd0c-8a8bdba9aa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099024159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.4099024159
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.354280041
Short name T320
Test name
Test status
Simulation time 493834201658 ps
CPU time 1072.92 seconds
Started Jan 14 01:38:18 PM PST 24
Finished Jan 14 01:56:11 PM PST 24
Peak memory 200960 kb
Host smart-7f598498-3303-4f26-a2b8-8dc1cb616988
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354280041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.354280041
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3248768516
Short name T165
Test name
Test status
Simulation time 488475571026 ps
CPU time 71.69 seconds
Started Jan 14 01:39:07 PM PST 24
Finished Jan 14 01:40:19 PM PST 24
Peak memory 200928 kb
Host smart-727937d6-bbb2-40f4-87fc-742e9406ec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248768516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3248768516
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1717165982
Short name T293
Test name
Test status
Simulation time 497594299993 ps
CPU time 1260.99 seconds
Started Jan 14 01:39:41 PM PST 24
Finished Jan 14 02:00:49 PM PST 24
Peak memory 200868 kb
Host smart-c586b286-5da3-479b-a883-441fc0275016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717165982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1717165982
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1369439858
Short name T300
Test name
Test status
Simulation time 522950150337 ps
CPU time 1282.88 seconds
Started Jan 14 01:40:04 PM PST 24
Finished Jan 14 02:01:33 PM PST 24
Peak memory 200876 kb
Host smart-64b3bf3c-ea08-4f82-9cd8-99bb6ff31157
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369439858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1369439858
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2475909924
Short name T222
Test name
Test status
Simulation time 500316618703 ps
CPU time 1108.52 seconds
Started Jan 14 01:33:55 PM PST 24
Finished Jan 14 01:52:24 PM PST 24
Peak memory 200908 kb
Host smart-bcb26c06-d321-4852-9996-e085688ab316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475909924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2475909924
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4001126084
Short name T340
Test name
Test status
Simulation time 321032963450 ps
CPU time 743.65 seconds
Started Jan 14 01:34:09 PM PST 24
Finished Jan 14 01:46:38 PM PST 24
Peak memory 200992 kb
Host smart-2472f794-7c24-435e-8e14-e06fa1d5c965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001126084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4001126084
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.869406963
Short name T180
Test name
Test status
Simulation time 492385539141 ps
CPU time 264 seconds
Started Jan 14 01:34:09 PM PST 24
Finished Jan 14 01:38:38 PM PST 24
Peak memory 200856 kb
Host smart-f8ac99be-88d9-4107-8008-ea50e0231728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869406963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.869406963
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.4172051025
Short name T338
Test name
Test status
Simulation time 264777695174 ps
CPU time 597.03 seconds
Started Jan 14 01:34:46 PM PST 24
Finished Jan 14 01:44:44 PM PST 24
Peak memory 201368 kb
Host smart-5be7bb82-1b41-48d9-85a2-441c45f8fe80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172051025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.4172051025
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.623875134
Short name T328
Test name
Test status
Simulation time 492771792090 ps
CPU time 270.71 seconds
Started Jan 14 01:36:36 PM PST 24
Finished Jan 14 01:41:15 PM PST 24
Peak memory 200932 kb
Host smart-db0a2b9a-eeb2-45cd-93ed-aad49f45fc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623875134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.623875134
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.4007472732
Short name T276
Test name
Test status
Simulation time 326209632750 ps
CPU time 819.89 seconds
Started Jan 14 01:38:19 PM PST 24
Finished Jan 14 01:51:59 PM PST 24
Peak memory 200820 kb
Host smart-3ce4c75e-bd72-494d-94ca-25acced2dd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007472732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.4007472732
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3001350146
Short name T832
Test name
Test status
Simulation time 506526500023 ps
CPU time 291.19 seconds
Started Jan 14 01:33:23 PM PST 24
Finished Jan 14 01:38:14 PM PST 24
Peak memory 200844 kb
Host smart-365ec841-8333-4aaf-bbef-b4872ce8a613
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001350146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3001350146
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1659225658
Short name T178
Test name
Test status
Simulation time 500100438466 ps
CPU time 617.79 seconds
Started Jan 14 01:33:33 PM PST 24
Finished Jan 14 01:43:51 PM PST 24
Peak memory 200924 kb
Host smart-d285244d-b84b-409a-bf25-4f7b562a6008
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659225658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1659225658
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3752595112
Short name T363
Test name
Test status
Simulation time 304337972123 ps
CPU time 1020.83 seconds
Started Jan 14 01:33:31 PM PST 24
Finished Jan 14 01:50:32 PM PST 24
Peak memory 201328 kb
Host smart-02f144de-93e8-4ea5-be2c-a7e99e11ad5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752595112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3752595112
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.237853576
Short name T349
Test name
Test status
Simulation time 427094487355 ps
CPU time 364.78 seconds
Started Jan 14 01:34:08 PM PST 24
Finished Jan 14 01:40:18 PM PST 24
Peak memory 209692 kb
Host smart-91857c81-151d-4b9c-a34c-4d57efb3a549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237853576 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.237853576
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3024460920
Short name T342
Test name
Test status
Simulation time 331292727524 ps
CPU time 701.73 seconds
Started Jan 14 01:34:08 PM PST 24
Finished Jan 14 01:45:54 PM PST 24
Peak memory 200920 kb
Host smart-a9ad57a5-2cd3-4fad-8e64-a17f97d3ec41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024460920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3024460920
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3295885669
Short name T341
Test name
Test status
Simulation time 317799086144 ps
CPU time 207.02 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:38:04 PM PST 24
Peak memory 200884 kb
Host smart-a9fe0041-a9c2-4cd3-9b23-ca6e68e33357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295885669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3295885669
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1281074651
Short name T259
Test name
Test status
Simulation time 93961389647 ps
CPU time 59.36 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:35:36 PM PST 24
Peak memory 210260 kb
Host smart-2d0b052c-460f-46cd-8fed-deb60f0c6961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281074651 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1281074651
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.804974394
Short name T296
Test name
Test status
Simulation time 343576644081 ps
CPU time 83.96 seconds
Started Jan 14 01:35:12 PM PST 24
Finished Jan 14 01:36:37 PM PST 24
Peak memory 200972 kb
Host smart-8dad5ec6-5067-4925-8aa5-9ab63a20a081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804974394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.804974394
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3966031502
Short name T292
Test name
Test status
Simulation time 327701061264 ps
CPU time 240.21 seconds
Started Jan 14 01:35:51 PM PST 24
Finished Jan 14 01:39:52 PM PST 24
Peak memory 200964 kb
Host smart-384c5bd1-9ebc-40ac-afe2-9adf4446edc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966031502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3966031502
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4120832945
Short name T227
Test name
Test status
Simulation time 318683877785 ps
CPU time 358.02 seconds
Started Jan 14 01:36:24 PM PST 24
Finished Jan 14 01:42:23 PM PST 24
Peak memory 201004 kb
Host smart-6f4794fc-428d-4800-9550-c66e4f71e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120832945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4120832945
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.937228318
Short name T315
Test name
Test status
Simulation time 334107018958 ps
CPU time 116.98 seconds
Started Jan 14 01:37:20 PM PST 24
Finished Jan 14 01:39:17 PM PST 24
Peak memory 200908 kb
Host smart-748c8409-e080-49ff-b976-44dc6cc9a517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937228318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.937228318
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3947535394
Short name T282
Test name
Test status
Simulation time 170929192408 ps
CPU time 375.51 seconds
Started Jan 14 01:37:36 PM PST 24
Finished Jan 14 01:43:53 PM PST 24
Peak memory 200800 kb
Host smart-e5ab24ce-8847-40cb-a39d-eaf665b7d003
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947535394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3947535394
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3103423007
Short name T319
Test name
Test status
Simulation time 262738005291 ps
CPU time 845.34 seconds
Started Jan 14 01:39:09 PM PST 24
Finished Jan 14 01:53:15 PM PST 24
Peak memory 209504 kb
Host smart-8585709c-9fc6-4bf3-b867-27501d9a55e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103423007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3103423007
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.491975527
Short name T358
Test name
Test status
Simulation time 123396201727 ps
CPU time 588.94 seconds
Started Jan 14 01:39:54 PM PST 24
Finished Jan 14 01:49:44 PM PST 24
Peak memory 201380 kb
Host smart-79685ca8-78b2-4f4a-8f6b-8d07e912de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491975527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.491975527
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1547436749
Short name T21
Test name
Test status
Simulation time 237700005253 ps
CPU time 790.67 seconds
Started Jan 14 01:40:08 PM PST 24
Finished Jan 14 01:53:21 PM PST 24
Peak memory 201348 kb
Host smart-0d2d8c97-0b11-440c-b485-76223b7694b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547436749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1547436749
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1463361072
Short name T229
Test name
Test status
Simulation time 52506624696 ps
CPU time 106.69 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:35:51 PM PST 24
Peak memory 209612 kb
Host smart-61061787-00da-4564-b81e-306cd7e57726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463361072 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1463361072
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2649791069
Short name T346
Test name
Test status
Simulation time 324285869134 ps
CPU time 396.46 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:40:41 PM PST 24
Peak memory 200976 kb
Host smart-119d7e44-07c8-4723-85cb-0ab418bdad1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649791069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2649791069
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1728187480
Short name T388
Test name
Test status
Simulation time 1241983231 ps
CPU time 2.88 seconds
Started Jan 14 01:02:20 PM PST 24
Finished Jan 14 01:02:23 PM PST 24
Peak memory 200672 kb
Host smart-2a369008-962e-49bd-b933-17077d28d1d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728187480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1728187480
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3252963192
Short name T873
Test name
Test status
Simulation time 53490501723 ps
CPU time 38.03 seconds
Started Jan 14 01:02:12 PM PST 24
Finished Jan 14 01:02:51 PM PST 24
Peak memory 200804 kb
Host smart-053f6983-731d-4f08-b726-7a4f16c4b4dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252963192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3252963192
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2862897820
Short name T33
Test name
Test status
Simulation time 878637789 ps
CPU time 2.69 seconds
Started Jan 14 01:02:02 PM PST 24
Finished Jan 14 01:02:06 PM PST 24
Peak memory 200456 kb
Host smart-074ab757-b1e9-45c3-9939-1cce113e28bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862897820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2862897820
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3479274631
Short name T404
Test name
Test status
Simulation time 372168169 ps
CPU time 0.96 seconds
Started Jan 14 01:02:16 PM PST 24
Finished Jan 14 01:02:17 PM PST 24
Peak memory 200496 kb
Host smart-7bac39a0-42ac-4368-a228-047d770cdafc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479274631 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3479274631
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2620215625
Short name T81
Test name
Test status
Simulation time 543460274 ps
CPU time 1.26 seconds
Started Jan 14 01:02:03 PM PST 24
Finished Jan 14 01:02:05 PM PST 24
Peak memory 200556 kb
Host smart-5c9c3756-5ef4-4428-adda-d94d3c9ce617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620215625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2620215625
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1658058440
Short name T397
Test name
Test status
Simulation time 331292158 ps
CPU time 1.4 seconds
Started Jan 14 01:02:06 PM PST 24
Finished Jan 14 01:02:08 PM PST 24
Peak memory 200564 kb
Host smart-7a137a9f-18fb-4d8f-a7e1-aa968e0f4875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658058440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1658058440
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3742549969
Short name T897
Test name
Test status
Simulation time 2313543935 ps
CPU time 4.87 seconds
Started Jan 14 01:02:16 PM PST 24
Finished Jan 14 01:02:21 PM PST 24
Peak memory 200596 kb
Host smart-a2222f64-0175-47ba-83ac-1630dc70f771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742549969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3742549969
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2298017117
Short name T410
Test name
Test status
Simulation time 518742336 ps
CPU time 2.39 seconds
Started Jan 14 01:02:01 PM PST 24
Finished Jan 14 01:02:04 PM PST 24
Peak memory 200788 kb
Host smart-e9a87561-d558-44db-8b22-2b266a1164b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298017117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2298017117
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.757724648
Short name T891
Test name
Test status
Simulation time 8718621050 ps
CPU time 12.88 seconds
Started Jan 14 01:02:03 PM PST 24
Finished Jan 14 01:02:17 PM PST 24
Peak memory 200752 kb
Host smart-70a010c4-44a3-489e-b2eb-3aa87313311d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757724648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.757724648
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3486543798
Short name T414
Test name
Test status
Simulation time 1290521297 ps
CPU time 1.68 seconds
Started Jan 14 01:02:17 PM PST 24
Finished Jan 14 01:02:19 PM PST 24
Peak memory 200708 kb
Host smart-08fe05b1-6993-472d-aa5d-585a6ccb7ad4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486543798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3486543798
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3440076631
Short name T907
Test name
Test status
Simulation time 787814459 ps
CPU time 2.33 seconds
Started Jan 14 01:02:12 PM PST 24
Finished Jan 14 01:02:15 PM PST 24
Peak memory 200568 kb
Host smart-da685110-00b8-4d53-9d4d-0e2ed7bf36fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440076631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3440076631
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4159439881
Short name T381
Test name
Test status
Simulation time 518364783 ps
CPU time 1.05 seconds
Started Jan 14 01:02:18 PM PST 24
Finished Jan 14 01:02:19 PM PST 24
Peak memory 200632 kb
Host smart-48863b25-ded1-46c6-8a83-387d2ab639b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159439881 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4159439881
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4276757456
Short name T71
Test name
Test status
Simulation time 500243711 ps
CPU time 1.01 seconds
Started Jan 14 01:02:11 PM PST 24
Finished Jan 14 01:02:13 PM PST 24
Peak memory 200496 kb
Host smart-17743df9-1d93-4f33-9dda-555a998e73d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276757456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4276757456
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.154623071
Short name T398
Test name
Test status
Simulation time 299505883 ps
CPU time 1 seconds
Started Jan 14 01:02:12 PM PST 24
Finished Jan 14 01:02:13 PM PST 24
Peak memory 200224 kb
Host smart-a94d3cfc-4b37-4ce5-9194-de4d2a163de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154623071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.154623071
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1250436190
Short name T94
Test name
Test status
Simulation time 2372684264 ps
CPU time 3.34 seconds
Started Jan 14 01:02:14 PM PST 24
Finished Jan 14 01:02:17 PM PST 24
Peak memory 200456 kb
Host smart-89765e1f-922b-4fbb-8c4d-e0df04c20050
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250436190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1250436190
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1528141856
Short name T911
Test name
Test status
Simulation time 8691829489 ps
CPU time 7.45 seconds
Started Jan 14 01:02:23 PM PST 24
Finished Jan 14 01:02:31 PM PST 24
Peak memory 200940 kb
Host smart-87d7cd7e-d01a-47d6-a43e-6521427734fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528141856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1528141856
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4192715734
Short name T383
Test name
Test status
Simulation time 501494000 ps
CPU time 2 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 200552 kb
Host smart-37889827-cf8e-44bd-8634-aef992e8c184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192715734 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.4192715734
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4255142515
Short name T92
Test name
Test status
Simulation time 418700126 ps
CPU time 1.92 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 200484 kb
Host smart-a5e81afc-3eec-4d64-bb16-931e36e4228c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255142515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.4255142515
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3987245439
Short name T77
Test name
Test status
Simulation time 301657216 ps
CPU time 0.96 seconds
Started Jan 14 01:02:38 PM PST 24
Finished Jan 14 01:02:43 PM PST 24
Peak memory 200460 kb
Host smart-2938a365-0ada-4328-beaf-3f868d8301b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987245439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3987245439
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3946736968
Short name T875
Test name
Test status
Simulation time 2348484640 ps
CPU time 2.7 seconds
Started Jan 14 01:02:37 PM PST 24
Finished Jan 14 01:02:45 PM PST 24
Peak memory 200544 kb
Host smart-c09423ed-c732-418a-97b8-96e1047d9183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946736968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3946736968
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2270018338
Short name T886
Test name
Test status
Simulation time 594821855 ps
CPU time 2.31 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 208988 kb
Host smart-153e0cca-9bea-4b22-9120-16e10a74e4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270018338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2270018338
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1444597158
Short name T27
Test name
Test status
Simulation time 378550739 ps
CPU time 1.43 seconds
Started Jan 14 01:02:38 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 200600 kb
Host smart-24d8e291-816f-4fde-97eb-e4f3a72143a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444597158 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1444597158
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1932595946
Short name T83
Test name
Test status
Simulation time 521446416 ps
CPU time 1.01 seconds
Started Jan 14 01:02:42 PM PST 24
Finished Jan 14 01:02:46 PM PST 24
Peak memory 200496 kb
Host smart-6c2eaf61-bed5-414e-bc79-ed8f40c7ae7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932595946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1932595946
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3666634432
Short name T887
Test name
Test status
Simulation time 465046497 ps
CPU time 1.13 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:43 PM PST 24
Peak memory 200240 kb
Host smart-18960cad-8ab4-43d3-ac7d-062a48e7c1b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666634432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3666634432
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4036616447
Short name T377
Test name
Test status
Simulation time 4677798629 ps
CPU time 10.78 seconds
Started Jan 14 01:02:38 PM PST 24
Finished Jan 14 01:02:53 PM PST 24
Peak memory 200780 kb
Host smart-ea615761-9836-4334-8141-328538c96da8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036616447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.4036616447
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3778103211
Short name T406
Test name
Test status
Simulation time 8705321106 ps
CPU time 7.03 seconds
Started Jan 14 01:02:36 PM PST 24
Finished Jan 14 01:02:48 PM PST 24
Peak memory 200812 kb
Host smart-60499e67-7f73-4f13-9152-6fbf95434039
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778103211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3778103211
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2236169872
Short name T914
Test name
Test status
Simulation time 528246780 ps
CPU time 2.09 seconds
Started Jan 14 01:02:40 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 200576 kb
Host smart-174d850f-1777-4f82-b415-aef46454c313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236169872 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2236169872
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3056855314
Short name T100
Test name
Test status
Simulation time 340291240 ps
CPU time 1.15 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:43 PM PST 24
Peak memory 200472 kb
Host smart-4533f9d2-6dc2-4ef2-9844-971ff9e4a2e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056855314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3056855314
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3770600863
Short name T878
Test name
Test status
Simulation time 415309001 ps
CPU time 1.58 seconds
Started Jan 14 01:02:42 PM PST 24
Finished Jan 14 01:02:45 PM PST 24
Peak memory 200180 kb
Host smart-72902d73-a434-4a48-955e-1b193e89e70e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770600863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3770600863
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.56836391
Short name T391
Test name
Test status
Simulation time 2431905807 ps
CPU time 3.83 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:46 PM PST 24
Peak memory 200560 kb
Host smart-b16b01a4-15a7-47e4-a037-41fd4f4dc4ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56836391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ct
rl_same_csr_outstanding.56836391
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.152870568
Short name T73
Test name
Test status
Simulation time 389752130 ps
CPU time 2.06 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 209020 kb
Host smart-486dfced-436f-4bdf-80bc-6833ebaef6ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152870568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.152870568
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.21595063
Short name T65
Test name
Test status
Simulation time 7483766355 ps
CPU time 6.27 seconds
Started Jan 14 01:02:38 PM PST 24
Finished Jan 14 01:02:48 PM PST 24
Peak memory 200812 kb
Host smart-aa1d3b59-8c90-40ac-840e-cad69c5fa5e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21595063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_int
g_err.21595063
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2732694986
Short name T98
Test name
Test status
Simulation time 605042700 ps
CPU time 1.28 seconds
Started Jan 14 01:02:40 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 200548 kb
Host smart-4d73316e-d2ec-44f0-9e07-67138e25e1be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732694986 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2732694986
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4037436646
Short name T82
Test name
Test status
Simulation time 405501341 ps
CPU time 1.03 seconds
Started Jan 14 01:02:38 PM PST 24
Finished Jan 14 01:02:43 PM PST 24
Peak memory 200476 kb
Host smart-a04ebdf4-4cc4-4984-9df0-91e3a5244795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037436646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4037436646
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1544130760
Short name T384
Test name
Test status
Simulation time 311522654 ps
CPU time 1.35 seconds
Started Jan 14 01:02:44 PM PST 24
Finished Jan 14 01:02:47 PM PST 24
Peak memory 200172 kb
Host smart-e0143385-769a-4f2c-a2f1-0a592e51cf1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544130760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1544130760
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2181177406
Short name T915
Test name
Test status
Simulation time 2208037326 ps
CPU time 2.16 seconds
Started Jan 14 01:02:41 PM PST 24
Finished Jan 14 01:02:45 PM PST 24
Peak memory 200528 kb
Host smart-044d7cac-9dd6-47cb-bc08-28fb2a5a9d2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181177406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2181177406
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1965068548
Short name T67
Test name
Test status
Simulation time 618806456 ps
CPU time 1.67 seconds
Started Jan 14 01:02:44 PM PST 24
Finished Jan 14 01:02:47 PM PST 24
Peak memory 200736 kb
Host smart-eff0fdb0-7892-421e-9661-13558e3fbacb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965068548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1965068548
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1244151080
Short name T908
Test name
Test status
Simulation time 441335884 ps
CPU time 1.08 seconds
Started Jan 14 01:02:54 PM PST 24
Finished Jan 14 01:02:56 PM PST 24
Peak memory 200584 kb
Host smart-d94ecb4b-4d14-465c-a677-4975d0abed11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244151080 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1244151080
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.917982458
Short name T37
Test name
Test status
Simulation time 532243233 ps
CPU time 1.14 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200536 kb
Host smart-c628a164-8746-4296-a812-3849fa1086a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917982458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.917982458
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1743395368
Short name T26
Test name
Test status
Simulation time 449295200 ps
CPU time 1.15 seconds
Started Jan 14 01:03:00 PM PST 24
Finished Jan 14 01:03:02 PM PST 24
Peak memory 200460 kb
Host smart-0148049c-4f6c-4762-a6e5-d2b93a817a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743395368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1743395368
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.4255943070
Short name T413
Test name
Test status
Simulation time 2916122129 ps
CPU time 7.38 seconds
Started Jan 14 01:02:56 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200688 kb
Host smart-5ecce570-800b-4b43-b369-1006f7ccac43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255943070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.4255943070
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2958833142
Short name T61
Test name
Test status
Simulation time 764338159 ps
CPU time 1.96 seconds
Started Jan 14 01:02:41 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 200804 kb
Host smart-46326f2a-29ac-44e0-8c61-85853c2090a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958833142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2958833142
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1290864437
Short name T11
Test name
Test status
Simulation time 9178682546 ps
CPU time 4.44 seconds
Started Jan 14 01:02:53 PM PST 24
Finished Jan 14 01:02:58 PM PST 24
Peak memory 200784 kb
Host smart-ff44fcb3-8af5-44c1-9b11-2209e9fe0374
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290864437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1290864437
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1272040503
Short name T894
Test name
Test status
Simulation time 528271566 ps
CPU time 1.52 seconds
Started Jan 14 01:02:44 PM PST 24
Finished Jan 14 01:02:47 PM PST 24
Peak memory 208972 kb
Host smart-c338b82a-a820-4754-b545-ab6ff9abdf3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272040503 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1272040503
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.183119895
Short name T93
Test name
Test status
Simulation time 516815241 ps
CPU time 1.95 seconds
Started Jan 14 01:02:51 PM PST 24
Finished Jan 14 01:02:54 PM PST 24
Peak memory 200568 kb
Host smart-1dfe8c54-f17c-476d-a401-020aa092f208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183119895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.183119895
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.415017198
Short name T418
Test name
Test status
Simulation time 384244929 ps
CPU time 0.71 seconds
Started Jan 14 01:02:57 PM PST 24
Finished Jan 14 01:02:58 PM PST 24
Peak memory 200192 kb
Host smart-5495f0df-517e-42ff-9db5-3106d6808978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415017198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.415017198
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1006697143
Short name T407
Test name
Test status
Simulation time 4640226528 ps
CPU time 17.7 seconds
Started Jan 14 01:02:42 PM PST 24
Finished Jan 14 01:03:02 PM PST 24
Peak memory 200816 kb
Host smart-ef040b5f-2d09-4e1e-8f14-d60276bc23d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006697143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1006697143
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.628345397
Short name T903
Test name
Test status
Simulation time 649664533 ps
CPU time 2.54 seconds
Started Jan 14 01:02:52 PM PST 24
Finished Jan 14 01:02:55 PM PST 24
Peak memory 200776 kb
Host smart-c6d38321-436b-4e02-99b9-3d3d99cfae6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628345397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.628345397
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2425683242
Short name T880
Test name
Test status
Simulation time 4342723694 ps
CPU time 4.16 seconds
Started Jan 14 01:02:51 PM PST 24
Finished Jan 14 01:02:56 PM PST 24
Peak memory 200784 kb
Host smart-8fa9a932-758c-4fbe-8db0-d828236d82ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425683242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2425683242
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2193875940
Short name T204
Test name
Test status
Simulation time 576842567 ps
CPU time 1.09 seconds
Started Jan 14 01:02:57 PM PST 24
Finished Jan 14 01:02:59 PM PST 24
Peak memory 200556 kb
Host smart-fb4e32db-d48a-4c80-a591-e6fc981f0fcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193875940 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2193875940
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.280436400
Short name T72
Test name
Test status
Simulation time 501065641 ps
CPU time 1 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200528 kb
Host smart-f63c3ac0-d629-4b65-8c55-a1bf9ecbf952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280436400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.280436400
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3795517607
Short name T378
Test name
Test status
Simulation time 498640703 ps
CPU time 1.25 seconds
Started Jan 14 01:03:00 PM PST 24
Finished Jan 14 01:03:02 PM PST 24
Peak memory 200224 kb
Host smart-d181f89b-7db5-438e-8545-a8dfe405a9f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795517607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3795517607
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2912433201
Short name T883
Test name
Test status
Simulation time 5003418580 ps
CPU time 6.24 seconds
Started Jan 14 01:02:45 PM PST 24
Finished Jan 14 01:02:52 PM PST 24
Peak memory 200708 kb
Host smart-069648c7-e163-4820-9ad8-4ee294ca8319
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912433201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2912433201
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2202301340
Short name T890
Test name
Test status
Simulation time 330181734 ps
CPU time 2.2 seconds
Started Jan 14 01:02:51 PM PST 24
Finished Jan 14 01:02:54 PM PST 24
Peak memory 200848 kb
Host smart-d9e77007-8b07-4850-b0c3-f1445f064fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202301340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2202301340
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1591618026
Short name T60
Test name
Test status
Simulation time 4443090799 ps
CPU time 11.35 seconds
Started Jan 14 01:02:57 PM PST 24
Finished Jan 14 01:03:09 PM PST 24
Peak memory 200844 kb
Host smart-bcbd5bb3-c1c4-4bcb-8298-7c4abe578e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591618026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1591618026
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.443501676
Short name T205
Test name
Test status
Simulation time 573124201 ps
CPU time 1.22 seconds
Started Jan 14 01:02:53 PM PST 24
Finished Jan 14 01:02:55 PM PST 24
Peak memory 200576 kb
Host smart-c2aacb7c-ee9b-421f-ae36-a6f989efc8d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443501676 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.443501676
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2764805448
Short name T375
Test name
Test status
Simulation time 420380445 ps
CPU time 1.66 seconds
Started Jan 14 01:02:49 PM PST 24
Finished Jan 14 01:02:51 PM PST 24
Peak memory 200528 kb
Host smart-14410333-c423-49af-9399-4afc09ae48ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764805448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2764805448
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.672823142
Short name T910
Test name
Test status
Simulation time 504055686 ps
CPU time 1.79 seconds
Started Jan 14 01:02:56 PM PST 24
Finished Jan 14 01:02:59 PM PST 24
Peak memory 200252 kb
Host smart-a332c43e-f643-4835-bec6-6e1ff303484f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672823142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.672823142
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1289795293
Short name T909
Test name
Test status
Simulation time 942930013 ps
CPU time 2.88 seconds
Started Jan 14 01:02:46 PM PST 24
Finished Jan 14 01:02:49 PM PST 24
Peak memory 217128 kb
Host smart-4a2622cd-b22d-43bc-b431-a0b1b196c235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289795293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1289795293
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4083076600
Short name T387
Test name
Test status
Simulation time 8594089477 ps
CPU time 7.18 seconds
Started Jan 14 01:02:45 PM PST 24
Finished Jan 14 01:02:53 PM PST 24
Peak memory 200652 kb
Host smart-6834c98c-8f5f-4b3f-8aca-a3f8002b1391
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083076600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4083076600
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1461151432
Short name T203
Test name
Test status
Simulation time 418030943 ps
CPU time 1.11 seconds
Started Jan 14 01:02:56 PM PST 24
Finished Jan 14 01:02:58 PM PST 24
Peak memory 200580 kb
Host smart-86296bbd-7977-4505-b7b7-599ec9ddeae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461151432 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1461151432
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.295159899
Short name T382
Test name
Test status
Simulation time 436063611 ps
CPU time 1.35 seconds
Started Jan 14 01:02:49 PM PST 24
Finished Jan 14 01:02:51 PM PST 24
Peak memory 200524 kb
Host smart-53ebca0a-97a6-4c04-9938-91bd6c5ee86c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295159899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.295159899
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3780760881
Short name T870
Test name
Test status
Simulation time 338051366 ps
CPU time 0.85 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200428 kb
Host smart-6c5136c0-2338-457f-8821-4769ff077039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780760881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3780760881
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2511427334
Short name T5
Test name
Test status
Simulation time 2369549827 ps
CPU time 2.97 seconds
Started Jan 14 01:02:52 PM PST 24
Finished Jan 14 01:02:56 PM PST 24
Peak memory 200568 kb
Host smart-205f9854-5769-4446-b9c4-fd585bb90173
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511427334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2511427334
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1946850231
Short name T912
Test name
Test status
Simulation time 469612260 ps
CPU time 2.86 seconds
Started Jan 14 01:02:49 PM PST 24
Finished Jan 14 01:02:53 PM PST 24
Peak memory 209004 kb
Host smart-1988c68e-c52c-4bf3-83e0-d3b91ec4a974
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946850231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1946850231
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1097923958
Short name T901
Test name
Test status
Simulation time 4931422208 ps
CPU time 2.56 seconds
Started Jan 14 01:02:53 PM PST 24
Finished Jan 14 01:02:56 PM PST 24
Peak memory 200756 kb
Host smart-8c2681dc-4f97-492b-8b0c-86560d4a6411
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097923958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1097923958
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2192813345
Short name T371
Test name
Test status
Simulation time 395398334 ps
CPU time 1.28 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200516 kb
Host smart-16bf0c70-c8ee-43e6-88e8-4baad554ebd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192813345 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2192813345
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.541008558
Short name T91
Test name
Test status
Simulation time 547927566 ps
CPU time 1.32 seconds
Started Jan 14 01:02:51 PM PST 24
Finished Jan 14 01:02:53 PM PST 24
Peak memory 200468 kb
Host smart-3d7bd7d7-48c2-4fe6-9631-055409dd9231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541008558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.541008558
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1626590105
Short name T396
Test name
Test status
Simulation time 363519924 ps
CPU time 1.01 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200504 kb
Host smart-cf527e82-ebd0-460a-865e-484ae6749134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626590105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1626590105
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1422540217
Short name T888
Test name
Test status
Simulation time 1992379013 ps
CPU time 2.06 seconds
Started Jan 14 01:02:59 PM PST 24
Finished Jan 14 01:03:01 PM PST 24
Peak memory 200388 kb
Host smart-19a1ca45-bdd8-42c0-8d1f-f5448d50f498
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422540217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1422540217
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.280772338
Short name T895
Test name
Test status
Simulation time 723455895 ps
CPU time 2.38 seconds
Started Jan 14 01:02:50 PM PST 24
Finished Jan 14 01:02:53 PM PST 24
Peak memory 216908 kb
Host smart-d1efaace-0a38-46f3-bef9-1976457b4c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280772338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.280772338
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3748777423
Short name T417
Test name
Test status
Simulation time 4169197413 ps
CPU time 11.65 seconds
Started Jan 14 01:03:01 PM PST 24
Finished Jan 14 01:03:14 PM PST 24
Peak memory 200944 kb
Host smart-08e7ab41-deca-444b-940f-eccaa514d01f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748777423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3748777423
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2004968971
Short name T12
Test name
Test status
Simulation time 956599659 ps
CPU time 4.06 seconds
Started Jan 14 01:02:17 PM PST 24
Finished Jan 14 01:02:22 PM PST 24
Peak memory 200828 kb
Host smart-4d096af8-58b5-4728-995f-64269bb98a7c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004968971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2004968971
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.517161957
Short name T400
Test name
Test status
Simulation time 26535084225 ps
CPU time 54.11 seconds
Started Jan 14 01:02:17 PM PST 24
Finished Jan 14 01:03:12 PM PST 24
Peak memory 200808 kb
Host smart-b9278c14-fbe7-4062-bac6-3633ef2f25c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517161957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.517161957
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1218099699
Short name T79
Test name
Test status
Simulation time 1330815211 ps
CPU time 4.02 seconds
Started Jan 14 01:02:16 PM PST 24
Finished Jan 14 01:02:20 PM PST 24
Peak memory 200512 kb
Host smart-09139e8e-9f65-435d-b399-731a1c6d3537
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218099699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1218099699
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.723926677
Short name T69
Test name
Test status
Simulation time 445426548 ps
CPU time 1.83 seconds
Started Jan 14 01:02:17 PM PST 24
Finished Jan 14 01:02:19 PM PST 24
Peak memory 200588 kb
Host smart-d047d6b5-fbe1-4958-83eb-c69d807585ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723926677 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.723926677
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.794834406
Short name T89
Test name
Test status
Simulation time 437147588 ps
CPU time 1.75 seconds
Started Jan 14 01:02:17 PM PST 24
Finished Jan 14 01:02:19 PM PST 24
Peak memory 200492 kb
Host smart-1eef7d6a-81e3-4dd3-965a-3ba208ea99c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794834406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.794834406
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2720872611
Short name T373
Test name
Test status
Simulation time 421707106 ps
CPU time 1.32 seconds
Started Jan 14 01:02:17 PM PST 24
Finished Jan 14 01:02:19 PM PST 24
Peak memory 200480 kb
Host smart-e058b34b-78de-49a6-9802-d6fc82215af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720872611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2720872611
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3841418609
Short name T95
Test name
Test status
Simulation time 4505336321 ps
CPU time 3.65 seconds
Started Jan 14 01:02:19 PM PST 24
Finished Jan 14 01:02:23 PM PST 24
Peak memory 200776 kb
Host smart-7d80b2e1-1480-4f72-8b4e-80ae601b8852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841418609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3841418609
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2630909146
Short name T408
Test name
Test status
Simulation time 378105630 ps
CPU time 2.27 seconds
Started Jan 14 01:02:11 PM PST 24
Finished Jan 14 01:02:14 PM PST 24
Peak memory 200716 kb
Host smart-594512dd-4366-48d3-923b-05ceb3fb9328
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630909146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2630909146
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3226894499
Short name T68
Test name
Test status
Simulation time 4495520525 ps
CPU time 2.89 seconds
Started Jan 14 01:02:19 PM PST 24
Finished Jan 14 01:02:22 PM PST 24
Peak memory 200804 kb
Host smart-e72614de-9c35-48c4-8aaa-72f345c05dca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226894499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3226894499
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3755400120
Short name T393
Test name
Test status
Simulation time 405105932 ps
CPU time 0.87 seconds
Started Jan 14 01:02:50 PM PST 24
Finished Jan 14 01:02:52 PM PST 24
Peak memory 200200 kb
Host smart-072e808f-e04a-4a24-834d-72212e5f72a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755400120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3755400120
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.357445824
Short name T80
Test name
Test status
Simulation time 479644986 ps
CPU time 0.88 seconds
Started Jan 14 01:02:54 PM PST 24
Finished Jan 14 01:02:55 PM PST 24
Peak memory 200164 kb
Host smart-d7299118-9f3c-4a87-bc99-cc57d66faf13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357445824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.357445824
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2831622175
Short name T889
Test name
Test status
Simulation time 350381598 ps
CPU time 0.79 seconds
Started Jan 14 01:02:54 PM PST 24
Finished Jan 14 01:02:55 PM PST 24
Peak memory 200200 kb
Host smart-85d626e7-f34f-49e5-b061-c610106ace58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831622175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2831622175
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1566497395
Short name T906
Test name
Test status
Simulation time 504627149 ps
CPU time 1.77 seconds
Started Jan 14 01:02:58 PM PST 24
Finished Jan 14 01:03:00 PM PST 24
Peak memory 200376 kb
Host smart-c54ba8d7-29d0-40cd-ade7-e0025b713214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566497395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1566497395
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3883892717
Short name T900
Test name
Test status
Simulation time 498646029 ps
CPU time 1.73 seconds
Started Jan 14 01:02:57 PM PST 24
Finished Jan 14 01:02:59 PM PST 24
Peak memory 200448 kb
Host smart-075fae08-9eee-4477-896b-3a1553d45beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883892717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3883892717
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1419289969
Short name T206
Test name
Test status
Simulation time 340019922 ps
CPU time 0.8 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200444 kb
Host smart-342d61a5-2872-460f-854d-0e9bd766b85a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419289969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1419289969
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1064562799
Short name T402
Test name
Test status
Simulation time 367141320 ps
CPU time 0.85 seconds
Started Jan 14 01:03:01 PM PST 24
Finished Jan 14 01:03:02 PM PST 24
Peak memory 200376 kb
Host smart-983402fd-b1f8-4f8d-bd0e-cc419c438c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064562799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1064562799
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.635780209
Short name T392
Test name
Test status
Simulation time 474845441 ps
CPU time 0.9 seconds
Started Jan 14 01:03:01 PM PST 24
Finished Jan 14 01:03:03 PM PST 24
Peak memory 200368 kb
Host smart-7351e1dd-c973-48d2-b093-a34eae651775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635780209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.635780209
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.107025299
Short name T78
Test name
Test status
Simulation time 428579906 ps
CPU time 1.51 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200140 kb
Host smart-d97e82e4-d59d-4d80-8dbd-d2047a713e5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107025299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.107025299
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2618311390
Short name T372
Test name
Test status
Simulation time 526935525 ps
CPU time 0.75 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200416 kb
Host smart-3fd1e59c-d8f1-4a93-b879-8424e1fc3968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618311390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2618311390
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3981028084
Short name T374
Test name
Test status
Simulation time 824816949 ps
CPU time 3.31 seconds
Started Jan 14 01:02:19 PM PST 24
Finished Jan 14 01:02:23 PM PST 24
Peak memory 200724 kb
Host smart-d9bafb8d-2844-4dfb-b548-794cd915da37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981028084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3981028084
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3345014935
Short name T84
Test name
Test status
Simulation time 51822070384 ps
CPU time 104.96 seconds
Started Jan 14 01:02:21 PM PST 24
Finished Jan 14 01:04:06 PM PST 24
Peak memory 200660 kb
Host smart-115160ed-7ac7-4643-a56d-ffba9f3d35da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345014935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3345014935
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.736764174
Short name T885
Test name
Test status
Simulation time 779383444 ps
CPU time 2.5 seconds
Started Jan 14 01:02:21 PM PST 24
Finished Jan 14 01:02:24 PM PST 24
Peak memory 200440 kb
Host smart-3da81bef-835e-4d98-829d-b5b433425444
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736764174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.736764174
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3043345356
Short name T401
Test name
Test status
Simulation time 350015609 ps
CPU time 1.07 seconds
Started Jan 14 01:02:17 PM PST 24
Finished Jan 14 01:02:19 PM PST 24
Peak memory 200600 kb
Host smart-e081dc62-0b04-4da3-a0a4-45032fea4bf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043345356 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3043345356
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1953557397
Short name T88
Test name
Test status
Simulation time 489508415 ps
CPU time 1.99 seconds
Started Jan 14 01:02:17 PM PST 24
Finished Jan 14 01:02:19 PM PST 24
Peak memory 200524 kb
Host smart-f8e4bf72-5461-49cf-9b4d-8e31ae9a95c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953557397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1953557397
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.42877552
Short name T376
Test name
Test status
Simulation time 400628480 ps
CPU time 1.08 seconds
Started Jan 14 01:02:17 PM PST 24
Finished Jan 14 01:02:19 PM PST 24
Peak memory 200544 kb
Host smart-4b22f2d4-e0cc-4844-b85c-304337c41692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42877552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.42877552
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4020945588
Short name T9
Test name
Test status
Simulation time 4614567480 ps
CPU time 3.75 seconds
Started Jan 14 01:02:19 PM PST 24
Finished Jan 14 01:02:23 PM PST 24
Peak memory 200840 kb
Host smart-fc5c833a-7687-412d-8f54-cb9ba59f4e60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020945588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4020945588
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3568153604
Short name T76
Test name
Test status
Simulation time 720251778 ps
CPU time 1.43 seconds
Started Jan 14 01:02:18 PM PST 24
Finished Jan 14 01:02:20 PM PST 24
Peak memory 200784 kb
Host smart-db475de1-08b8-4f5d-a52c-7aebc4c764e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568153604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3568153604
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.443047307
Short name T416
Test name
Test status
Simulation time 4541093272 ps
CPU time 4.21 seconds
Started Jan 14 01:02:19 PM PST 24
Finished Jan 14 01:02:24 PM PST 24
Peak memory 200752 kb
Host smart-0d2108c2-3195-4d1e-88b4-ec2286b43875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443047307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.443047307
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1347538129
Short name T370
Test name
Test status
Simulation time 502271406 ps
CPU time 0.93 seconds
Started Jan 14 01:02:56 PM PST 24
Finished Jan 14 01:02:58 PM PST 24
Peak memory 200216 kb
Host smart-a19b08c6-14c9-4f3c-9807-454c958c0c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347538129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1347538129
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.4289674196
Short name T7
Test name
Test status
Simulation time 444579485 ps
CPU time 0.92 seconds
Started Jan 14 01:03:01 PM PST 24
Finished Jan 14 01:03:02 PM PST 24
Peak memory 200488 kb
Host smart-0c9150a9-8b8e-47f1-8a84-f3e0ea1e9bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289674196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.4289674196
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2532199355
Short name T876
Test name
Test status
Simulation time 287574400 ps
CPU time 1.32 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:05 PM PST 24
Peak memory 200272 kb
Host smart-e2154c8f-4f66-43f4-bfd1-4d2b7db6daa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532199355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2532199355
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1323928221
Short name T403
Test name
Test status
Simulation time 364405980 ps
CPU time 1.52 seconds
Started Jan 14 01:03:01 PM PST 24
Finished Jan 14 01:03:03 PM PST 24
Peak memory 200504 kb
Host smart-26ed0d03-7975-490d-823f-73c83b31a1a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323928221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1323928221
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3931207389
Short name T379
Test name
Test status
Simulation time 500245538 ps
CPU time 1.68 seconds
Started Jan 14 01:03:00 PM PST 24
Finished Jan 14 01:03:02 PM PST 24
Peak memory 200504 kb
Host smart-7701b440-9322-426c-94db-31326115254e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931207389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3931207389
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.526611271
Short name T405
Test name
Test status
Simulation time 524320491 ps
CPU time 1.78 seconds
Started Jan 14 01:02:57 PM PST 24
Finished Jan 14 01:02:59 PM PST 24
Peak memory 200380 kb
Host smart-4bd74247-c980-41a0-ae12-a0e3bb446219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526611271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.526611271
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1789221847
Short name T872
Test name
Test status
Simulation time 428262255 ps
CPU time 0.93 seconds
Started Jan 14 01:03:00 PM PST 24
Finished Jan 14 01:03:02 PM PST 24
Peak memory 200276 kb
Host smart-f73028c7-7dc6-4bb7-886f-a769c46856d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789221847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1789221847
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3101994126
Short name T380
Test name
Test status
Simulation time 568366410 ps
CPU time 0.75 seconds
Started Jan 14 01:03:02 PM PST 24
Finished Jan 14 01:03:04 PM PST 24
Peak memory 200428 kb
Host smart-f4fc7aa9-3997-442e-acc9-a6145865951c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101994126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3101994126
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1723473817
Short name T899
Test name
Test status
Simulation time 492021202 ps
CPU time 1.8 seconds
Started Jan 14 01:03:03 PM PST 24
Finished Jan 14 01:03:06 PM PST 24
Peak memory 200292 kb
Host smart-d73789dc-9f30-4d99-8afb-9e50ab81c03a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723473817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1723473817
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2296376624
Short name T386
Test name
Test status
Simulation time 331854697 ps
CPU time 1.46 seconds
Started Jan 14 01:03:00 PM PST 24
Finished Jan 14 01:03:01 PM PST 24
Peak memory 200208 kb
Host smart-8aec1f34-45d1-42ba-9ce2-0d9e1a86ebde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296376624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2296376624
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1747047952
Short name T90
Test name
Test status
Simulation time 1141855837 ps
CPU time 3.69 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:33 PM PST 24
Peak memory 200832 kb
Host smart-2a34a643-6608-48f3-8c57-95543cd7c612
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747047952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1747047952
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2505321765
Short name T36
Test name
Test status
Simulation time 53161101678 ps
CPU time 119.39 seconds
Started Jan 14 01:02:20 PM PST 24
Finished Jan 14 01:04:20 PM PST 24
Peak memory 200732 kb
Host smart-ba5487c8-4a7e-4f26-b745-7a2bfc8a984a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505321765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2505321765
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2441804740
Short name T877
Test name
Test status
Simulation time 764766959 ps
CPU time 1.64 seconds
Started Jan 14 01:02:23 PM PST 24
Finished Jan 14 01:02:25 PM PST 24
Peak memory 200568 kb
Host smart-391d3b26-3109-4ade-bd0f-af6ff73042de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441804740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2441804740
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1082935339
Short name T389
Test name
Test status
Simulation time 357336716 ps
CPU time 1.57 seconds
Started Jan 14 01:02:26 PM PST 24
Finished Jan 14 01:02:28 PM PST 24
Peak memory 200596 kb
Host smart-bee843f8-36d0-4b52-823f-36ef807fc95c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082935339 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1082935339
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.795357137
Short name T86
Test name
Test status
Simulation time 374509954 ps
CPU time 0.92 seconds
Started Jan 14 01:02:21 PM PST 24
Finished Jan 14 01:02:22 PM PST 24
Peak memory 200508 kb
Host smart-ad69616a-e87e-4f95-a0db-7c429f94b38f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795357137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.795357137
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1202744046
Short name T390
Test name
Test status
Simulation time 308015661 ps
CPU time 1.31 seconds
Started Jan 14 01:02:21 PM PST 24
Finished Jan 14 01:02:23 PM PST 24
Peak memory 200336 kb
Host smart-2a967735-4f71-416c-9945-d265d8ab96f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202744046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1202744046
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1910773720
Short name T97
Test name
Test status
Simulation time 2704291804 ps
CPU time 4.09 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:33 PM PST 24
Peak memory 200552 kb
Host smart-af2f2b28-79f1-4205-821c-3767fe27225d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910773720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1910773720
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3760137827
Short name T415
Test name
Test status
Simulation time 446908639 ps
CPU time 2.59 seconds
Started Jan 14 01:02:19 PM PST 24
Finished Jan 14 01:02:22 PM PST 24
Peak memory 217108 kb
Host smart-a39efaa6-fe35-4e58-a8ce-f60cf745cfd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760137827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3760137827
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2470016555
Short name T357
Test name
Test status
Simulation time 4502593311 ps
CPU time 11.09 seconds
Started Jan 14 01:02:20 PM PST 24
Finished Jan 14 01:02:32 PM PST 24
Peak memory 200656 kb
Host smart-943ee5bb-0a29-419a-a554-c576f75c8660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470016555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2470016555
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1499864630
Short name T28
Test name
Test status
Simulation time 302054247 ps
CPU time 1.36 seconds
Started Jan 14 01:03:00 PM PST 24
Finished Jan 14 01:03:02 PM PST 24
Peak memory 200132 kb
Host smart-0c48b503-2bf1-4835-879b-0bc201fd5b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499864630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1499864630
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1902726410
Short name T904
Test name
Test status
Simulation time 316091520 ps
CPU time 0.82 seconds
Started Jan 14 01:03:03 PM PST 24
Finished Jan 14 01:03:05 PM PST 24
Peak memory 200428 kb
Host smart-dbcb5dc6-637f-4090-a8df-514a53c8b187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902726410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1902726410
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4107731021
Short name T913
Test name
Test status
Simulation time 394057397 ps
CPU time 1.48 seconds
Started Jan 14 01:03:01 PM PST 24
Finished Jan 14 01:03:03 PM PST 24
Peak memory 200320 kb
Host smart-4c3c96fd-71b9-4f7a-a577-7891762413df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107731021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.4107731021
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.347842996
Short name T892
Test name
Test status
Simulation time 302533664 ps
CPU time 1.36 seconds
Started Jan 14 01:03:00 PM PST 24
Finished Jan 14 01:03:01 PM PST 24
Peak memory 200176 kb
Host smart-e65f42e2-785d-46a8-a7e6-bbbd748cccc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347842996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.347842996
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3833386383
Short name T874
Test name
Test status
Simulation time 528862427 ps
CPU time 1.72 seconds
Started Jan 14 01:03:03 PM PST 24
Finished Jan 14 01:03:06 PM PST 24
Peak memory 200268 kb
Host smart-d9f8112b-f2c7-4e39-a48f-174e96a46972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833386383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3833386383
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1946309176
Short name T34
Test name
Test status
Simulation time 464126470 ps
CPU time 1.82 seconds
Started Jan 14 01:03:07 PM PST 24
Finished Jan 14 01:03:10 PM PST 24
Peak memory 200228 kb
Host smart-43ce1b5b-a44f-406e-aab3-587298aa29ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946309176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1946309176
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.57466633
Short name T394
Test name
Test status
Simulation time 411920353 ps
CPU time 0.83 seconds
Started Jan 14 01:03:06 PM PST 24
Finished Jan 14 01:03:07 PM PST 24
Peak memory 200156 kb
Host smart-83a7e7ab-6188-4d0c-87e8-91efb5eb42a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57466633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.57466633
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1719616974
Short name T884
Test name
Test status
Simulation time 398273624 ps
CPU time 1.6 seconds
Started Jan 14 01:03:08 PM PST 24
Finished Jan 14 01:03:10 PM PST 24
Peak memory 200456 kb
Host smart-e2e90200-b5a3-4dee-915d-cddaec89988d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719616974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1719616974
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.231101989
Short name T87
Test name
Test status
Simulation time 392052118 ps
CPU time 1.55 seconds
Started Jan 14 01:03:09 PM PST 24
Finished Jan 14 01:03:11 PM PST 24
Peak memory 200160 kb
Host smart-dc80c1c7-94c6-483f-88d3-eac036a5178d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231101989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.231101989
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.129306623
Short name T2
Test name
Test status
Simulation time 515020112 ps
CPU time 2.01 seconds
Started Jan 14 01:02:26 PM PST 24
Finished Jan 14 01:02:28 PM PST 24
Peak memory 200528 kb
Host smart-921be8c1-4dab-4250-8a8f-fbef38c9a915
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129306623 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.129306623
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3837012950
Short name T10
Test name
Test status
Simulation time 505166331 ps
CPU time 1.87 seconds
Started Jan 14 01:02:25 PM PST 24
Finished Jan 14 01:02:27 PM PST 24
Peak memory 200488 kb
Host smart-1898990f-531f-43a4-9454-e5aebe2098f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837012950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3837012950
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3752860572
Short name T395
Test name
Test status
Simulation time 2684475745 ps
CPU time 4.08 seconds
Started Jan 14 01:02:27 PM PST 24
Finished Jan 14 01:02:31 PM PST 24
Peak memory 200628 kb
Host smart-c62c4b09-98d3-486d-9d1c-d83a3138e68a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752860572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3752860572
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3578109513
Short name T409
Test name
Test status
Simulation time 472251464 ps
CPU time 2.52 seconds
Started Jan 14 01:02:29 PM PST 24
Finished Jan 14 01:02:32 PM PST 24
Peak memory 200816 kb
Host smart-acf718f8-7680-428b-a215-962954bec12c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578109513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3578109513
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.745209307
Short name T1
Test name
Test status
Simulation time 4619141046 ps
CPU time 6.98 seconds
Started Jan 14 01:02:27 PM PST 24
Finished Jan 14 01:02:35 PM PST 24
Peak memory 200692 kb
Host smart-a5e9bfda-806d-440e-954b-6ea5820bf655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745209307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.745209307
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2281958887
Short name T871
Test name
Test status
Simulation time 633610145 ps
CPU time 1.21 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:29 PM PST 24
Peak memory 200628 kb
Host smart-260c7f43-ecbb-4913-9dcb-0cd7a2db6844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281958887 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2281958887
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3416566770
Short name T99
Test name
Test status
Simulation time 433370831 ps
CPU time 1.06 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:30 PM PST 24
Peak memory 200484 kb
Host smart-9b811c09-3bb1-4652-bd13-1764ab3ea491
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416566770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3416566770
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1450196218
Short name T882
Test name
Test status
Simulation time 307733158 ps
CPU time 1.12 seconds
Started Jan 14 01:02:27 PM PST 24
Finished Jan 14 01:02:29 PM PST 24
Peak memory 200240 kb
Host smart-e6f53516-0a57-4469-bf25-ddda9f90f41c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450196218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1450196218
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.538335310
Short name T31
Test name
Test status
Simulation time 2622970963 ps
CPU time 2.66 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:31 PM PST 24
Peak memory 200536 kb
Host smart-cb27087d-5600-4484-b658-545b649dcc73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538335310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.538335310
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1440732623
Short name T881
Test name
Test status
Simulation time 1134948609 ps
CPU time 3.02 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:32 PM PST 24
Peak memory 216856 kb
Host smart-629a9eb5-d689-415a-b29a-b239ec0d674a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440732623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1440732623
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4217976741
Short name T893
Test name
Test status
Simulation time 4654784664 ps
CPU time 13.43 seconds
Started Jan 14 01:02:26 PM PST 24
Finished Jan 14 01:02:40 PM PST 24
Peak memory 200788 kb
Host smart-bcbccad6-8fb1-40f7-af34-c83c651b54ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217976741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4217976741
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2657846201
Short name T879
Test name
Test status
Simulation time 541459740 ps
CPU time 1.49 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:30 PM PST 24
Peak memory 200600 kb
Host smart-9b120919-71f9-408e-8737-e50d4ed7db37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657846201 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2657846201
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2297716500
Short name T898
Test name
Test status
Simulation time 409424839 ps
CPU time 0.83 seconds
Started Jan 14 01:02:27 PM PST 24
Finished Jan 14 01:02:29 PM PST 24
Peak memory 200524 kb
Host smart-9fdda72b-5cfe-48c6-aa69-0bef7101453f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297716500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2297716500
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1102201621
Short name T96
Test name
Test status
Simulation time 425914831 ps
CPU time 1.49 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:30 PM PST 24
Peak memory 200252 kb
Host smart-bb2c06b0-f618-4dbc-bb5b-90f11263bc80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102201621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1102201621
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2540537994
Short name T905
Test name
Test status
Simulation time 5156174910 ps
CPU time 4.06 seconds
Started Jan 14 01:02:29 PM PST 24
Finished Jan 14 01:02:33 PM PST 24
Peak memory 200840 kb
Host smart-9ee755aa-1e42-4855-b1f6-0ec819238eb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540537994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2540537994
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1703609370
Short name T399
Test name
Test status
Simulation time 539590143 ps
CPU time 2.69 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:31 PM PST 24
Peak memory 200712 kb
Host smart-310affdc-a2df-472c-9a1a-a99ed093ff75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703609370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1703609370
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.289444282
Short name T74
Test name
Test status
Simulation time 7822899702 ps
CPU time 12.02 seconds
Started Jan 14 01:02:28 PM PST 24
Finished Jan 14 01:02:40 PM PST 24
Peak memory 200716 kb
Host smart-7d923160-5b41-4a8a-b358-b5b60d311da6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289444282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.289444282
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1012642882
Short name T3
Test name
Test status
Simulation time 463973176 ps
CPU time 1.1 seconds
Started Jan 14 01:02:32 PM PST 24
Finished Jan 14 01:02:34 PM PST 24
Peak memory 200564 kb
Host smart-d94f6c96-c35b-479e-af76-af69ef6fb68d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012642882 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1012642882
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4162997661
Short name T896
Test name
Test status
Simulation time 531677616 ps
CPU time 1.85 seconds
Started Jan 14 01:02:29 PM PST 24
Finished Jan 14 01:02:31 PM PST 24
Peak memory 200560 kb
Host smart-24d0658a-1fb9-45f5-9916-a2f6ba9e9184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162997661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4162997661
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.104326407
Short name T385
Test name
Test status
Simulation time 448805649 ps
CPU time 0.89 seconds
Started Jan 14 01:02:30 PM PST 24
Finished Jan 14 01:02:31 PM PST 24
Peak memory 200296 kb
Host smart-10589966-5313-4d98-b49b-0b5c0c35d668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104326407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.104326407
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2466163932
Short name T101
Test name
Test status
Simulation time 2127222695 ps
CPU time 1.53 seconds
Started Jan 14 01:02:31 PM PST 24
Finished Jan 14 01:02:34 PM PST 24
Peak memory 200392 kb
Host smart-eef34771-f1ea-47ff-bdf9-c836c390b53c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466163932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2466163932
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3857860109
Short name T62
Test name
Test status
Simulation time 451796981 ps
CPU time 3.31 seconds
Started Jan 14 01:02:31 PM PST 24
Finished Jan 14 01:02:35 PM PST 24
Peak memory 208860 kb
Host smart-5fdfd423-5f05-446f-8d23-cd85facc643b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857860109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3857860109
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3199196940
Short name T64
Test name
Test status
Simulation time 8412426604 ps
CPU time 23.58 seconds
Started Jan 14 01:02:31 PM PST 24
Finished Jan 14 01:02:55 PM PST 24
Peak memory 200720 kb
Host smart-5ebbf8f2-2997-4782-ab0c-18019179b372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199196940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3199196940
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2051737658
Short name T8
Test name
Test status
Simulation time 552133649 ps
CPU time 2.07 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 200624 kb
Host smart-4b9196d9-6673-4a31-b611-4b051f42e46e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051737658 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2051737658
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1885524780
Short name T902
Test name
Test status
Simulation time 485826566 ps
CPU time 1.01 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:43 PM PST 24
Peak memory 200560 kb
Host smart-e9424db1-ce2e-4f42-8992-e0d794970ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885524780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1885524780
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4079291959
Short name T70
Test name
Test status
Simulation time 403647935 ps
CPU time 1.09 seconds
Started Jan 14 01:02:38 PM PST 24
Finished Jan 14 01:02:43 PM PST 24
Peak memory 200468 kb
Host smart-53b6e87c-09bc-47f2-a31f-3ad84808c773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079291959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4079291959
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.697643216
Short name T411
Test name
Test status
Simulation time 2507247126 ps
CPU time 2.02 seconds
Started Jan 14 01:02:36 PM PST 24
Finished Jan 14 01:02:44 PM PST 24
Peak memory 200532 kb
Host smart-12fc0bca-01e0-46cd-ae0b-16e97f383cc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697643216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.697643216
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.289251767
Short name T75
Test name
Test status
Simulation time 366981121 ps
CPU time 2.95 seconds
Started Jan 14 01:02:32 PM PST 24
Finished Jan 14 01:02:36 PM PST 24
Peak memory 208976 kb
Host smart-0a5a0e51-bcf9-445b-8c8f-d0806d18e640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289251767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.289251767
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.626877647
Short name T412
Test name
Test status
Simulation time 9309990079 ps
CPU time 4.77 seconds
Started Jan 14 01:02:39 PM PST 24
Finished Jan 14 01:02:47 PM PST 24
Peak memory 200788 kb
Host smart-ac47d227-16e0-4eb9-885c-59045235e395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626877647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.626877647
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2672133634
Short name T695
Test name
Test status
Simulation time 491852720 ps
CPU time 1.81 seconds
Started Jan 14 01:33:29 PM PST 24
Finished Jan 14 01:33:31 PM PST 24
Peak memory 200648 kb
Host smart-2043f4e6-f73a-4232-aa90-5b6032c35fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672133634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2672133634
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.228438772
Short name T20
Test name
Test status
Simulation time 167920787429 ps
CPU time 192.98 seconds
Started Jan 14 01:33:27 PM PST 24
Finished Jan 14 01:36:41 PM PST 24
Peak memory 200964 kb
Host smart-68588c82-41ac-4fde-8081-223343da1102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228438772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.228438772
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1579266497
Short name T805
Test name
Test status
Simulation time 485706889360 ps
CPU time 1157.2 seconds
Started Jan 14 01:33:29 PM PST 24
Finished Jan 14 01:52:46 PM PST 24
Peak memory 200972 kb
Host smart-37e9ae6e-99a6-4413-a35f-8145e642d41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579266497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1579266497
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4183202582
Short name T196
Test name
Test status
Simulation time 325015986313 ps
CPU time 60.69 seconds
Started Jan 14 01:33:34 PM PST 24
Finished Jan 14 01:34:36 PM PST 24
Peak memory 200872 kb
Host smart-743d6074-afca-4582-b417-e10caf249b25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183202582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4183202582
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2432543137
Short name T635
Test name
Test status
Simulation time 483699778223 ps
CPU time 640.47 seconds
Started Jan 14 01:33:36 PM PST 24
Finished Jan 14 01:44:18 PM PST 24
Peak memory 200972 kb
Host smart-6da51f65-8eb7-4f41-9f6a-b2def71062b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432543137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2432543137
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2726084637
Short name T598
Test name
Test status
Simulation time 165931684312 ps
CPU time 95.65 seconds
Started Jan 14 01:33:35 PM PST 24
Finished Jan 14 01:35:11 PM PST 24
Peak memory 200868 kb
Host smart-d7047490-97eb-4ebc-a038-02fbba90a2e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726084637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2726084637
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2830600432
Short name T147
Test name
Test status
Simulation time 166640329201 ps
CPU time 416.76 seconds
Started Jan 14 01:33:28 PM PST 24
Finished Jan 14 01:40:25 PM PST 24
Peak memory 200880 kb
Host smart-25e43ee4-7f36-4c98-9c32-acbf71d95e29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830600432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2830600432
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2924291222
Short name T210
Test name
Test status
Simulation time 105796614215 ps
CPU time 367.79 seconds
Started Jan 14 01:33:29 PM PST 24
Finished Jan 14 01:39:38 PM PST 24
Peak memory 201276 kb
Host smart-4aac890f-9ea1-42ca-b330-983914a67dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924291222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2924291222
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2565171731
Short name T697
Test name
Test status
Simulation time 36881686251 ps
CPU time 15.53 seconds
Started Jan 14 01:33:31 PM PST 24
Finished Jan 14 01:33:47 PM PST 24
Peak memory 200708 kb
Host smart-43f0e66c-fb46-4718-8a2e-d8a742730288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565171731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2565171731
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2134755083
Short name T759
Test name
Test status
Simulation time 5275819528 ps
CPU time 12.5 seconds
Started Jan 14 01:33:35 PM PST 24
Finished Jan 14 01:33:48 PM PST 24
Peak memory 200728 kb
Host smart-2c4c95c2-362c-4fc2-89c7-73c9b76da6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134755083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2134755083
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2755066913
Short name T47
Test name
Test status
Simulation time 3935832751 ps
CPU time 9.59 seconds
Started Jan 14 01:33:32 PM PST 24
Finished Jan 14 01:33:42 PM PST 24
Peak memory 216028 kb
Host smart-772bfe58-95aa-4137-9945-b6307a7f03c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755066913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2755066913
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.847535650
Short name T482
Test name
Test status
Simulation time 5942847425 ps
CPU time 8 seconds
Started Jan 14 01:33:33 PM PST 24
Finished Jan 14 01:33:42 PM PST 24
Peak memory 200708 kb
Host smart-f35edc02-9baf-4ccd-af12-081c41434a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847535650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.847535650
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.725533559
Short name T195
Test name
Test status
Simulation time 96977384454 ps
CPU time 172.51 seconds
Started Jan 14 01:33:27 PM PST 24
Finished Jan 14 01:36:20 PM PST 24
Peak memory 209720 kb
Host smart-9b24e96b-6503-4fbc-8c75-ea99342579b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725533559 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.725533559
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2331860752
Short name T541
Test name
Test status
Simulation time 529232517 ps
CPU time 1.26 seconds
Started Jan 14 01:33:46 PM PST 24
Finished Jan 14 01:33:48 PM PST 24
Peak memory 200640 kb
Host smart-6b6135b8-f08c-4e3a-af5e-29154cc9f32d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331860752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2331860752
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.896529919
Short name T534
Test name
Test status
Simulation time 329803580213 ps
CPU time 729.31 seconds
Started Jan 14 01:33:30 PM PST 24
Finished Jan 14 01:45:40 PM PST 24
Peak memory 200828 kb
Host smart-7c287624-141c-4bc0-801a-2f01566c234c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=896529919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.896529919
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1707792792
Short name T17
Test name
Test status
Simulation time 163000088930 ps
CPU time 102.55 seconds
Started Jan 14 01:33:33 PM PST 24
Finished Jan 14 01:35:16 PM PST 24
Peak memory 200912 kb
Host smart-ed109200-bd76-4662-9c91-ce0479241657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707792792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1707792792
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.552720486
Short name T514
Test name
Test status
Simulation time 499865081548 ps
CPU time 304.83 seconds
Started Jan 14 01:33:30 PM PST 24
Finished Jan 14 01:38:35 PM PST 24
Peak memory 200864 kb
Host smart-a8cc3602-a44b-4e14-a256-a238d20415c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=552720486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.552720486
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1106955122
Short name T307
Test name
Test status
Simulation time 336664371879 ps
CPU time 831.66 seconds
Started Jan 14 01:33:38 PM PST 24
Finished Jan 14 01:47:30 PM PST 24
Peak memory 200964 kb
Host smart-f4883b9e-ffb4-4a61-ac28-ce9c917d47af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106955122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1106955122
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1824095206
Short name T648
Test name
Test status
Simulation time 97382264440 ps
CPU time 513.02 seconds
Started Jan 14 01:33:37 PM PST 24
Finished Jan 14 01:42:10 PM PST 24
Peak memory 201492 kb
Host smart-b86025e6-fa7b-4855-a672-b5685e332a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824095206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1824095206
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.4135748473
Short name T721
Test name
Test status
Simulation time 38243166411 ps
CPU time 18.11 seconds
Started Jan 14 01:33:39 PM PST 24
Finished Jan 14 01:33:57 PM PST 24
Peak memory 200760 kb
Host smart-b671a18b-872c-4452-aeab-eb24a12e70aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135748473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.4135748473
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2439310368
Short name T458
Test name
Test status
Simulation time 3915403316 ps
CPU time 5.14 seconds
Started Jan 14 01:33:35 PM PST 24
Finished Jan 14 01:33:41 PM PST 24
Peak memory 200668 kb
Host smart-2b91b40c-1923-4fac-88ae-b42a1baccf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439310368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2439310368
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1378567340
Short name T48
Test name
Test status
Simulation time 7757092412 ps
CPU time 19.29 seconds
Started Jan 14 01:33:39 PM PST 24
Finished Jan 14 01:33:59 PM PST 24
Peak memory 217164 kb
Host smart-16efb37b-ba4e-4bf0-a09d-c9819305415d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378567340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1378567340
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1444834222
Short name T839
Test name
Test status
Simulation time 6019816818 ps
CPU time 7.86 seconds
Started Jan 14 01:33:29 PM PST 24
Finished Jan 14 01:33:37 PM PST 24
Peak memory 200716 kb
Host smart-6fb4479f-27dd-4319-bfa3-7ef79e5a0fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444834222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1444834222
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.89096620
Short name T236
Test name
Test status
Simulation time 358742184221 ps
CPU time 132.7 seconds
Started Jan 14 01:33:40 PM PST 24
Finished Jan 14 01:35:54 PM PST 24
Peak memory 200900 kb
Host smart-f5666894-8395-40d3-ab6c-b732db64fac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89096620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.89096620
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3509988928
Short name T727
Test name
Test status
Simulation time 101441604516 ps
CPU time 228.19 seconds
Started Jan 14 01:33:39 PM PST 24
Finished Jan 14 01:37:27 PM PST 24
Peak memory 217572 kb
Host smart-49d2363e-7932-48b4-9f23-97cb26ef1ebc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509988928 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3509988928
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3302383351
Short name T649
Test name
Test status
Simulation time 166009602670 ps
CPU time 381.12 seconds
Started Jan 14 01:33:49 PM PST 24
Finished Jan 14 01:40:11 PM PST 24
Peak memory 200868 kb
Host smart-f87f3b92-aaef-4b92-80ec-a0c99dc12cff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302383351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3302383351
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1606494150
Short name T710
Test name
Test status
Simulation time 496765650528 ps
CPU time 885.06 seconds
Started Jan 14 01:33:55 PM PST 24
Finished Jan 14 01:48:41 PM PST 24
Peak memory 200988 kb
Host smart-f71deffa-cb7b-4a00-b07d-a379372946ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606494150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1606494150
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2469238411
Short name T463
Test name
Test status
Simulation time 164798087281 ps
CPU time 203.77 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:37:28 PM PST 24
Peak memory 200952 kb
Host smart-b8a75f19-ae89-4c5e-a7f5-d98037a7406b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469238411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2469238411
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.980552029
Short name T724
Test name
Test status
Simulation time 325151379019 ps
CPU time 741.56 seconds
Started Jan 14 01:33:52 PM PST 24
Finished Jan 14 01:46:15 PM PST 24
Peak memory 200832 kb
Host smart-aa2c7421-e4b2-4879-b88a-b4ffc37d9d17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=980552029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.980552029
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.336588958
Short name T506
Test name
Test status
Simulation time 328356461618 ps
CPU time 308.76 seconds
Started Jan 14 01:33:49 PM PST 24
Finished Jan 14 01:38:58 PM PST 24
Peak memory 200848 kb
Host smart-768ed34f-98ca-4e9e-9c66-0c71e83870be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336588958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.336588958
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.616845445
Short name T717
Test name
Test status
Simulation time 96337943845 ps
CPU time 381.18 seconds
Started Jan 14 01:33:59 PM PST 24
Finished Jan 14 01:40:21 PM PST 24
Peak memory 201332 kb
Host smart-fda0ae69-f7aa-4494-a764-dbbe7413d9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616845445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.616845445
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.315244627
Short name T542
Test name
Test status
Simulation time 33007184834 ps
CPU time 18.51 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:34:23 PM PST 24
Peak memory 200764 kb
Host smart-a7985302-1af5-4d19-b4f8-c5f4b0a0f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315244627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.315244627
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.43590572
Short name T105
Test name
Test status
Simulation time 4037769429 ps
CPU time 5.14 seconds
Started Jan 14 01:33:50 PM PST 24
Finished Jan 14 01:33:55 PM PST 24
Peak memory 200760 kb
Host smart-70140f28-1331-432d-830a-eb373b6dc740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43590572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.43590572
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3420296813
Short name T597
Test name
Test status
Simulation time 5865729942 ps
CPU time 14 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:34:19 PM PST 24
Peak memory 200704 kb
Host smart-e293536c-5a85-4a8c-8151-f9c83cdbbebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420296813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3420296813
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1693652588
Short name T350
Test name
Test status
Simulation time 179374113478 ps
CPU time 170.67 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:36:48 PM PST 24
Peak memory 215608 kb
Host smart-d534d35f-397e-4efc-a1d4-196aaae4a782
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693652588 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1693652588
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3314793544
Short name T637
Test name
Test status
Simulation time 442579232 ps
CPU time 1.62 seconds
Started Jan 14 01:33:59 PM PST 24
Finished Jan 14 01:34:02 PM PST 24
Peak memory 200664 kb
Host smart-fb833cbd-1809-470e-90a7-2e008eba7304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314793544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3314793544
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1621609766
Short name T223
Test name
Test status
Simulation time 166815467343 ps
CPU time 212.74 seconds
Started Jan 14 01:34:00 PM PST 24
Finished Jan 14 01:37:34 PM PST 24
Peak memory 200936 kb
Host smart-ed41fc64-562f-41e3-a248-c74fa7416791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621609766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1621609766
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2172083755
Short name T862
Test name
Test status
Simulation time 161360657642 ps
CPU time 93.28 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:35:38 PM PST 24
Peak memory 200912 kb
Host smart-e88a9b99-9e91-4aea-8af3-9cee3d0baf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172083755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2172083755
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3486783241
Short name T827
Test name
Test status
Simulation time 491332933032 ps
CPU time 293.92 seconds
Started Jan 14 01:34:00 PM PST 24
Finished Jan 14 01:38:55 PM PST 24
Peak memory 200868 kb
Host smart-12651880-5aca-4f4a-8c61-76a2dee93985
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486783241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3486783241
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2163092160
Short name T132
Test name
Test status
Simulation time 501047852486 ps
CPU time 287.59 seconds
Started Jan 14 01:34:07 PM PST 24
Finished Jan 14 01:38:59 PM PST 24
Peak memory 200860 kb
Host smart-2d985ee6-a7cf-4b08-93c9-42801269bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163092160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2163092160
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2946454716
Short name T741
Test name
Test status
Simulation time 163578955537 ps
CPU time 97.73 seconds
Started Jan 14 01:34:06 PM PST 24
Finished Jan 14 01:35:45 PM PST 24
Peak memory 200776 kb
Host smart-e29f9465-31ad-4b1c-8ec3-b40ee473550e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946454716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2946454716
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.646614376
Short name T200
Test name
Test status
Simulation time 494598583242 ps
CPU time 294.13 seconds
Started Jan 14 01:34:02 PM PST 24
Finished Jan 14 01:38:57 PM PST 24
Peak memory 200944 kb
Host smart-3e57471d-92ec-41d2-9dd5-0321e5ea3e94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646614376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.646614376
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3326953474
Short name T654
Test name
Test status
Simulation time 159564609361 ps
CPU time 89.16 seconds
Started Jan 14 01:34:00 PM PST 24
Finished Jan 14 01:35:29 PM PST 24
Peak memory 200888 kb
Host smart-f7e17571-ab35-4f30-93ba-11a1a8186294
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326953474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3326953474
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2726974262
Short name T856
Test name
Test status
Simulation time 106439236223 ps
CPU time 466.26 seconds
Started Jan 14 01:34:04 PM PST 24
Finished Jan 14 01:41:51 PM PST 24
Peak memory 201340 kb
Host smart-e27612a4-8a41-4662-b38b-df02b1dda20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726974262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2726974262
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3874230261
Short name T615
Test name
Test status
Simulation time 24962311567 ps
CPU time 31.1 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:34:36 PM PST 24
Peak memory 200704 kb
Host smart-871a7fe0-fd9f-49d0-8bf6-a6c69dad3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874230261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3874230261
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3802814633
Short name T669
Test name
Test status
Simulation time 5288322429 ps
CPU time 13.53 seconds
Started Jan 14 01:34:02 PM PST 24
Finished Jan 14 01:34:16 PM PST 24
Peak memory 200736 kb
Host smart-1556d97b-6992-4c3e-b231-d0a9c5745624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802814633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3802814633
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2457763376
Short name T508
Test name
Test status
Simulation time 5902650708 ps
CPU time 15.8 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:34:13 PM PST 24
Peak memory 200652 kb
Host smart-96cd183d-022b-42ba-9bb1-9369eda291e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457763376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2457763376
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.655563275
Short name T425
Test name
Test status
Simulation time 48848542729 ps
CPU time 112.17 seconds
Started Jan 14 01:33:59 PM PST 24
Finished Jan 14 01:35:52 PM PST 24
Peak memory 200740 kb
Host smart-08573a6a-b664-44f1-abe0-6afc67f0cce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655563275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
655563275
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.373469984
Short name T277
Test name
Test status
Simulation time 120653581837 ps
CPU time 168.47 seconds
Started Jan 14 01:34:02 PM PST 24
Finished Jan 14 01:36:51 PM PST 24
Peak memory 209540 kb
Host smart-317a068c-6e01-4f43-8ad3-a1b605677d53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373469984 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.373469984
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.212882160
Short name T704
Test name
Test status
Simulation time 393218677 ps
CPU time 1.49 seconds
Started Jan 14 01:34:05 PM PST 24
Finished Jan 14 01:34:07 PM PST 24
Peak memory 200672 kb
Host smart-d2720694-a331-42d8-bb4a-8d0aa61902f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212882160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.212882160
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.572739021
Short name T134
Test name
Test status
Simulation time 485947849008 ps
CPU time 710.35 seconds
Started Jan 14 01:34:07 PM PST 24
Finished Jan 14 01:45:58 PM PST 24
Peak memory 200836 kb
Host smart-545dc114-889d-492a-aae9-dd81fb3c515a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572739021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.572739021
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.508800509
Short name T849
Test name
Test status
Simulation time 323997678271 ps
CPU time 746.08 seconds
Started Jan 14 01:34:02 PM PST 24
Finished Jan 14 01:46:29 PM PST 24
Peak memory 200920 kb
Host smart-d9601ff9-3c08-46cc-ba6d-e3f301f11604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508800509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.508800509
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3711379538
Short name T581
Test name
Test status
Simulation time 329792950417 ps
CPU time 623.53 seconds
Started Jan 14 01:34:01 PM PST 24
Finished Jan 14 01:44:25 PM PST 24
Peak memory 201004 kb
Host smart-91821a0c-c3ed-434d-90a3-4f96bd214ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711379538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3711379538
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2140136110
Short name T860
Test name
Test status
Simulation time 500605719109 ps
CPU time 295.31 seconds
Started Jan 14 01:34:04 PM PST 24
Finished Jan 14 01:39:00 PM PST 24
Peak memory 200840 kb
Host smart-442fed1d-795a-46a3-b487-23dc063f592e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140136110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2140136110
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.938077788
Short name T199
Test name
Test status
Simulation time 321568642137 ps
CPU time 193.76 seconds
Started Jan 14 01:34:09 PM PST 24
Finished Jan 14 01:37:27 PM PST 24
Peak memory 200868 kb
Host smart-a578e97a-7734-42fa-9460-a0c92b195903
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938077788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.938077788
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1302387726
Short name T594
Test name
Test status
Simulation time 327606209711 ps
CPU time 86.83 seconds
Started Jan 14 01:34:05 PM PST 24
Finished Jan 14 01:35:33 PM PST 24
Peak memory 200928 kb
Host smart-a7749f57-7cd6-4428-9300-bb387a4079c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302387726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1302387726
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4088434147
Short name T361
Test name
Test status
Simulation time 121973563229 ps
CPU time 388.51 seconds
Started Jan 14 01:34:06 PM PST 24
Finished Jan 14 01:40:36 PM PST 24
Peak memory 201212 kb
Host smart-5721d239-5930-4d16-8eac-020741d653f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088434147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4088434147
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2215376552
Short name T725
Test name
Test status
Simulation time 28017863779 ps
CPU time 7.17 seconds
Started Jan 14 01:34:05 PM PST 24
Finished Jan 14 01:34:13 PM PST 24
Peak memory 200732 kb
Host smart-7f510858-2b41-469c-a6c6-5481ab75569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215376552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2215376552
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3676873414
Short name T714
Test name
Test status
Simulation time 5029669635 ps
CPU time 12.79 seconds
Started Jan 14 01:34:09 PM PST 24
Finished Jan 14 01:34:26 PM PST 24
Peak memory 200692 kb
Host smart-fd664593-acf7-4a31-bc0f-b6fb53dfbd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676873414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3676873414
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.363085212
Short name T551
Test name
Test status
Simulation time 6105557424 ps
CPU time 4 seconds
Started Jan 14 01:34:05 PM PST 24
Finished Jan 14 01:34:10 PM PST 24
Peak memory 200692 kb
Host smart-edc77cab-e069-4dd2-b5cb-756fe8a83950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363085212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.363085212
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1150330482
Short name T703
Test name
Test status
Simulation time 220119471162 ps
CPU time 182.99 seconds
Started Jan 14 01:36:36 PM PST 24
Finished Jan 14 01:39:47 PM PST 24
Peak memory 209692 kb
Host smart-602d9aa8-5c44-47a0-b74f-8d4fed227166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150330482 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1150330482
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1010546150
Short name T423
Test name
Test status
Simulation time 485093463 ps
CPU time 0.87 seconds
Started Jan 14 01:34:11 PM PST 24
Finished Jan 14 01:34:15 PM PST 24
Peak memory 200676 kb
Host smart-f50c13f0-f964-43ee-9b85-bd367d835b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010546150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1010546150
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.4024543974
Short name T325
Test name
Test status
Simulation time 488126633071 ps
CPU time 892.88 seconds
Started Jan 14 01:34:10 PM PST 24
Finished Jan 14 01:49:07 PM PST 24
Peak memory 200832 kb
Host smart-6c64991a-c38b-410a-82c5-dce75bc2ce63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024543974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.4024543974
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1791311261
Short name T747
Test name
Test status
Simulation time 162285772612 ps
CPU time 183.96 seconds
Started Jan 14 01:34:08 PM PST 24
Finished Jan 14 01:37:18 PM PST 24
Peak memory 200956 kb
Host smart-3e41d85a-779e-4808-9f7d-0f22f7086ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791311261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1791311261
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1895535955
Short name T626
Test name
Test status
Simulation time 159676941628 ps
CPU time 342.24 seconds
Started Jan 14 01:34:05 PM PST 24
Finished Jan 14 01:39:48 PM PST 24
Peak memory 200896 kb
Host smart-d119f7b9-3fde-436f-9d1c-584f0c61ffcc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895535955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1895535955
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3789740329
Short name T156
Test name
Test status
Simulation time 157820472359 ps
CPU time 92.5 seconds
Started Jan 14 01:34:12 PM PST 24
Finished Jan 14 01:35:47 PM PST 24
Peak memory 200896 kb
Host smart-74247cf5-68b2-45fc-aa76-222020780e93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789740329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3789740329
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3741178303
Short name T737
Test name
Test status
Simulation time 329336482112 ps
CPU time 215.06 seconds
Started Jan 14 01:34:07 PM PST 24
Finished Jan 14 01:37:46 PM PST 24
Peak memory 201004 kb
Host smart-3d37cec3-434c-48ec-83d1-7c41a533848a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741178303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3741178303
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.118243443
Short name T505
Test name
Test status
Simulation time 332738658417 ps
CPU time 391.84 seconds
Started Jan 14 01:34:09 PM PST 24
Finished Jan 14 01:40:45 PM PST 24
Peak memory 200948 kb
Host smart-016279c6-ae4f-49dc-b884-1cfbb14c87ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118243443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.118243443
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3676220035
Short name T865
Test name
Test status
Simulation time 26012206488 ps
CPU time 13.07 seconds
Started Jan 14 01:34:10 PM PST 24
Finished Jan 14 01:34:27 PM PST 24
Peak memory 200756 kb
Host smart-2df0a70f-f509-46ba-a886-855f3a9242f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676220035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3676220035
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2190528641
Short name T145
Test name
Test status
Simulation time 3585807431 ps
CPU time 5.68 seconds
Started Jan 14 01:34:07 PM PST 24
Finished Jan 14 01:34:13 PM PST 24
Peak memory 200756 kb
Host smart-9574c462-ec2f-4a14-8711-d70b2c89a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190528641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2190528641
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1143170569
Short name T434
Test name
Test status
Simulation time 5460755975 ps
CPU time 3.8 seconds
Started Jan 14 01:34:05 PM PST 24
Finished Jan 14 01:34:10 PM PST 24
Peak memory 200704 kb
Host smart-808c1e6e-7fc4-46c3-8608-6db2b40619e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143170569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1143170569
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2067641810
Short name T254
Test name
Test status
Simulation time 516727961369 ps
CPU time 815.99 seconds
Started Jan 14 01:34:08 PM PST 24
Finished Jan 14 01:47:50 PM PST 24
Peak memory 200932 kb
Host smart-fb7be350-a3d9-473f-8fe7-4f4bdcb8fbf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067641810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2067641810
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2859827230
Short name T498
Test name
Test status
Simulation time 537701750 ps
CPU time 0.71 seconds
Started Jan 14 01:34:11 PM PST 24
Finished Jan 14 01:34:15 PM PST 24
Peak memory 200676 kb
Host smart-5ad6699c-94e1-48f8-8fd8-7e35949306e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859827230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2859827230
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3924250183
Short name T187
Test name
Test status
Simulation time 352701669140 ps
CPU time 56.52 seconds
Started Jan 14 01:34:07 PM PST 24
Finished Jan 14 01:35:09 PM PST 24
Peak memory 200708 kb
Host smart-e2742103-74ad-47ed-aecd-a2280a1e66fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924250183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3924250183
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1407314008
Short name T579
Test name
Test status
Simulation time 165063355555 ps
CPU time 359.5 seconds
Started Jan 14 01:34:10 PM PST 24
Finished Jan 14 01:40:13 PM PST 24
Peak memory 200888 kb
Host smart-d3a7948b-d0fc-4a23-adc0-f970de24e244
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407314008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1407314008
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3478847958
Short name T524
Test name
Test status
Simulation time 331753742576 ps
CPU time 360.58 seconds
Started Jan 14 01:34:08 PM PST 24
Finished Jan 14 01:40:14 PM PST 24
Peak memory 200964 kb
Host smart-119dadcd-9027-4d76-974f-8c79cea460b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478847958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3478847958
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.290613752
Short name T749
Test name
Test status
Simulation time 164824979179 ps
CPU time 91.22 seconds
Started Jan 14 01:34:12 PM PST 24
Finished Jan 14 01:35:46 PM PST 24
Peak memory 200904 kb
Host smart-9b99521b-7c1b-49f6-a59b-4d92997a7f4b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=290613752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.290613752
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2199766500
Short name T645
Test name
Test status
Simulation time 502353875438 ps
CPU time 1171.27 seconds
Started Jan 14 01:34:07 PM PST 24
Finished Jan 14 01:53:39 PM PST 24
Peak memory 200736 kb
Host smart-7ebf68af-236a-48af-b2aa-9297e0fbcf70
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199766500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2199766500
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3148850685
Short name T822
Test name
Test status
Simulation time 136804572329 ps
CPU time 414.54 seconds
Started Jan 14 01:34:10 PM PST 24
Finished Jan 14 01:41:08 PM PST 24
Peak memory 201312 kb
Host smart-53d86ebb-c371-4c71-bb82-9a13b3681bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148850685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3148850685
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1984345806
Short name T490
Test name
Test status
Simulation time 42544451319 ps
CPU time 100.11 seconds
Started Jan 14 01:34:08 PM PST 24
Finished Jan 14 01:35:54 PM PST 24
Peak memory 200724 kb
Host smart-8126d1c1-7869-4105-9755-665c97709786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984345806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1984345806
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2309980707
Short name T447
Test name
Test status
Simulation time 5104766295 ps
CPU time 7.44 seconds
Started Jan 14 01:34:12 PM PST 24
Finished Jan 14 01:34:21 PM PST 24
Peak memory 200760 kb
Host smart-ccf28f8d-acd9-4cb5-90cd-9c2ca81bcdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309980707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2309980707
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3444945510
Short name T576
Test name
Test status
Simulation time 5654972147 ps
CPU time 2.51 seconds
Started Jan 14 01:34:08 PM PST 24
Finished Jan 14 01:34:15 PM PST 24
Peak memory 200696 kb
Host smart-2dd7e0b0-5716-4e08-8e3d-78ca18b0264d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444945510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3444945510
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.73880869
Short name T582
Test name
Test status
Simulation time 333724908444 ps
CPU time 770.07 seconds
Started Jan 14 01:34:21 PM PST 24
Finished Jan 14 01:47:13 PM PST 24
Peak memory 200952 kb
Host smart-bf084b14-0a0b-465e-889b-fc8d34184862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73880869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.73880869
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.627977262
Short name T675
Test name
Test status
Simulation time 432226810990 ps
CPU time 437.36 seconds
Started Jan 14 01:34:04 PM PST 24
Finished Jan 14 01:41:23 PM PST 24
Peak memory 209616 kb
Host smart-9caca5ce-ec8d-4d67-a81c-1122f0b9775e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627977262 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.627977262
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3330402045
Short name T592
Test name
Test status
Simulation time 500537429 ps
CPU time 0.91 seconds
Started Jan 14 01:34:19 PM PST 24
Finished Jan 14 01:34:21 PM PST 24
Peak memory 200648 kb
Host smart-d28bfb3b-d74a-43cd-bed9-2fc444241f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330402045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3330402045
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3523963004
Short name T484
Test name
Test status
Simulation time 488048497705 ps
CPU time 1156 seconds
Started Jan 14 01:34:16 PM PST 24
Finished Jan 14 01:53:35 PM PST 24
Peak memory 200792 kb
Host smart-ea28cdf6-6d87-4e60-a19c-061c205333c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523963004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3523963004
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.543580923
Short name T261
Test name
Test status
Simulation time 161659703528 ps
CPU time 181.75 seconds
Started Jan 14 01:34:08 PM PST 24
Finished Jan 14 01:37:14 PM PST 24
Peak memory 200892 kb
Host smart-20e7e7e5-cdb1-4cc8-83fa-7f8686c509de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543580923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.543580923
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3582061102
Short name T584
Test name
Test status
Simulation time 163265801426 ps
CPU time 61.43 seconds
Started Jan 14 01:34:12 PM PST 24
Finished Jan 14 01:35:16 PM PST 24
Peak memory 200868 kb
Host smart-5f5d817b-e5f7-4704-b88d-1c05cd2ba02c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582061102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3582061102
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.4230052562
Short name T602
Test name
Test status
Simulation time 329608685186 ps
CPU time 730.89 seconds
Started Jan 14 01:34:13 PM PST 24
Finished Jan 14 01:46:28 PM PST 24
Peak memory 200872 kb
Host smart-3bd43ab1-dc9a-42da-a52b-2ebf7aed6e8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230052562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.4230052562
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4281636278
Short name T606
Test name
Test status
Simulation time 327606674902 ps
CPU time 805.46 seconds
Started Jan 14 01:34:19 PM PST 24
Finished Jan 14 01:47:46 PM PST 24
Peak memory 200896 kb
Host smart-6eb63d2b-eaee-4c03-b027-03d44572aeaa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281636278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4281636278
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3473296070
Short name T219
Test name
Test status
Simulation time 105996037913 ps
CPU time 589.77 seconds
Started Jan 14 01:34:19 PM PST 24
Finished Jan 14 01:44:10 PM PST 24
Peak memory 201460 kb
Host smart-80328467-4a9a-4990-aa0d-ad9a3347b17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473296070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3473296070
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3796525653
Short name T42
Test name
Test status
Simulation time 35100122172 ps
CPU time 73.51 seconds
Started Jan 14 01:34:18 PM PST 24
Finished Jan 14 01:35:32 PM PST 24
Peak memory 200724 kb
Host smart-54174893-b789-4b7a-8c75-6f57ba7ba839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796525653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3796525653
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3140492033
Short name T53
Test name
Test status
Simulation time 4505816557 ps
CPU time 7.07 seconds
Started Jan 14 01:34:20 PM PST 24
Finished Jan 14 01:34:28 PM PST 24
Peak memory 200700 kb
Host smart-27a30416-c3f4-4910-8a80-33e1421cd556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140492033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3140492033
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3919652715
Short name T446
Test name
Test status
Simulation time 5877324247 ps
CPU time 1.75 seconds
Started Jan 14 01:34:13 PM PST 24
Finished Jan 14 01:34:20 PM PST 24
Peak memory 200700 kb
Host smart-eee62d4a-974d-4fb6-a137-251b63e78e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919652715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3919652715
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.375166612
Short name T799
Test name
Test status
Simulation time 225831726259 ps
CPU time 191.19 seconds
Started Jan 14 01:34:21 PM PST 24
Finished Jan 14 01:37:33 PM PST 24
Peak memory 209076 kb
Host smart-96fe569c-f14e-4650-b838-e3ef42469cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375166612 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.375166612
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1508775390
Short name T495
Test name
Test status
Simulation time 364537974 ps
CPU time 0.8 seconds
Started Jan 14 01:34:30 PM PST 24
Finished Jan 14 01:34:33 PM PST 24
Peak memory 200648 kb
Host smart-88c0b3d3-e977-4b21-aaf7-1c03624da863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508775390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1508775390
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2794794207
Short name T256
Test name
Test status
Simulation time 160593042865 ps
CPU time 104.02 seconds
Started Jan 14 01:34:28 PM PST 24
Finished Jan 14 01:36:14 PM PST 24
Peak memory 200956 kb
Host smart-84f0af25-1f0b-4e33-ac55-747c058e0ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794794207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2794794207
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1518928928
Short name T262
Test name
Test status
Simulation time 162329538343 ps
CPU time 25.84 seconds
Started Jan 14 01:34:20 PM PST 24
Finished Jan 14 01:34:47 PM PST 24
Peak memory 200956 kb
Host smart-6dae38a6-baf1-49ed-b2e2-709eb5c4949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518928928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1518928928
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1876757228
Short name T833
Test name
Test status
Simulation time 497500254559 ps
CPU time 865.13 seconds
Started Jan 14 01:34:23 PM PST 24
Finished Jan 14 01:48:53 PM PST 24
Peak memory 200956 kb
Host smart-b58ac825-9c6e-4a02-90ab-6b2dc527a41d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876757228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1876757228
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1288688695
Short name T529
Test name
Test status
Simulation time 330010881067 ps
CPU time 177.91 seconds
Started Jan 14 01:34:28 PM PST 24
Finished Jan 14 01:37:28 PM PST 24
Peak memory 200836 kb
Host smart-e8b21405-93eb-47b0-82ef-3e81bcbcc6d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288688695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1288688695
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2911597176
Short name T306
Test name
Test status
Simulation time 170428395722 ps
CPU time 203.89 seconds
Started Jan 14 01:34:28 PM PST 24
Finished Jan 14 01:37:54 PM PST 24
Peak memory 200860 kb
Host smart-22382ed6-c666-4acb-b429-2b41da942c95
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911597176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2911597176
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1097458405
Short name T845
Test name
Test status
Simulation time 338770575551 ps
CPU time 73.33 seconds
Started Jan 14 01:34:23 PM PST 24
Finished Jan 14 01:35:41 PM PST 24
Peak memory 200896 kb
Host smart-b9affb80-3871-4e62-b696-c775b39ab2e7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097458405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1097458405
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.4230103945
Short name T826
Test name
Test status
Simulation time 85630559252 ps
CPU time 324.74 seconds
Started Jan 14 01:34:27 PM PST 24
Finished Jan 14 01:39:54 PM PST 24
Peak memory 201460 kb
Host smart-68a75827-9feb-43dc-95ed-2cb19f7131a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230103945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.4230103945
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2668689397
Short name T670
Test name
Test status
Simulation time 31243762033 ps
CPU time 6.31 seconds
Started Jan 14 01:34:30 PM PST 24
Finished Jan 14 01:34:39 PM PST 24
Peak memory 200640 kb
Host smart-c3b51118-874f-4549-b305-4a4f6ea6b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668689397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2668689397
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.584751675
Short name T618
Test name
Test status
Simulation time 2758122943 ps
CPU time 6.75 seconds
Started Jan 14 01:34:22 PM PST 24
Finished Jan 14 01:34:30 PM PST 24
Peak memory 200772 kb
Host smart-f1f36876-3c53-46e0-92d0-0dc0db1451de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584751675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.584751675
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.697844779
Short name T460
Test name
Test status
Simulation time 5684875865 ps
CPU time 3.87 seconds
Started Jan 14 01:34:18 PM PST 24
Finished Jan 14 01:34:23 PM PST 24
Peak memory 200712 kb
Host smart-71eb165a-7066-427f-8788-0480e4568163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697844779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.697844779
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1093981599
Short name T103
Test name
Test status
Simulation time 49546510125 ps
CPU time 93.12 seconds
Started Jan 14 01:34:32 PM PST 24
Finished Jan 14 01:36:06 PM PST 24
Peak memory 200768 kb
Host smart-53aad6ba-c593-45d4-8b33-96116ef567e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093981599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1093981599
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2284647418
Short name T763
Test name
Test status
Simulation time 33468389727 ps
CPU time 23.59 seconds
Started Jan 14 01:34:30 PM PST 24
Finished Jan 14 01:34:56 PM PST 24
Peak memory 201008 kb
Host smart-b0aae0bd-cedb-41cd-8750-5cbea302c891
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284647418 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2284647418
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2580236141
Short name T421
Test name
Test status
Simulation time 472650678 ps
CPU time 0.86 seconds
Started Jan 14 01:34:21 PM PST 24
Finished Jan 14 01:34:23 PM PST 24
Peak memory 200420 kb
Host smart-3e82496f-3b23-4876-97ff-028695021792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580236141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2580236141
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3664179252
Short name T148
Test name
Test status
Simulation time 322508534052 ps
CPU time 106.81 seconds
Started Jan 14 01:34:25 PM PST 24
Finished Jan 14 01:36:16 PM PST 24
Peak memory 200888 kb
Host smart-e5af3234-c459-449f-b3b6-8f6aad6c9aee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664179252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3664179252
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2364380126
Short name T188
Test name
Test status
Simulation time 500145820519 ps
CPU time 228.1 seconds
Started Jan 14 01:34:32 PM PST 24
Finished Jan 14 01:38:21 PM PST 24
Peak memory 200988 kb
Host smart-6b889a09-a01d-42cc-a8d0-1aa9594b04cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364380126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2364380126
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.557085424
Short name T620
Test name
Test status
Simulation time 329926213046 ps
CPU time 754.49 seconds
Started Jan 14 01:34:27 PM PST 24
Finished Jan 14 01:47:04 PM PST 24
Peak memory 200952 kb
Host smart-40656a9e-1299-4419-bf32-d33dbd280aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557085424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.557085424
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.695518609
Short name T512
Test name
Test status
Simulation time 497422303163 ps
CPU time 556.43 seconds
Started Jan 14 01:34:31 PM PST 24
Finished Jan 14 01:43:49 PM PST 24
Peak memory 200872 kb
Host smart-bb37db1b-98c6-40a3-97e1-c7f1b1ebccb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=695518609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.695518609
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1189451595
Short name T802
Test name
Test status
Simulation time 330818507532 ps
CPU time 366.36 seconds
Started Jan 14 01:34:22 PM PST 24
Finished Jan 14 01:40:29 PM PST 24
Peak memory 200952 kb
Host smart-791e01fc-76e4-4cb2-a9ea-32f29b2c7a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189451595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1189451595
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2530643482
Short name T682
Test name
Test status
Simulation time 490974959208 ps
CPU time 176.89 seconds
Started Jan 14 01:34:27 PM PST 24
Finished Jan 14 01:37:26 PM PST 24
Peak memory 200948 kb
Host smart-7a42b133-8159-4d28-b238-a01ff56aaf83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530643482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2530643482
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2790172930
Short name T491
Test name
Test status
Simulation time 167509220107 ps
CPU time 54.93 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:35:32 PM PST 24
Peak memory 200972 kb
Host smart-ba753f4c-ad4f-4906-b302-80920cb34dfe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790172930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2790172930
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3991900916
Short name T545
Test name
Test status
Simulation time 337467593376 ps
CPU time 715.68 seconds
Started Jan 14 01:34:30 PM PST 24
Finished Jan 14 01:46:28 PM PST 24
Peak memory 200916 kb
Host smart-13594dc8-be6e-49a0-81fd-a00b69b8b084
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991900916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3991900916
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2882757705
Short name T738
Test name
Test status
Simulation time 134673687842 ps
CPU time 555.22 seconds
Started Jan 14 01:34:26 PM PST 24
Finished Jan 14 01:43:44 PM PST 24
Peak memory 201396 kb
Host smart-9f362ba7-29d5-442c-896e-90ff736e7ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882757705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2882757705
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2658300438
Short name T528
Test name
Test status
Simulation time 36865066268 ps
CPU time 85.76 seconds
Started Jan 14 01:34:29 PM PST 24
Finished Jan 14 01:35:58 PM PST 24
Peak memory 200720 kb
Host smart-b52a5f8b-6478-40c3-b335-ef43a9269eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658300438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2658300438
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2394414964
Short name T552
Test name
Test status
Simulation time 2976732364 ps
CPU time 2.69 seconds
Started Jan 14 01:34:36 PM PST 24
Finished Jan 14 01:34:40 PM PST 24
Peak memory 200760 kb
Host smart-292f19f5-8710-4a48-8abf-92d1d2f92022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394414964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2394414964
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3791130707
Short name T526
Test name
Test status
Simulation time 5821678876 ps
CPU time 12.85 seconds
Started Jan 14 01:34:30 PM PST 24
Finished Jan 14 01:34:45 PM PST 24
Peak memory 200704 kb
Host smart-2861579e-ad67-4dfc-8305-3bf7f5a1ce93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791130707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3791130707
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.687616587
Short name T336
Test name
Test status
Simulation time 72030015128 ps
CPU time 271.03 seconds
Started Jan 14 01:34:29 PM PST 24
Finished Jan 14 01:39:03 PM PST 24
Peak memory 209560 kb
Host smart-62d5a370-33d8-4df6-afe9-b0577f095e36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687616587 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.687616587
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3972428030
Short name T668
Test name
Test status
Simulation time 506843074 ps
CPU time 1.87 seconds
Started Jan 14 01:34:32 PM PST 24
Finished Jan 14 01:34:35 PM PST 24
Peak memory 200736 kb
Host smart-0ff463a1-627b-48ed-b82c-a79f4a7f694f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972428030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3972428030
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3395733962
Short name T183
Test name
Test status
Simulation time 165269321160 ps
CPU time 57.22 seconds
Started Jan 14 01:34:45 PM PST 24
Finished Jan 14 01:35:44 PM PST 24
Peak memory 200968 kb
Host smart-657d74e9-c027-4ce3-b4c3-a9c114f91511
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395733962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3395733962
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.294524591
Short name T316
Test name
Test status
Simulation time 334113250593 ps
CPU time 199.62 seconds
Started Jan 14 01:34:34 PM PST 24
Finished Jan 14 01:37:57 PM PST 24
Peak memory 200992 kb
Host smart-e6addf63-7f87-4220-9dca-b8f0f3966d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294524591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.294524591
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4094847437
Short name T295
Test name
Test status
Simulation time 490791626575 ps
CPU time 1175.32 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:54:13 PM PST 24
Peak memory 200948 kb
Host smart-fd6c02f2-1028-4aaf-bbcb-59240b3a5892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094847437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.4094847437
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.893114809
Short name T851
Test name
Test status
Simulation time 497742999316 ps
CPU time 207.61 seconds
Started Jan 14 01:34:34 PM PST 24
Finished Jan 14 01:38:04 PM PST 24
Peak memory 200860 kb
Host smart-a8bd8841-fdd4-4c38-ba50-5e1f7f89a681
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=893114809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.893114809
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2406576138
Short name T113
Test name
Test status
Simulation time 322559891692 ps
CPU time 732.09 seconds
Started Jan 14 01:34:34 PM PST 24
Finished Jan 14 01:46:49 PM PST 24
Peak memory 200916 kb
Host smart-d34a0f63-7c0c-4281-95c3-d0941f72a76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406576138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2406576138
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3401454169
Short name T559
Test name
Test status
Simulation time 328784965646 ps
CPU time 770.45 seconds
Started Jan 14 01:34:31 PM PST 24
Finished Jan 14 01:47:23 PM PST 24
Peak memory 200844 kb
Host smart-b041c699-1922-4fa5-aa7f-9256b58d99d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401454169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3401454169
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.71332643
Short name T671
Test name
Test status
Simulation time 167472741584 ps
CPU time 402.86 seconds
Started Jan 14 01:34:46 PM PST 24
Finished Jan 14 01:41:29 PM PST 24
Peak memory 200872 kb
Host smart-cb248618-ed3f-4bfa-adb0-4d6d8cef7e13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71332643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.a
dc_ctrl_filters_wakeup_fixed.71332643
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.547028993
Short name T208
Test name
Test status
Simulation time 112007394920 ps
CPU time 359.11 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:40:36 PM PST 24
Peak memory 201332 kb
Host smart-8db1e496-d15d-4601-acb1-ac0d83a72894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547028993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.547028993
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1027570735
Short name T450
Test name
Test status
Simulation time 39248513853 ps
CPU time 86.67 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:36:04 PM PST 24
Peak memory 200692 kb
Host smart-bcfab760-4138-46d9-a7af-179e2652862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027570735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1027570735
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3498539032
Short name T438
Test name
Test status
Simulation time 4500088493 ps
CPU time 6.13 seconds
Started Jan 14 01:34:34 PM PST 24
Finished Jan 14 01:34:43 PM PST 24
Peak memory 200728 kb
Host smart-aae3537e-a408-484b-b643-20f7301acb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498539032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3498539032
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1113644268
Short name T504
Test name
Test status
Simulation time 5664034272 ps
CPU time 13.07 seconds
Started Jan 14 01:34:33 PM PST 24
Finished Jan 14 01:34:48 PM PST 24
Peak memory 200724 kb
Host smart-0874fca9-b5f3-4682-a50c-8903aab7464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113644268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1113644268
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.559232162
Short name T211
Test name
Test status
Simulation time 115653214348 ps
CPU time 599.09 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:44:36 PM PST 24
Peak memory 209696 kb
Host smart-61f9e9ca-d90f-4318-a230-d4659f008fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559232162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
559232162
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1214215563
Short name T318
Test name
Test status
Simulation time 208439464314 ps
CPU time 138.14 seconds
Started Jan 14 01:34:34 PM PST 24
Finished Jan 14 01:36:54 PM PST 24
Peak memory 209556 kb
Host smart-54f96e46-4273-4bf2-a0ab-c0474b208393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214215563 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1214215563
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2071197031
Short name T532
Test name
Test status
Simulation time 496676152 ps
CPU time 1.8 seconds
Started Jan 14 01:34:37 PM PST 24
Finished Jan 14 01:34:44 PM PST 24
Peak memory 200648 kb
Host smart-bb9389d5-3dd0-4efa-b916-02e3f076a305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071197031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2071197031
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2939864030
Short name T140
Test name
Test status
Simulation time 493453714922 ps
CPU time 277.41 seconds
Started Jan 14 01:34:33 PM PST 24
Finished Jan 14 01:39:12 PM PST 24
Peak memory 200896 kb
Host smart-d0b4fc64-470b-4274-91fa-5ccbfcb64dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939864030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2939864030
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1280823881
Short name T523
Test name
Test status
Simulation time 327598951945 ps
CPU time 364.9 seconds
Started Jan 14 01:34:34 PM PST 24
Finished Jan 14 01:40:41 PM PST 24
Peak memory 200856 kb
Host smart-6440eadc-a1ce-4b14-81f5-7060e4ca697c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280823881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1280823881
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3755102220
Short name T625
Test name
Test status
Simulation time 331625258650 ps
CPU time 364.75 seconds
Started Jan 14 01:34:34 PM PST 24
Finished Jan 14 01:40:41 PM PST 24
Peak memory 200940 kb
Host smart-86716b1b-2dba-4c93-b022-699d3bf34f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755102220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3755102220
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.712264572
Short name T658
Test name
Test status
Simulation time 166662493706 ps
CPU time 90.26 seconds
Started Jan 14 01:34:36 PM PST 24
Finished Jan 14 01:36:08 PM PST 24
Peak memory 200784 kb
Host smart-062e2048-066f-4276-a2e9-1acae828f474
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=712264572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.712264572
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1050434971
Short name T575
Test name
Test status
Simulation time 159768950434 ps
CPU time 396.63 seconds
Started Jan 14 01:34:45 PM PST 24
Finished Jan 14 01:41:23 PM PST 24
Peak memory 200980 kb
Host smart-8019460e-e4c7-4c70-8145-d77889b4ad44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050434971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1050434971
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1921508530
Short name T502
Test name
Test status
Simulation time 499623266516 ps
CPU time 295.31 seconds
Started Jan 14 01:34:37 PM PST 24
Finished Jan 14 01:39:38 PM PST 24
Peak memory 200852 kb
Host smart-640fe08e-3114-47f2-b679-2cbc25ed0d7a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921508530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1921508530
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3568663959
Short name T366
Test name
Test status
Simulation time 79496000592 ps
CPU time 270.41 seconds
Started Jan 14 01:34:38 PM PST 24
Finished Jan 14 01:39:13 PM PST 24
Peak memory 201288 kb
Host smart-ba60aff4-6514-4f06-aee9-b9dc5dd62376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568663959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3568663959
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2940702843
Short name T820
Test name
Test status
Simulation time 32521847783 ps
CPU time 7.29 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:34:44 PM PST 24
Peak memory 200756 kb
Host smart-e2556cf5-ba23-4c37-9aa0-4941fdf8edf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940702843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2940702843
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3543866011
Short name T589
Test name
Test status
Simulation time 5420612683 ps
CPU time 13.12 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:34:50 PM PST 24
Peak memory 200676 kb
Host smart-4bb1d33f-3b4a-4ba2-991f-ab7deb2b7d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543866011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3543866011
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.878614146
Short name T696
Test name
Test status
Simulation time 5641752955 ps
CPU time 13.66 seconds
Started Jan 14 01:34:36 PM PST 24
Finished Jan 14 01:34:51 PM PST 24
Peak memory 200756 kb
Host smart-53eac764-45a5-4a21-ad0c-ab2c13b1ae36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878614146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.878614146
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3969546665
Short name T279
Test name
Test status
Simulation time 173168205531 ps
CPU time 27.64 seconds
Started Jan 14 01:34:46 PM PST 24
Finished Jan 14 01:35:14 PM PST 24
Peak memory 200932 kb
Host smart-59f2d021-d797-487a-b807-0077bdedfb10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969546665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3969546665
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1551281368
Short name T429
Test name
Test status
Simulation time 530596304 ps
CPU time 1.21 seconds
Started Jan 14 01:33:45 PM PST 24
Finished Jan 14 01:33:47 PM PST 24
Peak memory 200696 kb
Host smart-35ec91a7-9c7e-47c8-b2cc-90034460502d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551281368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1551281368
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.262861595
Short name T864
Test name
Test status
Simulation time 490815066355 ps
CPU time 1119.3 seconds
Started Jan 14 01:33:43 PM PST 24
Finished Jan 14 01:52:23 PM PST 24
Peak memory 200924 kb
Host smart-f0176d37-6e57-4fc5-8361-2165f652b0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262861595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.262861595
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.451256726
Short name T609
Test name
Test status
Simulation time 495838426784 ps
CPU time 546.25 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:42:51 PM PST 24
Peak memory 200876 kb
Host smart-3c2665e1-dc92-4bd3-b495-02bbbfff131f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=451256726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.451256726
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3549451864
Short name T221
Test name
Test status
Simulation time 491948097254 ps
CPU time 552.03 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:42:56 PM PST 24
Peak memory 200856 kb
Host smart-6881a27f-e049-4350-8df9-887ff4c59991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549451864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3549451864
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.439115375
Short name T634
Test name
Test status
Simulation time 503879447961 ps
CPU time 1149 seconds
Started Jan 14 01:33:43 PM PST 24
Finished Jan 14 01:52:53 PM PST 24
Peak memory 200940 kb
Host smart-049320d9-97c0-4c1e-99b2-8d9f259ae767
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=439115375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.439115375
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.685547988
Short name T268
Test name
Test status
Simulation time 327968934941 ps
CPU time 753.87 seconds
Started Jan 14 01:33:57 PM PST 24
Finished Jan 14 01:46:32 PM PST 24
Peak memory 200860 kb
Host smart-fe0c5715-d364-4ea6-a397-bf85d1f15d68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685547988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.685547988
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1972042459
Short name T599
Test name
Test status
Simulation time 160123405471 ps
CPU time 99.21 seconds
Started Jan 14 01:33:40 PM PST 24
Finished Jan 14 01:35:20 PM PST 24
Peak memory 200888 kb
Host smart-955a247a-215a-470e-969c-490aa46cc476
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972042459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1972042459
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3098194577
Short name T217
Test name
Test status
Simulation time 61158095077 ps
CPU time 251.37 seconds
Started Jan 14 01:33:41 PM PST 24
Finished Jan 14 01:37:53 PM PST 24
Peak memory 201396 kb
Host smart-2a244315-cf4d-494e-90a2-a00ca6515d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098194577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3098194577
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2110133534
Short name T439
Test name
Test status
Simulation time 22055190223 ps
CPU time 5.66 seconds
Started Jan 14 01:33:55 PM PST 24
Finished Jan 14 01:34:01 PM PST 24
Peak memory 200744 kb
Host smart-21346cf6-983e-4212-acf7-514a58b8fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110133534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2110133534
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1622445522
Short name T452
Test name
Test status
Simulation time 4574615156 ps
CPU time 3.5 seconds
Started Jan 14 01:33:51 PM PST 24
Finished Jan 14 01:33:55 PM PST 24
Peak memory 200688 kb
Host smart-b6452c21-3471-4085-bd9f-45a3bbf3661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622445522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1622445522
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4216595016
Short name T493
Test name
Test status
Simulation time 5575428023 ps
CPU time 2.64 seconds
Started Jan 14 01:33:36 PM PST 24
Finished Jan 14 01:33:39 PM PST 24
Peak memory 200756 kb
Host smart-fac2300b-37cb-4566-931e-7ba132c44dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216595016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4216595016
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.267523226
Short name T728
Test name
Test status
Simulation time 333549640733 ps
CPU time 116.66 seconds
Started Jan 14 01:33:46 PM PST 24
Finished Jan 14 01:35:43 PM PST 24
Peak memory 200872 kb
Host smart-129f1664-3850-4c3d-a161-d840fe7b0aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267523226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.267523226
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1563377291
Short name T347
Test name
Test status
Simulation time 140700860038 ps
CPU time 168.28 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:36:45 PM PST 24
Peak memory 209556 kb
Host smart-ee30b9fa-f080-4995-81d0-6c970e204e42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563377291 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1563377291
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1033988759
Short name T580
Test name
Test status
Simulation time 386197832 ps
CPU time 0.82 seconds
Started Jan 14 01:34:54 PM PST 24
Finished Jan 14 01:34:56 PM PST 24
Peak memory 200756 kb
Host smart-a9659c3c-6f17-48be-8989-b17f2e95ce08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033988759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1033988759
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3157605386
Short name T791
Test name
Test status
Simulation time 500020566533 ps
CPU time 1228.89 seconds
Started Jan 14 01:34:35 PM PST 24
Finished Jan 14 01:55:06 PM PST 24
Peak memory 200792 kb
Host smart-2bdbee5d-0c4f-401b-8d07-3b031a8a42c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157605386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3157605386
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.4149744180
Short name T560
Test name
Test status
Simulation time 167191162279 ps
CPU time 388.02 seconds
Started Jan 14 01:34:36 PM PST 24
Finished Jan 14 01:41:05 PM PST 24
Peak memory 200924 kb
Host smart-81e79a8c-90bf-4cd7-810a-f76072a315a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149744180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.4149744180
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1305243191
Short name T676
Test name
Test status
Simulation time 157314030076 ps
CPU time 332.88 seconds
Started Jan 14 01:34:39 PM PST 24
Finished Jan 14 01:40:16 PM PST 24
Peak memory 200836 kb
Host smart-fc384c2a-a516-4f80-8b36-a60fe53faf0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305243191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1305243191
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.835464435
Short name T689
Test name
Test status
Simulation time 486798472102 ps
CPU time 1111.17 seconds
Started Jan 14 01:34:53 PM PST 24
Finished Jan 14 01:53:25 PM PST 24
Peak memory 200832 kb
Host smart-aa06024c-c60e-4700-a87f-395a1a31566c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835464435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.835464435
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3134400904
Short name T362
Test name
Test status
Simulation time 103224140072 ps
CPU time 419.22 seconds
Started Jan 14 01:34:54 PM PST 24
Finished Jan 14 01:41:55 PM PST 24
Peak memory 201388 kb
Host smart-3d9e0e79-47f7-4d64-aa7c-e7670874fd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134400904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3134400904
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1243544703
Short name T442
Test name
Test status
Simulation time 42998766484 ps
CPU time 48 seconds
Started Jan 14 01:34:48 PM PST 24
Finished Jan 14 01:35:36 PM PST 24
Peak memory 200752 kb
Host smart-a931e9c9-3702-4ba8-90df-12849b4898ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243544703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1243544703
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1380230632
Short name T422
Test name
Test status
Simulation time 4573515341 ps
CPU time 11.75 seconds
Started Jan 14 01:34:53 PM PST 24
Finished Jan 14 01:35:06 PM PST 24
Peak memory 200740 kb
Host smart-f9c75fb4-c2f5-4b91-84a9-13dcf48e6fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380230632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1380230632
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.27724448
Short name T509
Test name
Test status
Simulation time 5789900348 ps
CPU time 15.21 seconds
Started Jan 14 01:34:37 PM PST 24
Finished Jan 14 01:34:57 PM PST 24
Peak memory 200748 kb
Host smart-f1bb48b8-e31d-41f6-ad2d-623c98646725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27724448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.27724448
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3792028540
Short name T855
Test name
Test status
Simulation time 323341213 ps
CPU time 0.82 seconds
Started Jan 14 01:35:08 PM PST 24
Finished Jan 14 01:35:10 PM PST 24
Peak memory 200664 kb
Host smart-7323af02-8e59-4918-ba1b-6462234f57cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792028540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3792028540
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1124782034
Short name T803
Test name
Test status
Simulation time 329743400944 ps
CPU time 79.23 seconds
Started Jan 14 01:35:01 PM PST 24
Finished Jan 14 01:36:21 PM PST 24
Peak memory 200916 kb
Host smart-d6c9fcc4-b995-499c-a669-394150deb607
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124782034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1124782034
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2047280880
Short name T280
Test name
Test status
Simulation time 324795767453 ps
CPU time 794.54 seconds
Started Jan 14 01:34:58 PM PST 24
Finished Jan 14 01:48:14 PM PST 24
Peak memory 200904 kb
Host smart-387b5781-4fe5-418e-8570-0b95f6f304bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047280880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2047280880
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1970362363
Short name T672
Test name
Test status
Simulation time 330852395675 ps
CPU time 209.14 seconds
Started Jan 14 01:34:54 PM PST 24
Finished Jan 14 01:38:24 PM PST 24
Peak memory 201016 kb
Host smart-82fba7fc-193f-4b03-a009-ec6d0b263972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970362363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1970362363
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.614154566
Short name T549
Test name
Test status
Simulation time 497886610955 ps
CPU time 1108.04 seconds
Started Jan 14 01:34:53 PM PST 24
Finished Jan 14 01:53:22 PM PST 24
Peak memory 200860 kb
Host smart-b2661d45-7b1c-4ee3-bcb3-627937a403ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=614154566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.614154566
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1565832380
Short name T186
Test name
Test status
Simulation time 325058950079 ps
CPU time 181.67 seconds
Started Jan 14 01:34:52 PM PST 24
Finished Jan 14 01:37:54 PM PST 24
Peak memory 200968 kb
Host smart-1dddac2c-5afb-413a-aaf3-22d65f36f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565832380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1565832380
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.4234797286
Short name T831
Test name
Test status
Simulation time 164401590182 ps
CPU time 84.92 seconds
Started Jan 14 01:34:51 PM PST 24
Finished Jan 14 01:36:16 PM PST 24
Peak memory 200892 kb
Host smart-cd0dcf1a-9948-4ba7-b00c-9aa7407810e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234797286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.4234797286
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.4049343361
Short name T628
Test name
Test status
Simulation time 164344950954 ps
CPU time 330.61 seconds
Started Jan 14 01:34:53 PM PST 24
Finished Jan 14 01:40:24 PM PST 24
Peak memory 200896 kb
Host smart-391098c5-0d5c-4cdd-a626-542c66d68ff9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049343361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.4049343361
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1732303138
Short name T706
Test name
Test status
Simulation time 329254044867 ps
CPU time 742.7 seconds
Started Jan 14 01:34:58 PM PST 24
Finished Jan 14 01:47:21 PM PST 24
Peak memory 200972 kb
Host smart-4d7b36f8-8a8f-4035-932e-75b4004328e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732303138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1732303138
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3071336782
Short name T169
Test name
Test status
Simulation time 44272742944 ps
CPU time 21.51 seconds
Started Jan 14 01:34:57 PM PST 24
Finished Jan 14 01:35:20 PM PST 24
Peak memory 200756 kb
Host smart-8e4d75a9-ac96-4067-acef-655cd20df9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071336782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3071336782
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1235345742
Short name T843
Test name
Test status
Simulation time 4613002941 ps
CPU time 3.54 seconds
Started Jan 14 01:34:54 PM PST 24
Finished Jan 14 01:34:58 PM PST 24
Peak memory 200736 kb
Host smart-5c2a5b39-f083-455b-a305-ba9ae82b2949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235345742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1235345742
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3271490550
Short name T550
Test name
Test status
Simulation time 5957091675 ps
CPU time 3.84 seconds
Started Jan 14 01:34:46 PM PST 24
Finished Jan 14 01:34:51 PM PST 24
Peak memory 200680 kb
Host smart-c0ff560f-62a2-4ce3-9c1d-fc1550a7d2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271490550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3271490550
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3466118190
Short name T631
Test name
Test status
Simulation time 42132932320 ps
CPU time 27.77 seconds
Started Jan 14 01:35:08 PM PST 24
Finished Jan 14 01:35:36 PM PST 24
Peak memory 200768 kb
Host smart-52558639-d2ad-49c6-b2ab-0775094290ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466118190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3466118190
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1550979127
Short name T197
Test name
Test status
Simulation time 194569019881 ps
CPU time 110.49 seconds
Started Jan 14 01:34:57 PM PST 24
Finished Jan 14 01:36:48 PM PST 24
Peak memory 209120 kb
Host smart-b00ded41-172b-4e0e-9a50-d9b15d5e94dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550979127 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1550979127
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3299957390
Short name T837
Test name
Test status
Simulation time 288611103 ps
CPU time 1.35 seconds
Started Jan 14 01:35:08 PM PST 24
Finished Jan 14 01:35:11 PM PST 24
Peak memory 200680 kb
Host smart-e8cbdd6f-1dcc-4e3d-964e-4b9547bfcc79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299957390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3299957390
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2962795632
Short name T356
Test name
Test status
Simulation time 336517026851 ps
CPU time 698.29 seconds
Started Jan 14 01:35:09 PM PST 24
Finished Jan 14 01:46:48 PM PST 24
Peak memory 200868 kb
Host smart-202ed23a-f993-4cb2-b1be-d62c2573a0ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962795632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2962795632
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2139003239
Short name T114
Test name
Test status
Simulation time 161595755927 ps
CPU time 186.64 seconds
Started Jan 14 01:35:08 PM PST 24
Finished Jan 14 01:38:15 PM PST 24
Peak memory 200900 kb
Host smart-b09152c5-1ad7-4ef0-82ff-18fa784c5b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139003239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2139003239
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.553509343
Short name T335
Test name
Test status
Simulation time 165379539901 ps
CPU time 194.87 seconds
Started Jan 14 01:35:07 PM PST 24
Finished Jan 14 01:38:23 PM PST 24
Peak memory 200856 kb
Host smart-d383d77e-cc83-4ed9-92e7-9ab34cc36336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553509343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.553509343
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2257599380
Short name T483
Test name
Test status
Simulation time 488586274756 ps
CPU time 1149.93 seconds
Started Jan 14 01:35:10 PM PST 24
Finished Jan 14 01:54:21 PM PST 24
Peak memory 200876 kb
Host smart-346774ba-b913-4a35-8ebe-61c3554c57c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257599380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2257599380
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1588302166
Short name T561
Test name
Test status
Simulation time 496127409334 ps
CPU time 1205.48 seconds
Started Jan 14 01:35:07 PM PST 24
Finished Jan 14 01:55:13 PM PST 24
Peak memory 200940 kb
Host smart-03d6b582-2316-4379-b12b-6f10cf94e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588302166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1588302166
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2937741514
Short name T455
Test name
Test status
Simulation time 332680270119 ps
CPU time 397.6 seconds
Started Jan 14 01:35:08 PM PST 24
Finished Jan 14 01:41:47 PM PST 24
Peak memory 200832 kb
Host smart-47ebb208-4060-4bc4-980a-16039186448b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937741514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2937741514
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1073666631
Short name T133
Test name
Test status
Simulation time 493552052715 ps
CPU time 1077.37 seconds
Started Jan 14 01:35:13 PM PST 24
Finished Jan 14 01:53:11 PM PST 24
Peak memory 200980 kb
Host smart-8cdde52f-fc2e-41a6-a9fe-592c7ef8f87d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073666631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1073666631
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1167232456
Short name T544
Test name
Test status
Simulation time 484239907122 ps
CPU time 1032.17 seconds
Started Jan 14 01:35:09 PM PST 24
Finished Jan 14 01:52:22 PM PST 24
Peak memory 200880 kb
Host smart-2ff9ceff-b67a-4bba-9d57-8836f8a57d6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167232456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1167232456
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3589420743
Short name T793
Test name
Test status
Simulation time 112942194343 ps
CPU time 612.91 seconds
Started Jan 14 01:35:08 PM PST 24
Finished Jan 14 01:45:22 PM PST 24
Peak memory 201328 kb
Host smart-90da3034-ae10-4831-b26b-7a653ba425bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589420743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3589420743
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2076852426
Short name T836
Test name
Test status
Simulation time 27462506981 ps
CPU time 65.58 seconds
Started Jan 14 01:35:10 PM PST 24
Finished Jan 14 01:36:17 PM PST 24
Peak memory 200740 kb
Host smart-c7aa2f65-9b14-44d7-b920-4bd36167787f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076852426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2076852426
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1991310733
Short name T106
Test name
Test status
Simulation time 5165651173 ps
CPU time 8.19 seconds
Started Jan 14 01:35:13 PM PST 24
Finished Jan 14 01:35:22 PM PST 24
Peak memory 200728 kb
Host smart-07ccc134-14f6-4ce7-964a-c13ec2643ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991310733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1991310733
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3694386107
Short name T563
Test name
Test status
Simulation time 5812275407 ps
CPU time 3.48 seconds
Started Jan 14 01:35:08 PM PST 24
Finished Jan 14 01:35:12 PM PST 24
Peak memory 200728 kb
Host smart-d455709a-ae5b-43aa-bde3-f8512f890397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694386107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3694386107
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1881765652
Short name T863
Test name
Test status
Simulation time 148840747573 ps
CPU time 43.43 seconds
Started Jan 14 01:35:07 PM PST 24
Finished Jan 14 01:35:52 PM PST 24
Peak memory 209236 kb
Host smart-0749a1f2-1bb8-4d18-ace1-2ee7be8835c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881765652 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1881765652
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1293694653
Short name T812
Test name
Test status
Simulation time 489407854 ps
CPU time 0.87 seconds
Started Jan 14 01:35:16 PM PST 24
Finished Jan 14 01:35:17 PM PST 24
Peak memory 200632 kb
Host smart-ac41a1ca-b356-4e62-bf59-1be980a4f9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293694653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1293694653
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2195204930
Short name T345
Test name
Test status
Simulation time 165124890537 ps
CPU time 21.32 seconds
Started Jan 14 01:35:12 PM PST 24
Finished Jan 14 01:35:34 PM PST 24
Peak memory 200892 kb
Host smart-1964c4fa-9494-4bf2-8061-5f7428df51c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195204930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2195204930
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2524792109
Short name T785
Test name
Test status
Simulation time 171506981301 ps
CPU time 212.54 seconds
Started Jan 14 01:35:20 PM PST 24
Finished Jan 14 01:38:53 PM PST 24
Peak memory 200884 kb
Host smart-ab93dfc9-6fce-43c6-b244-8688c938c472
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524792109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2524792109
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.74484641
Short name T324
Test name
Test status
Simulation time 329079961978 ps
CPU time 404.7 seconds
Started Jan 14 01:35:08 PM PST 24
Finished Jan 14 01:41:54 PM PST 24
Peak memory 200904 kb
Host smart-63a43ca5-1241-4f49-949f-597e5033ed90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74484641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.74484641
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.4122360889
Short name T684
Test name
Test status
Simulation time 330816962344 ps
CPU time 703.86 seconds
Started Jan 14 01:35:15 PM PST 24
Finished Jan 14 01:46:59 PM PST 24
Peak memory 200876 kb
Host smart-fc085ed1-d382-4e39-9c22-6c615863516a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122360889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.4122360889
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1077332967
Short name T265
Test name
Test status
Simulation time 503961714177 ps
CPU time 558.77 seconds
Started Jan 14 01:35:20 PM PST 24
Finished Jan 14 01:44:39 PM PST 24
Peak memory 200904 kb
Host smart-d37b89f5-9896-4fa6-99b5-f313e39d6446
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077332967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1077332967
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2368893648
Short name T847
Test name
Test status
Simulation time 495077509062 ps
CPU time 195.01 seconds
Started Jan 14 01:35:15 PM PST 24
Finished Jan 14 01:38:31 PM PST 24
Peak memory 200832 kb
Host smart-5e796d6a-ed55-4eab-8ad0-3cb562671d67
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368893648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2368893648
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2903502173
Short name T796
Test name
Test status
Simulation time 128094557882 ps
CPU time 648.56 seconds
Started Jan 14 01:35:13 PM PST 24
Finished Jan 14 01:46:02 PM PST 24
Peak memory 201380 kb
Host smart-29a968eb-57bc-4165-9080-8efc12bbe38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903502173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2903502173
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2652801433
Short name T556
Test name
Test status
Simulation time 42391249562 ps
CPU time 98.4 seconds
Started Jan 14 01:35:13 PM PST 24
Finished Jan 14 01:36:52 PM PST 24
Peak memory 200744 kb
Host smart-b93cb2ac-4ebc-4594-abb2-9df42b6df080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652801433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2652801433
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.758565143
Short name T527
Test name
Test status
Simulation time 3995206032 ps
CPU time 9.79 seconds
Started Jan 14 01:35:12 PM PST 24
Finished Jan 14 01:35:22 PM PST 24
Peak memory 200760 kb
Host smart-74e7130c-b2d2-4742-bb77-8d63c46cae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758565143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.758565143
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2286391710
Short name T752
Test name
Test status
Simulation time 5763630948 ps
CPU time 7.66 seconds
Started Jan 14 01:35:10 PM PST 24
Finished Jan 14 01:35:18 PM PST 24
Peak memory 200744 kb
Host smart-f1113a23-6a10-4864-8b79-0079dc28e5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286391710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2286391710
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.554536985
Short name T713
Test name
Test status
Simulation time 495275874496 ps
CPU time 327.11 seconds
Started Jan 14 01:35:20 PM PST 24
Finished Jan 14 01:40:48 PM PST 24
Peak memory 200900 kb
Host smart-19aa6575-3498-4445-84e6-db5d6a68b0d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554536985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
554536985
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1454486628
Short name T731
Test name
Test status
Simulation time 267221189226 ps
CPU time 179.86 seconds
Started Jan 14 01:35:15 PM PST 24
Finished Jan 14 01:38:15 PM PST 24
Peak memory 209588 kb
Host smart-abf7b4fe-9441-46cf-88ea-1ec099347623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454486628 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1454486628
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2523997616
Short name T554
Test name
Test status
Simulation time 414578356 ps
CPU time 0.82 seconds
Started Jan 14 01:35:33 PM PST 24
Finished Jan 14 01:35:35 PM PST 24
Peak memory 200644 kb
Host smart-1c1860f7-570f-4a78-b7a6-bbdfa71cfd54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523997616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2523997616
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2086198699
Short name T343
Test name
Test status
Simulation time 331845996648 ps
CPU time 378.96 seconds
Started Jan 14 01:35:20 PM PST 24
Finished Jan 14 01:41:40 PM PST 24
Peak memory 200944 kb
Host smart-8b2cd5af-b9a6-49df-b006-8f0f467c8e25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086198699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2086198699
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1478517054
Short name T124
Test name
Test status
Simulation time 320439040838 ps
CPU time 712.07 seconds
Started Jan 14 01:35:21 PM PST 24
Finished Jan 14 01:47:14 PM PST 24
Peak memory 201012 kb
Host smart-33fb8c21-6e1c-48e5-b1e3-3e2b9f414624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478517054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1478517054
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.355646461
Short name T158
Test name
Test status
Simulation time 160284056298 ps
CPU time 95.86 seconds
Started Jan 14 01:35:24 PM PST 24
Finished Jan 14 01:37:01 PM PST 24
Peak memory 200976 kb
Host smart-49916b6f-9c94-445a-b13e-f2efe94c3aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355646461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.355646461
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3209254532
Short name T756
Test name
Test status
Simulation time 167175391926 ps
CPU time 401.39 seconds
Started Jan 14 01:35:22 PM PST 24
Finished Jan 14 01:42:04 PM PST 24
Peak memory 200860 kb
Host smart-2e3e4cbd-36eb-4790-982b-f9080561ea73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209254532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3209254532
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.121545062
Short name T162
Test name
Test status
Simulation time 166551006157 ps
CPU time 96.72 seconds
Started Jan 14 01:35:22 PM PST 24
Finished Jan 14 01:37:00 PM PST 24
Peak memory 200904 kb
Host smart-3a5b5344-7a81-4c04-b008-e4a60ffe6ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121545062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.121545062
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3009230891
Short name T440
Test name
Test status
Simulation time 159095351860 ps
CPU time 200.81 seconds
Started Jan 14 01:35:20 PM PST 24
Finished Jan 14 01:38:41 PM PST 24
Peak memory 200828 kb
Host smart-fe9578e1-7153-42cd-a68d-fdbad9a663b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009230891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3009230891
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.121565726
Short name T287
Test name
Test status
Simulation time 331051660528 ps
CPU time 735.46 seconds
Started Jan 14 01:35:21 PM PST 24
Finished Jan 14 01:47:38 PM PST 24
Peak memory 200852 kb
Host smart-6d3e9df5-1a97-4350-b7d1-8907125eb3ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121565726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.121565726
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2715529797
Short name T59
Test name
Test status
Simulation time 171855880814 ps
CPU time 202.06 seconds
Started Jan 14 01:35:22 PM PST 24
Finished Jan 14 01:38:45 PM PST 24
Peak memory 200904 kb
Host smart-6084c1f5-5140-43ce-ae72-ac08b48b244a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715529797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2715529797
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1142976148
Short name T499
Test name
Test status
Simulation time 80568144932 ps
CPU time 334.45 seconds
Started Jan 14 01:35:33 PM PST 24
Finished Jan 14 01:41:08 PM PST 24
Peak memory 201284 kb
Host smart-df716705-31d5-4a36-9620-0dc20bba72ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142976148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1142976148
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3908608027
Short name T817
Test name
Test status
Simulation time 23047156376 ps
CPU time 14.76 seconds
Started Jan 14 01:35:34 PM PST 24
Finished Jan 14 01:35:49 PM PST 24
Peak memory 200744 kb
Host smart-9aa75dc5-1351-4981-9b12-34bf8e985b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908608027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3908608027
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1117349322
Short name T790
Test name
Test status
Simulation time 3736226898 ps
CPU time 9.66 seconds
Started Jan 14 01:35:33 PM PST 24
Finished Jan 14 01:35:43 PM PST 24
Peak memory 200740 kb
Host smart-b093199f-a564-4570-866d-a08bbc190214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117349322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1117349322
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1686210365
Short name T432
Test name
Test status
Simulation time 5705052926 ps
CPU time 13.43 seconds
Started Jan 14 01:35:20 PM PST 24
Finished Jan 14 01:35:34 PM PST 24
Peak memory 200752 kb
Host smart-f6aaa2d5-fa99-4d9e-abbb-52e2948d065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686210365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1686210365
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.680254767
Short name T825
Test name
Test status
Simulation time 33891284553 ps
CPU time 80.51 seconds
Started Jan 14 01:35:36 PM PST 24
Finished Jan 14 01:36:57 PM PST 24
Peak memory 200728 kb
Host smart-5023f521-bc31-4232-906e-4a71caf2a6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680254767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
680254767
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3840273651
Short name T330
Test name
Test status
Simulation time 76765159891 ps
CPU time 85.59 seconds
Started Jan 14 01:35:34 PM PST 24
Finished Jan 14 01:37:00 PM PST 24
Peak memory 201008 kb
Host smart-c37599ce-f851-45bf-b362-e23e32d1f312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840273651 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3840273651
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1455067419
Short name T652
Test name
Test status
Simulation time 402226744 ps
CPU time 0.71 seconds
Started Jan 14 01:35:51 PM PST 24
Finished Jan 14 01:35:52 PM PST 24
Peak memory 200676 kb
Host smart-a1778572-0e59-4647-831a-ee6b869011a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455067419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1455067419
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1434030457
Short name T201
Test name
Test status
Simulation time 493632146463 ps
CPU time 98.59 seconds
Started Jan 14 01:35:42 PM PST 24
Finished Jan 14 01:37:21 PM PST 24
Peak memory 201032 kb
Host smart-34c759d4-2e3e-4fc4-9b1a-cc3b6f1b4abe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434030457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1434030457
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3348594295
Short name T112
Test name
Test status
Simulation time 343917749698 ps
CPU time 713.05 seconds
Started Jan 14 01:35:44 PM PST 24
Finished Jan 14 01:47:37 PM PST 24
Peak memory 200992 kb
Host smart-6159d37c-063c-41d5-b14e-12d72c86ccac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348594295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3348594295
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3059640562
Short name T107
Test name
Test status
Simulation time 167319385693 ps
CPU time 197.9 seconds
Started Jan 14 01:35:33 PM PST 24
Finished Jan 14 01:38:51 PM PST 24
Peak memory 200936 kb
Host smart-af2da8b7-595c-44d3-825b-1c8875697090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059640562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3059640562
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1738660423
Short name T426
Test name
Test status
Simulation time 488757478805 ps
CPU time 1201.38 seconds
Started Jan 14 01:35:42 PM PST 24
Finished Jan 14 01:55:44 PM PST 24
Peak memory 200892 kb
Host smart-98ee2e99-402e-474c-a67d-b23522ee2435
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738660423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1738660423
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3729578639
Short name T321
Test name
Test status
Simulation time 511730147562 ps
CPU time 1178.49 seconds
Started Jan 14 01:35:35 PM PST 24
Finished Jan 14 01:55:14 PM PST 24
Peak memory 200876 kb
Host smart-27d5b88f-45f8-425c-9859-005e344b9c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729578639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3729578639
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2709397327
Short name T436
Test name
Test status
Simulation time 166061588422 ps
CPU time 119.93 seconds
Started Jan 14 01:35:33 PM PST 24
Finished Jan 14 01:37:34 PM PST 24
Peak memory 200888 kb
Host smart-4b484f45-f761-4d9f-ad5e-34f88163d330
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709397327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2709397327
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1026166030
Short name T570
Test name
Test status
Simulation time 497139686566 ps
CPU time 64.96 seconds
Started Jan 14 01:35:45 PM PST 24
Finished Jan 14 01:36:51 PM PST 24
Peak memory 200896 kb
Host smart-d1647664-3282-4e85-9b53-e9fa413a2639
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026166030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1026166030
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.211990095
Short name T212
Test name
Test status
Simulation time 126674844567 ps
CPU time 662.91 seconds
Started Jan 14 01:35:43 PM PST 24
Finished Jan 14 01:46:46 PM PST 24
Peak memory 201384 kb
Host smart-0761d5cb-1119-4a76-9614-da641b395af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211990095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.211990095
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2553716317
Short name T591
Test name
Test status
Simulation time 38527941277 ps
CPU time 20.89 seconds
Started Jan 14 01:35:43 PM PST 24
Finished Jan 14 01:36:05 PM PST 24
Peak memory 200744 kb
Host smart-0d8dc055-38f6-4935-9f86-863cef3ad45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553716317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2553716317
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.989862077
Short name T419
Test name
Test status
Simulation time 4967396886 ps
CPU time 11.51 seconds
Started Jan 14 01:35:42 PM PST 24
Finished Jan 14 01:35:54 PM PST 24
Peak memory 200760 kb
Host smart-293b954b-8792-4f8c-a019-b568793e064d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989862077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.989862077
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3929746153
Short name T521
Test name
Test status
Simulation time 6061744398 ps
CPU time 4.39 seconds
Started Jan 14 01:35:33 PM PST 24
Finished Jan 14 01:35:38 PM PST 24
Peak memory 200704 kb
Host smart-ca233484-a946-4eaf-838f-b501958816dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929746153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3929746153
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1155588641
Short name T118
Test name
Test status
Simulation time 497205260246 ps
CPU time 1156.54 seconds
Started Jan 14 01:35:43 PM PST 24
Finished Jan 14 01:55:00 PM PST 24
Peak memory 200888 kb
Host smart-4b58ee78-5080-4ca3-9bb8-043d8fc41ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155588641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1155588641
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3164030397
Short name T761
Test name
Test status
Simulation time 148946869321 ps
CPU time 152.88 seconds
Started Jan 14 01:35:42 PM PST 24
Finished Jan 14 01:38:15 PM PST 24
Peak memory 209688 kb
Host smart-a0e00dab-9611-41db-9afb-7a9144d19739
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164030397 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3164030397
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3121987781
Short name T29
Test name
Test status
Simulation time 465115961 ps
CPU time 0.88 seconds
Started Jan 14 01:36:00 PM PST 24
Finished Jan 14 01:36:01 PM PST 24
Peak memory 200676 kb
Host smart-888fbbed-588d-4f17-9776-5ec24b9ae449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121987781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3121987781
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1098774584
Short name T762
Test name
Test status
Simulation time 498517014272 ps
CPU time 300.59 seconds
Started Jan 14 01:35:53 PM PST 24
Finished Jan 14 01:40:54 PM PST 24
Peak memory 200860 kb
Host smart-bb7a598a-4d6e-44ff-9712-f2928c26d44e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098774584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1098774584
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3213442573
Short name T567
Test name
Test status
Simulation time 166825386512 ps
CPU time 94.41 seconds
Started Jan 14 01:35:54 PM PST 24
Finished Jan 14 01:37:29 PM PST 24
Peak memory 200848 kb
Host smart-a6025714-3364-43d3-a3ea-c46ca29f603a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213442573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3213442573
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2272272
Short name T164
Test name
Test status
Simulation time 492219310161 ps
CPU time 221.81 seconds
Started Jan 14 01:35:51 PM PST 24
Finished Jan 14 01:39:33 PM PST 24
Peak memory 200900 kb
Host smart-49e893e1-a0b4-4bbb-8c0d-64e121c1f136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2272272
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4242263885
Short name T120
Test name
Test status
Simulation time 166437442140 ps
CPU time 36.06 seconds
Started Jan 14 01:35:52 PM PST 24
Finished Jan 14 01:36:28 PM PST 24
Peak memory 200856 kb
Host smart-a6c4cf03-e232-4974-8bb9-e5e3c569987e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242263885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4242263885
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.478589053
Short name T608
Test name
Test status
Simulation time 497346186898 ps
CPU time 1160.9 seconds
Started Jan 14 01:35:51 PM PST 24
Finished Jan 14 01:55:12 PM PST 24
Peak memory 200900 kb
Host smart-dd423580-d648-416d-b8d7-f7d1c12618b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478589053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.478589053
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3667380912
Short name T535
Test name
Test status
Simulation time 488782780591 ps
CPU time 1133.28 seconds
Started Jan 14 01:35:52 PM PST 24
Finished Jan 14 01:54:46 PM PST 24
Peak memory 200956 kb
Host smart-94282417-d74d-45bd-b55d-4d53a19b5ccc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667380912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3667380912
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3475010979
Short name T730
Test name
Test status
Simulation time 86304466322 ps
CPU time 369.59 seconds
Started Jan 14 01:36:04 PM PST 24
Finished Jan 14 01:42:14 PM PST 24
Peak memory 201384 kb
Host smart-6efc41bb-63d6-4cb8-931a-9e33b298d1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475010979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3475010979
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3947296519
Short name T518
Test name
Test status
Simulation time 47116202460 ps
CPU time 29.5 seconds
Started Jan 14 01:36:00 PM PST 24
Finished Jan 14 01:36:31 PM PST 24
Peak memory 200596 kb
Host smart-9fea6920-bf17-4faa-8e29-921085c0e071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947296519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3947296519
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1697770714
Short name T744
Test name
Test status
Simulation time 3243544750 ps
CPU time 1.11 seconds
Started Jan 14 01:36:00 PM PST 24
Finished Jan 14 01:36:02 PM PST 24
Peak memory 200600 kb
Host smart-50a81da7-9c07-4454-bd66-29ec8cf476b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697770714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1697770714
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3788043390
Short name T861
Test name
Test status
Simulation time 5757059611 ps
CPU time 14.57 seconds
Started Jan 14 01:35:51 PM PST 24
Finished Jan 14 01:36:07 PM PST 24
Peak memory 200668 kb
Host smart-4d276065-67fb-40a8-8589-9c613cca8436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788043390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3788043390
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.203896574
Short name T841
Test name
Test status
Simulation time 14775379022 ps
CPU time 17.05 seconds
Started Jan 14 01:36:08 PM PST 24
Finished Jan 14 01:36:25 PM PST 24
Peak memory 200888 kb
Host smart-7cbfb19c-6bff-4fd7-8501-081c123f9d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203896574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
203896574
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1034846754
Short name T787
Test name
Test status
Simulation time 52212268095 ps
CPU time 69.41 seconds
Started Jan 14 01:36:04 PM PST 24
Finished Jan 14 01:37:14 PM PST 24
Peak memory 209220 kb
Host smart-9d0c9e26-ad52-4799-9328-cfc6395953c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034846754 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1034846754
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.438319197
Short name T807
Test name
Test status
Simulation time 438987207 ps
CPU time 0.87 seconds
Started Jan 14 01:36:18 PM PST 24
Finished Jan 14 01:36:19 PM PST 24
Peak memory 200684 kb
Host smart-65397b3a-40a0-473b-b062-d632da62f5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438319197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.438319197
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1334648798
Short name T288
Test name
Test status
Simulation time 161059236760 ps
CPU time 182.24 seconds
Started Jan 14 01:36:21 PM PST 24
Finished Jan 14 01:39:23 PM PST 24
Peak memory 200960 kb
Host smart-b61bee6f-7418-4e51-bcf7-863a9c54c9f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334648798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1334648798
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.386268850
Short name T772
Test name
Test status
Simulation time 155159547740 ps
CPU time 76.92 seconds
Started Jan 14 01:36:02 PM PST 24
Finished Jan 14 01:37:19 PM PST 24
Peak memory 200856 kb
Host smart-5b9b9579-d3c8-40f9-99a2-896411e647f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=386268850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.386268850
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1548128700
Short name T661
Test name
Test status
Simulation time 166744528530 ps
CPU time 238.64 seconds
Started Jan 14 01:35:59 PM PST 24
Finished Jan 14 01:39:58 PM PST 24
Peak memory 200916 kb
Host smart-46ab8113-b855-4c2d-bc70-433a41f39582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548128700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1548128700
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2481564787
Short name T751
Test name
Test status
Simulation time 327141785333 ps
CPU time 792.8 seconds
Started Jan 14 01:35:59 PM PST 24
Finished Jan 14 01:49:12 PM PST 24
Peak memory 200816 kb
Host smart-6a3aacad-3d5c-4d86-a255-a4029d0b866e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481564787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2481564787
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1387641338
Short name T595
Test name
Test status
Simulation time 494116088898 ps
CPU time 492.78 seconds
Started Jan 14 01:36:00 PM PST 24
Finished Jan 14 01:44:14 PM PST 24
Peak memory 200944 kb
Host smart-d3c6a211-ab79-4695-9051-db562221c946
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387641338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1387641338
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2127336708
Short name T218
Test name
Test status
Simulation time 74954659982 ps
CPU time 375.6 seconds
Started Jan 14 01:36:15 PM PST 24
Finished Jan 14 01:42:31 PM PST 24
Peak memory 201408 kb
Host smart-7e894ae4-7ca2-48bc-bd4a-0dd8d690ad10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127336708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2127336708
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2521144085
Short name T519
Test name
Test status
Simulation time 32140068311 ps
CPU time 7.1 seconds
Started Jan 14 01:36:16 PM PST 24
Finished Jan 14 01:36:24 PM PST 24
Peak memory 200760 kb
Host smart-f437aca4-aba6-4c73-9382-c3c4447980fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521144085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2521144085
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.250376699
Short name T531
Test name
Test status
Simulation time 3234294629 ps
CPU time 8.66 seconds
Started Jan 14 01:36:15 PM PST 24
Finished Jan 14 01:36:25 PM PST 24
Peak memory 200720 kb
Host smart-1dc5f297-b016-4f30-a0f1-98ffaad5c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250376699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.250376699
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.981580934
Short name T431
Test name
Test status
Simulation time 5696288152 ps
CPU time 14.93 seconds
Started Jan 14 01:36:02 PM PST 24
Finished Jan 14 01:36:18 PM PST 24
Peak memory 200740 kb
Host smart-4242c097-9e5c-406b-8fa2-e0552e145141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981580934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.981580934
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1371022152
Short name T641
Test name
Test status
Simulation time 10767939538 ps
CPU time 11.1 seconds
Started Jan 14 01:36:15 PM PST 24
Finished Jan 14 01:36:27 PM PST 24
Peak memory 200764 kb
Host smart-3b712bde-7bdc-4062-9cb2-a866bbf7dd78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371022152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1371022152
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2808770263
Short name T867
Test name
Test status
Simulation time 109483958575 ps
CPU time 262.04 seconds
Started Jan 14 01:36:15 PM PST 24
Finished Jan 14 01:40:38 PM PST 24
Peak memory 209700 kb
Host smart-cfa8d7ba-0e50-415a-8b59-8aa0629e6b2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808770263 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2808770263
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2640410355
Short name T764
Test name
Test status
Simulation time 430814671 ps
CPU time 0.99 seconds
Started Jan 14 01:36:21 PM PST 24
Finished Jan 14 01:36:22 PM PST 24
Peak memory 200648 kb
Host smart-6367cfc8-c313-4e9f-b5db-9d8c3471a15f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640410355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2640410355
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.685634330
Short name T650
Test name
Test status
Simulation time 168238439744 ps
CPU time 369.96 seconds
Started Jan 14 01:36:22 PM PST 24
Finished Jan 14 01:42:32 PM PST 24
Peak memory 200960 kb
Host smart-f09ea507-ddbb-409b-ad2f-1d49637363dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685634330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.685634330
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2436102977
Short name T815
Test name
Test status
Simulation time 325963354228 ps
CPU time 696.8 seconds
Started Jan 14 01:36:16 PM PST 24
Finished Jan 14 01:47:53 PM PST 24
Peak memory 200928 kb
Host smart-541538b4-bd1f-487a-b277-221b576e11fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436102977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2436102977
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2807684551
Short name T662
Test name
Test status
Simulation time 161145657801 ps
CPU time 97.85 seconds
Started Jan 14 01:36:14 PM PST 24
Finished Jan 14 01:37:52 PM PST 24
Peak memory 200928 kb
Host smart-34a8ca9c-7d63-4ae1-b983-fcf49cd71ce6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807684551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2807684551
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3659664530
Short name T543
Test name
Test status
Simulation time 335208163833 ps
CPU time 193.03 seconds
Started Jan 14 01:36:14 PM PST 24
Finished Jan 14 01:39:27 PM PST 24
Peak memory 200916 kb
Host smart-764590c1-7de9-4242-b932-2f39f53940d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659664530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3659664530
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2674773567
Short name T150
Test name
Test status
Simulation time 485506598771 ps
CPU time 298.62 seconds
Started Jan 14 01:36:18 PM PST 24
Finished Jan 14 01:41:17 PM PST 24
Peak memory 200944 kb
Host smart-b3528a38-5751-47a1-bec2-fee80c342769
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674773567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2674773567
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2961754440
Short name T743
Test name
Test status
Simulation time 162373394190 ps
CPU time 372.55 seconds
Started Jan 14 01:36:21 PM PST 24
Finished Jan 14 01:42:34 PM PST 24
Peak memory 200920 kb
Host smart-f7febcd0-3e7a-4fab-83f8-ba4082358da9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961754440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2961754440
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.4229448637
Short name T522
Test name
Test status
Simulation time 161248562311 ps
CPU time 174.74 seconds
Started Jan 14 01:36:13 PM PST 24
Finished Jan 14 01:39:08 PM PST 24
Peak memory 200880 kb
Host smart-45e96b8f-4743-4f4d-a51b-93ec8cb867d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229448637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.4229448637
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1759914531
Short name T688
Test name
Test status
Simulation time 73030376153 ps
CPU time 281.61 seconds
Started Jan 14 01:36:15 PM PST 24
Finished Jan 14 01:40:57 PM PST 24
Peak memory 201376 kb
Host smart-6de745f7-5d25-4dbc-9373-338ecb8150a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759914531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1759914531
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4039174085
Short name T801
Test name
Test status
Simulation time 41364625886 ps
CPU time 45.59 seconds
Started Jan 14 01:36:14 PM PST 24
Finished Jan 14 01:37:00 PM PST 24
Peak memory 200728 kb
Host smart-cf2e2826-e529-4038-90b0-7d3b0f70f62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039174085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4039174085
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1528914396
Short name T829
Test name
Test status
Simulation time 3699271009 ps
CPU time 2.77 seconds
Started Jan 14 01:36:14 PM PST 24
Finished Jan 14 01:36:17 PM PST 24
Peak memory 200756 kb
Host smart-acc3d389-fff8-4f38-9129-0387f9f7d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528914396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1528914396
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1082775192
Short name T475
Test name
Test status
Simulation time 5968965453 ps
CPU time 4.22 seconds
Started Jan 14 01:36:21 PM PST 24
Finished Jan 14 01:36:26 PM PST 24
Peak memory 200712 kb
Host smart-7e53bb68-c493-4139-b733-ebece072d194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082775192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1082775192
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2154668113
Short name T781
Test name
Test status
Simulation time 42198524765 ps
CPU time 100.94 seconds
Started Jan 14 01:36:20 PM PST 24
Finished Jan 14 01:38:01 PM PST 24
Peak memory 200768 kb
Host smart-f3568a6b-f4d0-4e5a-8026-814fdac7e0cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154668113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2154668113
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1494081754
Short name T224
Test name
Test status
Simulation time 8641321105 ps
CPU time 33.8 seconds
Started Jan 14 01:36:20 PM PST 24
Finished Jan 14 01:36:55 PM PST 24
Peak memory 209604 kb
Host smart-c2151be9-b220-4ffb-a381-bc256e420d26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494081754 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1494081754
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3199847157
Short name T479
Test name
Test status
Simulation time 469661473 ps
CPU time 0.77 seconds
Started Jan 14 01:36:34 PM PST 24
Finished Jan 14 01:36:40 PM PST 24
Peak memory 200580 kb
Host smart-44ff2a75-a832-4c6e-834b-e8367a0a385e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199847157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3199847157
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.182702273
Short name T39
Test name
Test status
Simulation time 326870150057 ps
CPU time 332.26 seconds
Started Jan 14 01:36:19 PM PST 24
Finished Jan 14 01:41:52 PM PST 24
Peak memory 200984 kb
Host smart-20bc2594-229f-4d05-ac18-650ff0a2f76c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182702273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.182702273
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2882801459
Short name T181
Test name
Test status
Simulation time 500908952644 ps
CPU time 268.94 seconds
Started Jan 14 01:36:21 PM PST 24
Finished Jan 14 01:40:51 PM PST 24
Peak memory 200864 kb
Host smart-0e648678-3097-4f5c-b0c0-96506ac3d4f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882801459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2882801459
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.4152509409
Short name T182
Test name
Test status
Simulation time 337602937409 ps
CPU time 212.55 seconds
Started Jan 14 01:36:20 PM PST 24
Finished Jan 14 01:39:53 PM PST 24
Peak memory 200916 kb
Host smart-771babd7-a4fe-4f40-beac-e75a3ed5fcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152509409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.4152509409
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.444980074
Short name T571
Test name
Test status
Simulation time 328205579020 ps
CPU time 747.77 seconds
Started Jan 14 01:36:24 PM PST 24
Finished Jan 14 01:48:53 PM PST 24
Peak memory 200812 kb
Host smart-6d112a7c-22e0-4cae-85be-cc2dfddca61d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=444980074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.444980074
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2230563472
Short name T123
Test name
Test status
Simulation time 318373977779 ps
CPU time 702.62 seconds
Started Jan 14 01:36:24 PM PST 24
Finished Jan 14 01:48:08 PM PST 24
Peak memory 200960 kb
Host smart-d945f7bd-43af-4737-b1b9-d4b8ecce4fb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230563472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2230563472
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2066384872
Short name T627
Test name
Test status
Simulation time 331999373836 ps
CPU time 184.87 seconds
Started Jan 14 01:36:24 PM PST 24
Finished Jan 14 01:39:30 PM PST 24
Peak memory 200948 kb
Host smart-11ed4e48-03cc-4be5-a007-ec5f67c8c708
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066384872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2066384872
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1745412741
Short name T677
Test name
Test status
Simulation time 114432674069 ps
CPU time 422.43 seconds
Started Jan 14 01:36:32 PM PST 24
Finished Jan 14 01:43:36 PM PST 24
Peak memory 201396 kb
Host smart-94bb5647-18cc-479a-918d-6cb2188cb57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745412741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1745412741
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3908606043
Short name T501
Test name
Test status
Simulation time 40513840420 ps
CPU time 91.33 seconds
Started Jan 14 01:36:20 PM PST 24
Finished Jan 14 01:37:52 PM PST 24
Peak memory 200712 kb
Host smart-7812d71c-27de-413b-aab5-88b6ba651e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908606043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3908606043
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.548114564
Short name T733
Test name
Test status
Simulation time 3078014990 ps
CPU time 2.35 seconds
Started Jan 14 01:36:20 PM PST 24
Finished Jan 14 01:36:23 PM PST 24
Peak memory 200724 kb
Host smart-18d6eba7-4373-4431-921d-e16ab4ea7405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548114564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.548114564
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3980318626
Short name T771
Test name
Test status
Simulation time 6095597031 ps
CPU time 14.82 seconds
Started Jan 14 01:36:20 PM PST 24
Finished Jan 14 01:36:35 PM PST 24
Peak memory 200676 kb
Host smart-cff55853-cf73-4783-b763-845c51fcdb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980318626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3980318626
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.213738783
Short name T748
Test name
Test status
Simulation time 817673407835 ps
CPU time 1311.57 seconds
Started Jan 14 01:36:33 PM PST 24
Finished Jan 14 01:58:31 PM PST 24
Peak memory 217760 kb
Host smart-ae86378e-8025-4bef-a49c-5aff81de483e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213738783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
213738783
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.13158401
Short name T678
Test name
Test status
Simulation time 373420939 ps
CPU time 1.51 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:33:47 PM PST 24
Peak memory 200684 kb
Host smart-a88bed4e-00bd-4f91-a840-2e83841595fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13158401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.13158401
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2494577163
Short name T153
Test name
Test status
Simulation time 164168690697 ps
CPU time 43.97 seconds
Started Jan 14 01:33:38 PM PST 24
Finished Jan 14 01:34:23 PM PST 24
Peak memory 200952 kb
Host smart-c10ba7d6-06c1-46a3-a99f-e5b2d79b39f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494577163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2494577163
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.371060072
Short name T50
Test name
Test status
Simulation time 165684028988 ps
CPU time 407.96 seconds
Started Jan 14 01:33:37 PM PST 24
Finished Jan 14 01:40:26 PM PST 24
Peak memory 200912 kb
Host smart-6b8e530b-8441-42e9-a5d3-238e4f5688f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371060072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.371060072
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.675266238
Short name T699
Test name
Test status
Simulation time 160904785701 ps
CPU time 358.37 seconds
Started Jan 14 01:33:47 PM PST 24
Finished Jan 14 01:39:46 PM PST 24
Peak memory 200924 kb
Host smart-79b6a946-8909-4696-9f10-77d638d02d27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=675266238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.675266238
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1354386253
Short name T705
Test name
Test status
Simulation time 170928330145 ps
CPU time 350.39 seconds
Started Jan 14 01:33:57 PM PST 24
Finished Jan 14 01:39:48 PM PST 24
Peak memory 199732 kb
Host smart-b69babfd-02d5-4a87-a5c2-65683a942e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354386253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1354386253
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3416400514
Short name T810
Test name
Test status
Simulation time 331213778687 ps
CPU time 172.22 seconds
Started Jan 14 01:33:41 PM PST 24
Finished Jan 14 01:36:34 PM PST 24
Peak memory 200972 kb
Host smart-04e2a0b6-e4fe-40e3-a6aa-fcf00e1c83bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416400514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3416400514
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1369555410
Short name T167
Test name
Test status
Simulation time 165234896800 ps
CPU time 60.12 seconds
Started Jan 14 01:33:35 PM PST 24
Finished Jan 14 01:34:35 PM PST 24
Peak memory 200964 kb
Host smart-74d20df5-c4a5-4496-90ab-4f581eba3c64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369555410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1369555410
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.179339637
Short name T638
Test name
Test status
Simulation time 165548123088 ps
CPU time 98.46 seconds
Started Jan 14 01:33:35 PM PST 24
Finished Jan 14 01:35:14 PM PST 24
Peak memory 200892 kb
Host smart-939a02d6-1526-4aff-a2ba-caede0436db5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179339637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.179339637
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.235249896
Short name T214
Test name
Test status
Simulation time 100139384673 ps
CPU time 365.68 seconds
Started Jan 14 01:33:35 PM PST 24
Finished Jan 14 01:39:41 PM PST 24
Peak memory 201260 kb
Host smart-7c0554b0-cd51-431e-8397-2a4074697f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235249896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.235249896
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3570564182
Short name T485
Test name
Test status
Simulation time 42306959456 ps
CPU time 14.95 seconds
Started Jan 14 01:33:39 PM PST 24
Finished Jan 14 01:33:54 PM PST 24
Peak memory 200752 kb
Host smart-df717e7c-f363-42a6-a9c4-f718c9fb00a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570564182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3570564182
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1662251974
Short name T600
Test name
Test status
Simulation time 4637300478 ps
CPU time 1.94 seconds
Started Jan 14 01:33:45 PM PST 24
Finished Jan 14 01:33:48 PM PST 24
Peak memory 200636 kb
Host smart-6beb9765-fc9c-4602-803b-9e342245d228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662251974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1662251974
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1731638244
Short name T49
Test name
Test status
Simulation time 4150088490 ps
CPU time 3 seconds
Started Jan 14 01:33:39 PM PST 24
Finished Jan 14 01:33:42 PM PST 24
Peak memory 216144 kb
Host smart-decf24a1-2628-4263-bc9e-4a7704c8cf80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731638244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1731638244
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.42609695
Short name T673
Test name
Test status
Simulation time 5850337588 ps
CPU time 4.13 seconds
Started Jan 14 01:33:54 PM PST 24
Finished Jan 14 01:33:59 PM PST 24
Peak memory 200816 kb
Host smart-3103a7cf-74c0-475c-a60a-cdb3c591d740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42609695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.42609695
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3851689464
Short name T487
Test name
Test status
Simulation time 354568956 ps
CPU time 1.03 seconds
Started Jan 14 01:36:45 PM PST 24
Finished Jan 14 01:36:51 PM PST 24
Peak memory 200608 kb
Host smart-2e7931c0-e495-4013-8ea4-30bbbbfa2e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851689464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3851689464
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1170753777
Short name T233
Test name
Test status
Simulation time 160709817168 ps
CPU time 64.33 seconds
Started Jan 14 01:36:37 PM PST 24
Finished Jan 14 01:37:49 PM PST 24
Peak memory 200912 kb
Host smart-be793bd7-9815-44af-a830-dfb738567931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170753777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1170753777
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3431817089
Short name T252
Test name
Test status
Simulation time 506310540729 ps
CPU time 1101.96 seconds
Started Jan 14 01:36:32 PM PST 24
Finished Jan 14 01:54:56 PM PST 24
Peak memory 200960 kb
Host smart-2ab4c27f-3b1d-4f11-94c3-8b605ee2f627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431817089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3431817089
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.311949433
Short name T25
Test name
Test status
Simulation time 498321042373 ps
CPU time 1134.19 seconds
Started Jan 14 01:36:31 PM PST 24
Finished Jan 14 01:55:27 PM PST 24
Peak memory 200868 kb
Host smart-27796f06-13ad-408c-8ba3-d06c80386919
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=311949433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.311949433
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3535837571
Short name T607
Test name
Test status
Simulation time 331562592193 ps
CPU time 464.21 seconds
Started Jan 14 01:36:35 PM PST 24
Finished Jan 14 01:44:28 PM PST 24
Peak memory 200952 kb
Host smart-a87fa99f-fc04-4cfe-8248-6df506455470
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535837571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3535837571
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1890100813
Short name T715
Test name
Test status
Simulation time 166646646874 ps
CPU time 38.38 seconds
Started Jan 14 01:36:45 PM PST 24
Finished Jan 14 01:37:26 PM PST 24
Peak memory 200816 kb
Host smart-99048ce5-a350-47a3-99f1-a5951d5a7336
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890100813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1890100813
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1159240136
Short name T798
Test name
Test status
Simulation time 492700530626 ps
CPU time 1070.02 seconds
Started Jan 14 01:36:45 PM PST 24
Finished Jan 14 01:54:40 PM PST 24
Peak memory 200812 kb
Host smart-7004ce31-3f40-4c9c-bf87-04911d40d977
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159240136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1159240136
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2191080299
Short name T215
Test name
Test status
Simulation time 107588969248 ps
CPU time 401.71 seconds
Started Jan 14 01:36:45 PM PST 24
Finished Jan 14 01:43:30 PM PST 24
Peak memory 201292 kb
Host smart-0d3c0bfc-29b2-4102-bc4b-4aa24da910af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191080299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2191080299
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2877418792
Short name T590
Test name
Test status
Simulation time 31500139550 ps
CPU time 74.62 seconds
Started Jan 14 01:36:37 PM PST 24
Finished Jan 14 01:37:59 PM PST 24
Peak memory 200760 kb
Host smart-21a1c1b2-e19b-4ab4-9587-a36419880542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877418792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2877418792
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1221164352
Short name T435
Test name
Test status
Simulation time 4116834012 ps
CPU time 4.17 seconds
Started Jan 14 01:36:37 PM PST 24
Finished Jan 14 01:36:49 PM PST 24
Peak memory 200760 kb
Host smart-bf4ad0eb-f06f-4710-9297-2708081a6e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221164352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1221164352
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3659875801
Short name T723
Test name
Test status
Simulation time 5800599339 ps
CPU time 7.86 seconds
Started Jan 14 01:36:37 PM PST 24
Finished Jan 14 01:36:52 PM PST 24
Peak memory 200668 kb
Host smart-0c2bbb52-ff46-4566-a67c-545e4802e1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659875801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3659875801
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1423439260
Short name T22
Test name
Test status
Simulation time 89880626702 ps
CPU time 326.8 seconds
Started Jan 14 01:36:39 PM PST 24
Finished Jan 14 01:42:12 PM PST 24
Peak memory 201344 kb
Host smart-79742c14-0d8a-42bc-853a-083c6c154978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423439260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1423439260
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3690901313
Short name T225
Test name
Test status
Simulation time 25388074930 ps
CPU time 57.5 seconds
Started Jan 14 01:36:39 PM PST 24
Finished Jan 14 01:37:42 PM PST 24
Peak memory 200928 kb
Host smart-5c55554e-169c-4fdd-8fdc-1d68c17b5488
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690901313 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3690901313
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3005934761
Short name T44
Test name
Test status
Simulation time 435328054 ps
CPU time 1.63 seconds
Started Jan 14 01:36:52 PM PST 24
Finished Jan 14 01:36:55 PM PST 24
Peak memory 200676 kb
Host smart-a07d3c70-1a4f-4b86-ad32-e0244dad8470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005934761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3005934761
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.4179479551
Short name T305
Test name
Test status
Simulation time 477529172538 ps
CPU time 371.64 seconds
Started Jan 14 01:36:48 PM PST 24
Finished Jan 14 01:43:03 PM PST 24
Peak memory 200784 kb
Host smart-d439e131-87fa-4495-8416-3a4554417a5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179479551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.4179479551
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2066024645
Short name T311
Test name
Test status
Simulation time 501882646084 ps
CPU time 1169.5 seconds
Started Jan 14 01:36:47 PM PST 24
Finished Jan 14 01:56:21 PM PST 24
Peak memory 200988 kb
Host smart-a21d89d7-1d95-4707-867c-52c882eb3273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066024645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2066024645
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3920152613
Short name T707
Test name
Test status
Simulation time 164544793308 ps
CPU time 361.76 seconds
Started Jan 14 01:36:44 PM PST 24
Finished Jan 14 01:42:50 PM PST 24
Peak memory 200808 kb
Host smart-66700030-c3fb-4aa9-8628-8522972ff119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920152613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3920152613
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3518771635
Short name T520
Test name
Test status
Simulation time 325335660305 ps
CPU time 739.45 seconds
Started Jan 14 01:36:37 PM PST 24
Finished Jan 14 01:49:04 PM PST 24
Peak memory 200848 kb
Host smart-ffefae2b-7fdc-45ee-a614-3deee029c4cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518771635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3518771635
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2075589278
Short name T121
Test name
Test status
Simulation time 167299129768 ps
CPU time 100.03 seconds
Started Jan 14 01:36:38 PM PST 24
Finished Jan 14 01:38:24 PM PST 24
Peak memory 200964 kb
Host smart-ecb2fa62-6c83-4456-8517-bccdbf82952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075589278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2075589278
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1856136168
Short name T775
Test name
Test status
Simulation time 163973331586 ps
CPU time 385.79 seconds
Started Jan 14 01:36:38 PM PST 24
Finished Jan 14 01:43:10 PM PST 24
Peak memory 200836 kb
Host smart-c7af3618-f31e-46d9-ac9b-70474ca3d51a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856136168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1856136168
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2532876911
Short name T271
Test name
Test status
Simulation time 492620293992 ps
CPU time 569.29 seconds
Started Jan 14 01:36:38 PM PST 24
Finished Jan 14 01:46:14 PM PST 24
Peak memory 200948 kb
Host smart-0c961d92-0411-4770-94a9-89ccdd1d7760
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532876911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2532876911
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1654889281
Short name T540
Test name
Test status
Simulation time 328800954208 ps
CPU time 383.96 seconds
Started Jan 14 01:36:47 PM PST 24
Finished Jan 14 01:43:15 PM PST 24
Peak memory 200944 kb
Host smart-cf16ad75-13b0-4db9-b027-71e782394508
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654889281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1654889281
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1932493579
Short name T207
Test name
Test status
Simulation time 123308720581 ps
CPU time 690.69 seconds
Started Jan 14 01:36:46 PM PST 24
Finished Jan 14 01:48:21 PM PST 24
Peak memory 201348 kb
Host smart-288684b6-e48d-486e-a6f4-f718b7ade340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932493579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1932493579
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4113059783
Short name T750
Test name
Test status
Simulation time 25693980208 ps
CPU time 15.9 seconds
Started Jan 14 01:36:47 PM PST 24
Finished Jan 14 01:37:07 PM PST 24
Peak memory 200596 kb
Host smart-02dbe72e-1cd9-45d8-9fdb-cda3fb11f5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113059783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4113059783
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.886495581
Short name T844
Test name
Test status
Simulation time 5130219430 ps
CPU time 3.95 seconds
Started Jan 14 01:36:47 PM PST 24
Finished Jan 14 01:36:55 PM PST 24
Peak memory 200752 kb
Host smart-62c88719-0a88-4967-9227-4c4e501f0283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886495581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.886495581
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.390551057
Short name T774
Test name
Test status
Simulation time 5821857428 ps
CPU time 15.28 seconds
Started Jan 14 01:36:39 PM PST 24
Finished Jan 14 01:37:02 PM PST 24
Peak memory 200804 kb
Host smart-e62aa82c-d741-457c-bc30-2c18d8655fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390551057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.390551057
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.767685219
Short name T858
Test name
Test status
Simulation time 102136513924 ps
CPU time 298.61 seconds
Started Jan 14 01:36:53 PM PST 24
Finished Jan 14 01:41:53 PM PST 24
Peak memory 201272 kb
Host smart-3ad2037d-c179-4e56-afac-e4b82e5b926c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767685219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
767685219
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3911171880
Short name T260
Test name
Test status
Simulation time 95247489193 ps
CPU time 231.18 seconds
Started Jan 14 01:36:54 PM PST 24
Finished Jan 14 01:40:46 PM PST 24
Peak memory 209544 kb
Host smart-3d8075d4-03bf-4cd0-b56d-517d7a6454f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911171880 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3911171880
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3936702334
Short name T459
Test name
Test status
Simulation time 444332644 ps
CPU time 1.14 seconds
Started Jan 14 01:37:00 PM PST 24
Finished Jan 14 01:37:03 PM PST 24
Peak memory 200692 kb
Host smart-83d15ad5-98e7-460f-b46e-af0e6c1c1299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936702334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3936702334
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.65687387
Short name T192
Test name
Test status
Simulation time 325210088283 ps
CPU time 195.28 seconds
Started Jan 14 01:37:00 PM PST 24
Finished Jan 14 01:40:17 PM PST 24
Peak memory 200880 kb
Host smart-3826e3e9-8822-455f-b6b3-700c3b7d4a93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65687387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gatin
g.65687387
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1825409416
Short name T811
Test name
Test status
Simulation time 499015039037 ps
CPU time 597.55 seconds
Started Jan 14 01:37:01 PM PST 24
Finished Jan 14 01:47:00 PM PST 24
Peak memory 200912 kb
Host smart-0fd4da3b-6f68-4e9d-98d1-afed7f473e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825409416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1825409416
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2026267907
Short name T640
Test name
Test status
Simulation time 170347962010 ps
CPU time 379.65 seconds
Started Jan 14 01:36:53 PM PST 24
Finished Jan 14 01:43:13 PM PST 24
Peak memory 200844 kb
Host smart-330c9848-1db2-4299-b5ee-d7f11c0ccb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026267907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2026267907
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1869673012
Short name T488
Test name
Test status
Simulation time 337985959705 ps
CPU time 201.16 seconds
Started Jan 14 01:36:56 PM PST 24
Finished Jan 14 01:40:18 PM PST 24
Peak memory 200860 kb
Host smart-bd1024be-b48a-4070-9f05-b5ca32b28afb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869673012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1869673012
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2296029922
Short name T656
Test name
Test status
Simulation time 488647334434 ps
CPU time 262.17 seconds
Started Jan 14 01:36:54 PM PST 24
Finished Jan 14 01:41:18 PM PST 24
Peak memory 200864 kb
Host smart-29d106b8-965e-41ae-b166-6c424a835a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296029922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2296029922
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1241821733
Short name T469
Test name
Test status
Simulation time 322195715492 ps
CPU time 687.72 seconds
Started Jan 14 01:36:55 PM PST 24
Finished Jan 14 01:48:23 PM PST 24
Peak memory 200888 kb
Host smart-0f7b572c-ca30-4ed9-8ac1-0da27f3b2b48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241821733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1241821733
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3541822186
Short name T136
Test name
Test status
Simulation time 499089682445 ps
CPU time 851.14 seconds
Started Jan 14 01:36:59 PM PST 24
Finished Jan 14 01:51:13 PM PST 24
Peak memory 200956 kb
Host smart-9b182bef-176e-422a-a9d4-85df679a3d4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541822186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3541822186
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2564347787
Short name T547
Test name
Test status
Simulation time 163540244314 ps
CPU time 192.36 seconds
Started Jan 14 01:37:02 PM PST 24
Finished Jan 14 01:40:17 PM PST 24
Peak memory 200884 kb
Host smart-a4b215e7-f345-4609-84ab-a53c2e2382ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564347787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2564347787
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.597457947
Short name T610
Test name
Test status
Simulation time 143720539998 ps
CPU time 541.9 seconds
Started Jan 14 01:37:02 PM PST 24
Finished Jan 14 01:46:06 PM PST 24
Peak memory 201432 kb
Host smart-3b55e98e-f70a-4689-9a8a-54cf1fa04b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597457947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.597457947
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1359348092
Short name T503
Test name
Test status
Simulation time 38017950890 ps
CPU time 92.19 seconds
Started Jan 14 01:37:00 PM PST 24
Finished Jan 14 01:38:34 PM PST 24
Peak memory 200728 kb
Host smart-b3e90c7c-3120-4fd7-83d2-ef9196ade07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359348092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1359348092
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2115078576
Short name T578
Test name
Test status
Simulation time 3107289893 ps
CPU time 2.6 seconds
Started Jan 14 01:37:02 PM PST 24
Finished Jan 14 01:37:06 PM PST 24
Peak memory 200744 kb
Host smart-8e2d945d-76d1-4294-8af6-d27bf6e34d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115078576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2115078576
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2506650045
Short name T778
Test name
Test status
Simulation time 5835592881 ps
CPU time 4.37 seconds
Started Jan 14 01:36:54 PM PST 24
Finished Jan 14 01:36:59 PM PST 24
Peak memory 200736 kb
Host smart-1977e777-1078-4520-a913-f39a92b6bcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506650045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2506650045
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.730638773
Short name T368
Test name
Test status
Simulation time 146882499819 ps
CPU time 385.19 seconds
Started Jan 14 01:37:00 PM PST 24
Finished Jan 14 01:43:27 PM PST 24
Peak memory 201340 kb
Host smart-620b1f7e-ca5c-48c9-8401-96e561a97019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730638773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
730638773
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3017497913
Short name T779
Test name
Test status
Simulation time 24546634891 ps
CPU time 70.87 seconds
Started Jan 14 01:37:00 PM PST 24
Finished Jan 14 01:38:13 PM PST 24
Peak memory 209636 kb
Host smart-15ae2dc0-b641-4e32-9892-973fc56051cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017497913 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3017497913
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3064311861
Short name T461
Test name
Test status
Simulation time 485808461 ps
CPU time 1.68 seconds
Started Jan 14 01:37:12 PM PST 24
Finished Jan 14 01:37:15 PM PST 24
Peak memory 200636 kb
Host smart-bac8097c-04c7-477b-8f61-f265f74e6775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064311861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3064311861
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.652081720
Short name T135
Test name
Test status
Simulation time 320320179422 ps
CPU time 630.62 seconds
Started Jan 14 01:37:14 PM PST 24
Finished Jan 14 01:47:46 PM PST 24
Peak memory 200856 kb
Host smart-c6574c80-c7e9-4d6f-acd2-e97be5305c54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652081720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.652081720
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1536467404
Short name T334
Test name
Test status
Simulation time 336461339028 ps
CPU time 193.18 seconds
Started Jan 14 01:37:13 PM PST 24
Finished Jan 14 01:40:27 PM PST 24
Peak memory 200920 kb
Host smart-a44f85d0-6c54-4dc5-a594-6b9206b531c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536467404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1536467404
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1930660965
Short name T777
Test name
Test status
Simulation time 486350303611 ps
CPU time 293.57 seconds
Started Jan 14 01:37:01 PM PST 24
Finished Jan 14 01:41:56 PM PST 24
Peak memory 200932 kb
Host smart-c7db6888-01c5-4a37-81d4-f572fae898c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930660965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1930660965
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1343306463
Short name T780
Test name
Test status
Simulation time 489023018887 ps
CPU time 1152.43 seconds
Started Jan 14 01:37:01 PM PST 24
Finished Jan 14 01:56:15 PM PST 24
Peak memory 200928 kb
Host smart-04d8e5b8-4888-433c-92d3-2267f87c1e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343306463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1343306463
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3201291191
Short name T480
Test name
Test status
Simulation time 324824925921 ps
CPU time 129.22 seconds
Started Jan 14 01:37:02 PM PST 24
Finished Jan 14 01:39:12 PM PST 24
Peak memory 200924 kb
Host smart-1e2539bb-6c41-4e8f-a7de-1998e4520009
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201291191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3201291191
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1395615330
Short name T740
Test name
Test status
Simulation time 326897586190 ps
CPU time 359.66 seconds
Started Jan 14 01:37:15 PM PST 24
Finished Jan 14 01:43:16 PM PST 24
Peak memory 200908 kb
Host smart-e5cfc400-409f-4867-9415-399c3e58c718
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395615330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1395615330
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3931795650
Short name T15
Test name
Test status
Simulation time 317396605034 ps
CPU time 729.57 seconds
Started Jan 14 01:37:10 PM PST 24
Finished Jan 14 01:49:21 PM PST 24
Peak memory 200900 kb
Host smart-77744fd5-ecff-440d-931b-2df6bfdd0d26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931795650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3931795650
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1983729850
Short name T159
Test name
Test status
Simulation time 103151037635 ps
CPU time 382.1 seconds
Started Jan 14 01:37:12 PM PST 24
Finished Jan 14 01:43:36 PM PST 24
Peak memory 201344 kb
Host smart-e35707bc-3c1d-452b-b4af-d4799faa000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983729850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1983729850
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.188672168
Short name T651
Test name
Test status
Simulation time 26872969557 ps
CPU time 30.75 seconds
Started Jan 14 01:37:14 PM PST 24
Finished Jan 14 01:37:46 PM PST 24
Peak memory 200740 kb
Host smart-f6405f18-7923-4f70-9838-6e699e347101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188672168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.188672168
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2833090966
Short name T619
Test name
Test status
Simulation time 4514007330 ps
CPU time 10.36 seconds
Started Jan 14 01:37:15 PM PST 24
Finished Jan 14 01:37:26 PM PST 24
Peak memory 200728 kb
Host smart-8605837c-b19c-443f-bbf7-624d51d4f3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833090966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2833090966
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1366468043
Short name T585
Test name
Test status
Simulation time 5731288746 ps
CPU time 6.89 seconds
Started Jan 14 01:37:02 PM PST 24
Finished Jan 14 01:37:10 PM PST 24
Peak memory 200744 kb
Host smart-69ce43f3-2708-4175-a468-093bc119e21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366468043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1366468043
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3690857216
Short name T365
Test name
Test status
Simulation time 275756659210 ps
CPU time 917.84 seconds
Started Jan 14 01:37:12 PM PST 24
Finished Jan 14 01:52:31 PM PST 24
Peak memory 201384 kb
Host smart-c8c919b9-d4d6-4803-b882-eae916cf9429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690857216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3690857216
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.747520204
Short name T160
Test name
Test status
Simulation time 31344537357 ps
CPU time 99.7 seconds
Started Jan 14 01:37:14 PM PST 24
Finished Jan 14 01:38:54 PM PST 24
Peak memory 209452 kb
Host smart-f99445aa-84de-4be9-bba1-49829d44d15b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747520204 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.747520204
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2329089474
Short name T467
Test name
Test status
Simulation time 353841718 ps
CPU time 1.42 seconds
Started Jan 14 01:37:28 PM PST 24
Finished Jan 14 01:37:31 PM PST 24
Peak memory 200580 kb
Host smart-477bbc25-85d6-4cac-850f-f938eb9e1934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329089474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2329089474
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.4105369950
Short name T129
Test name
Test status
Simulation time 488778785076 ps
CPU time 305.66 seconds
Started Jan 14 01:37:29 PM PST 24
Finished Jan 14 01:42:36 PM PST 24
Peak memory 200908 kb
Host smart-87ddf0ea-b6d6-4834-adda-feaad048aa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105369950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4105369950
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1267897715
Short name T758
Test name
Test status
Simulation time 331348867188 ps
CPU time 787.7 seconds
Started Jan 14 01:37:18 PM PST 24
Finished Jan 14 01:50:27 PM PST 24
Peak memory 200828 kb
Host smart-e241a821-9032-43ad-b328-0ad2935c56dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267897715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1267897715
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1245850118
Short name T173
Test name
Test status
Simulation time 161859399922 ps
CPU time 87.28 seconds
Started Jan 14 01:37:19 PM PST 24
Finished Jan 14 01:38:47 PM PST 24
Peak memory 201024 kb
Host smart-088def66-dec6-45ae-9edf-dfa09d6be3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245850118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1245850118
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2409276619
Short name T632
Test name
Test status
Simulation time 487554269829 ps
CPU time 1201.59 seconds
Started Jan 14 01:37:16 PM PST 24
Finished Jan 14 01:57:19 PM PST 24
Peak memory 200844 kb
Host smart-d614b3db-ff18-4869-80e6-e6100c34d763
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409276619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2409276619
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2191568991
Short name T757
Test name
Test status
Simulation time 504931864271 ps
CPU time 1250.48 seconds
Started Jan 14 01:37:17 PM PST 24
Finished Jan 14 01:58:09 PM PST 24
Peak memory 200812 kb
Host smart-20b129eb-e782-4be2-ac35-1c5c1d7e0ae3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191568991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2191568991
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3009307997
Short name T577
Test name
Test status
Simulation time 173273055460 ps
CPU time 390 seconds
Started Jan 14 01:37:17 PM PST 24
Finished Jan 14 01:43:48 PM PST 24
Peak memory 200848 kb
Host smart-00fa9f9d-406e-4a15-947d-039baccdd11f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009307997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3009307997
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.524976886
Short name T367
Test name
Test status
Simulation time 76844762764 ps
CPU time 446.07 seconds
Started Jan 14 01:37:32 PM PST 24
Finished Jan 14 01:44:59 PM PST 24
Peak memory 201304 kb
Host smart-8c80a918-6ed7-4004-9df6-f440713d4b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524976886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.524976886
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2668653712
Short name T622
Test name
Test status
Simulation time 22697854836 ps
CPU time 53.33 seconds
Started Jan 14 01:37:28 PM PST 24
Finished Jan 14 01:38:23 PM PST 24
Peak memory 200644 kb
Host smart-a0fe4950-d697-4e99-8321-582899ec1ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668653712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2668653712
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3984824597
Short name T642
Test name
Test status
Simulation time 3994473095 ps
CPU time 8.2 seconds
Started Jan 14 01:37:30 PM PST 24
Finished Jan 14 01:37:39 PM PST 24
Peak memory 200712 kb
Host smart-a3c65bab-da1e-4896-b489-e3a452d5f375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984824597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3984824597
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.724825149
Short name T732
Test name
Test status
Simulation time 5865734445 ps
CPU time 4.04 seconds
Started Jan 14 01:37:14 PM PST 24
Finished Jan 14 01:37:19 PM PST 24
Peak memory 200744 kb
Host smart-bd8dfea1-7888-4e08-82a3-6572c1ac33a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724825149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.724825149
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1769120997
Short name T141
Test name
Test status
Simulation time 487352141552 ps
CPU time 815.79 seconds
Started Jan 14 01:37:36 PM PST 24
Finished Jan 14 01:51:13 PM PST 24
Peak memory 200932 kb
Host smart-eb99798a-a1da-4a4a-b2bb-b32679aff29b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769120997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1769120997
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.209316653
Short name T354
Test name
Test status
Simulation time 174860199548 ps
CPU time 215.94 seconds
Started Jan 14 01:37:31 PM PST 24
Finished Jan 14 01:41:08 PM PST 24
Peak memory 209548 kb
Host smart-cbf49d79-0935-4d99-9361-473e18dc2cd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209316653 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.209316653
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3279677532
Short name T494
Test name
Test status
Simulation time 466491307 ps
CPU time 1.64 seconds
Started Jan 14 01:37:36 PM PST 24
Finished Jan 14 01:37:39 PM PST 24
Peak memory 200628 kb
Host smart-74c99be4-fc87-42a3-bf42-aa81b9e42c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279677532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3279677532
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1390268989
Short name T284
Test name
Test status
Simulation time 500075528534 ps
CPU time 197.8 seconds
Started Jan 14 01:37:41 PM PST 24
Finished Jan 14 01:40:59 PM PST 24
Peak memory 200868 kb
Host smart-849675fd-89e0-4a67-b725-0d6c9102fe6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390268989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1390268989
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3940731448
Short name T175
Test name
Test status
Simulation time 332117829636 ps
CPU time 374.53 seconds
Started Jan 14 01:37:37 PM PST 24
Finished Jan 14 01:43:53 PM PST 24
Peak memory 200872 kb
Host smart-085c560d-e639-44f5-afd4-f61c36fc49ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940731448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3940731448
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2253952820
Short name T161
Test name
Test status
Simulation time 169390313501 ps
CPU time 82.38 seconds
Started Jan 14 01:37:37 PM PST 24
Finished Jan 14 01:39:01 PM PST 24
Peak memory 200948 kb
Host smart-f89e488b-324f-4df0-a1c3-d203fdcbb285
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253952820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2253952820
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3653980586
Short name T742
Test name
Test status
Simulation time 324043213732 ps
CPU time 695.49 seconds
Started Jan 14 01:37:27 PM PST 24
Finished Jan 14 01:49:04 PM PST 24
Peak memory 200872 kb
Host smart-8b279fa1-1fc2-4504-8de3-415999bfe9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653980586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3653980586
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1532707117
Short name T428
Test name
Test status
Simulation time 327226613721 ps
CPU time 749.74 seconds
Started Jan 14 01:37:28 PM PST 24
Finished Jan 14 01:49:59 PM PST 24
Peak memory 200892 kb
Host smart-7266cf3b-975d-4044-95d5-ec6af724149f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532707117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1532707117
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3937867879
Short name T813
Test name
Test status
Simulation time 493825071382 ps
CPU time 178.69 seconds
Started Jan 14 01:37:44 PM PST 24
Finished Jan 14 01:40:43 PM PST 24
Peak memory 200752 kb
Host smart-66badf83-e477-4521-bd32-052f9bcb512b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937867879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3937867879
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1327860469
Short name T691
Test name
Test status
Simulation time 333138669468 ps
CPU time 182.86 seconds
Started Jan 14 01:37:43 PM PST 24
Finished Jan 14 01:40:47 PM PST 24
Peak memory 200904 kb
Host smart-9cc384d5-c4c2-4b69-a579-4a73306319f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327860469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1327860469
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2579232918
Short name T788
Test name
Test status
Simulation time 78333548699 ps
CPU time 393.57 seconds
Started Jan 14 01:37:39 PM PST 24
Finished Jan 14 01:44:13 PM PST 24
Peak memory 201316 kb
Host smart-c8eaa675-301c-4cdf-9398-5e32b5c2d000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579232918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2579232918
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.878624153
Short name T808
Test name
Test status
Simulation time 43087403117 ps
CPU time 25.62 seconds
Started Jan 14 01:37:35 PM PST 24
Finished Jan 14 01:38:02 PM PST 24
Peak memory 200684 kb
Host smart-64cbf73b-d2f4-4176-9f5e-7656fe371f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878624153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.878624153
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2499112002
Short name T481
Test name
Test status
Simulation time 2923276428 ps
CPU time 7.83 seconds
Started Jan 14 01:37:36 PM PST 24
Finished Jan 14 01:37:46 PM PST 24
Peak memory 200732 kb
Host smart-64ec4aa3-d53c-4a3b-ac1b-d3d8ce3d797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499112002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2499112002
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.438825183
Short name T448
Test name
Test status
Simulation time 5996692388 ps
CPU time 15.34 seconds
Started Jan 14 01:37:30 PM PST 24
Finished Jan 14 01:37:46 PM PST 24
Peak memory 200676 kb
Host smart-5dfac4f9-629f-4951-bf96-91233f424a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438825183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.438825183
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.4260388373
Short name T557
Test name
Test status
Simulation time 167712554824 ps
CPU time 97.61 seconds
Started Jan 14 01:37:35 PM PST 24
Finished Jan 14 01:39:14 PM PST 24
Peak memory 200888 kb
Host smart-4854da20-9e9b-4dcb-a0bb-1aed2334206d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260388373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.4260388373
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1512933689
Short name T130
Test name
Test status
Simulation time 629583897050 ps
CPU time 124.32 seconds
Started Jan 14 01:37:38 PM PST 24
Finished Jan 14 01:39:43 PM PST 24
Peak memory 209172 kb
Host smart-954a08d1-12fb-4548-a1ec-ef7859aebb2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512933689 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1512933689
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.391160761
Short name T157
Test name
Test status
Simulation time 361187225 ps
CPU time 0.81 seconds
Started Jan 14 01:37:50 PM PST 24
Finished Jan 14 01:37:52 PM PST 24
Peak memory 200744 kb
Host smart-3ef009dd-f4a9-46b9-9a15-6a3553ce880c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391160761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.391160761
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.765472526
Short name T257
Test name
Test status
Simulation time 168605846289 ps
CPU time 197.72 seconds
Started Jan 14 01:37:51 PM PST 24
Finished Jan 14 01:41:10 PM PST 24
Peak memory 200868 kb
Host smart-11eaeea0-f565-4bc9-b857-afbd44c5e3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765472526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.765472526
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3624352728
Short name T694
Test name
Test status
Simulation time 160617151988 ps
CPU time 340.45 seconds
Started Jan 14 01:37:44 PM PST 24
Finished Jan 14 01:43:25 PM PST 24
Peak memory 200808 kb
Host smart-5088a130-a442-4628-a06c-8e7fc2eceb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624352728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3624352728
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.908588367
Short name T797
Test name
Test status
Simulation time 496912164221 ps
CPU time 276.95 seconds
Started Jan 14 01:37:44 PM PST 24
Finished Jan 14 01:42:22 PM PST 24
Peak memory 200880 kb
Host smart-8056cff7-309b-44bf-9965-b1b5ddf49fed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=908588367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.908588367
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1203937567
Short name T665
Test name
Test status
Simulation time 328410483917 ps
CPU time 781 seconds
Started Jan 14 01:37:43 PM PST 24
Finished Jan 14 01:50:45 PM PST 24
Peak memory 200924 kb
Host smart-2e5503bf-1f31-4c97-9c46-0baad01e1185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203937567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1203937567
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.356672191
Short name T685
Test name
Test status
Simulation time 492826747737 ps
CPU time 517.92 seconds
Started Jan 14 01:37:36 PM PST 24
Finished Jan 14 01:46:16 PM PST 24
Peak memory 200888 kb
Host smart-8c71761e-2a5f-4b9c-b851-4c5f4218b36d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=356672191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.356672191
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1706364406
Short name T515
Test name
Test status
Simulation time 327512779609 ps
CPU time 682.25 seconds
Started Jan 14 01:37:50 PM PST 24
Finished Jan 14 01:49:14 PM PST 24
Peak memory 200872 kb
Host smart-3cfc2a48-5be8-4c26-bfad-4e6acd4fd356
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706364406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1706364406
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2544953752
Short name T816
Test name
Test status
Simulation time 66315116237 ps
CPU time 249.61 seconds
Started Jan 14 01:37:51 PM PST 24
Finished Jan 14 01:42:02 PM PST 24
Peak memory 201348 kb
Host smart-ee74d388-6fd5-453e-9ac8-04aefb61b211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544953752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2544953752
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2974236675
Short name T736
Test name
Test status
Simulation time 29531315339 ps
CPU time 60.93 seconds
Started Jan 14 01:37:48 PM PST 24
Finished Jan 14 01:38:50 PM PST 24
Peak memory 200748 kb
Host smart-206c949a-4851-49be-82bf-12871b24e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974236675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2974236675
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3370285983
Short name T574
Test name
Test status
Simulation time 3391641122 ps
CPU time 2.51 seconds
Started Jan 14 01:37:48 PM PST 24
Finished Jan 14 01:37:51 PM PST 24
Peak memory 200752 kb
Host smart-88e4fc8a-53a7-4c6b-b145-4ed24f662f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370285983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3370285983
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1575538244
Short name T708
Test name
Test status
Simulation time 6097094117 ps
CPU time 13.74 seconds
Started Jan 14 01:37:37 PM PST 24
Finished Jan 14 01:37:52 PM PST 24
Peak memory 200696 kb
Host smart-ed6628b5-d48a-4bcb-a31f-7f10609bbb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575538244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1575538244
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.490621449
Short name T636
Test name
Test status
Simulation time 36840545715 ps
CPU time 46.96 seconds
Started Jan 14 01:37:49 PM PST 24
Finished Jan 14 01:38:37 PM PST 24
Peak memory 200824 kb
Host smart-1c1cc4d8-6668-4b61-8f67-9b621afba151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490621449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
490621449
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3493666043
Short name T718
Test name
Test status
Simulation time 74067980782 ps
CPU time 159.6 seconds
Started Jan 14 01:37:47 PM PST 24
Finished Jan 14 01:40:28 PM PST 24
Peak memory 209636 kb
Host smart-97fece4c-1a75-4a30-8181-1f0acd5eda9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493666043 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3493666043
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.274019419
Short name T804
Test name
Test status
Simulation time 400040797 ps
CPU time 1.52 seconds
Started Jan 14 01:38:02 PM PST 24
Finished Jan 14 01:38:04 PM PST 24
Peak memory 200672 kb
Host smart-485cde41-bab5-44c1-b4ae-6bbce136094b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274019419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.274019419
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.44592164
Short name T746
Test name
Test status
Simulation time 334273704719 ps
CPU time 100.8 seconds
Started Jan 14 01:37:53 PM PST 24
Finished Jan 14 01:39:35 PM PST 24
Peak memory 200880 kb
Host smart-e103dfb9-96f4-4d17-8f59-904cdff81fe2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44592164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gatin
g.44592164
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3044149649
Short name T291
Test name
Test status
Simulation time 160471296137 ps
CPU time 73.83 seconds
Started Jan 14 01:37:51 PM PST 24
Finished Jan 14 01:39:06 PM PST 24
Peak memory 200948 kb
Host smart-9588bf81-a219-41d4-ae14-a0e85f31a542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044149649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3044149649
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2407551388
Short name T720
Test name
Test status
Simulation time 165487749185 ps
CPU time 392.78 seconds
Started Jan 14 01:37:49 PM PST 24
Finished Jan 14 01:44:23 PM PST 24
Peak memory 200932 kb
Host smart-57bfc97e-c944-4495-bfb8-a28d857c1591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407551388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2407551388
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3391742038
Short name T659
Test name
Test status
Simulation time 330128099171 ps
CPU time 239.72 seconds
Started Jan 14 01:37:56 PM PST 24
Finished Jan 14 01:41:56 PM PST 24
Peak memory 200860 kb
Host smart-dcf2bea9-4b3a-4e74-9097-4669aad4c66a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391742038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3391742038
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.759490552
Short name T119
Test name
Test status
Simulation time 496627767904 ps
CPU time 1145.31 seconds
Started Jan 14 01:37:46 PM PST 24
Finished Jan 14 01:56:53 PM PST 24
Peak memory 201008 kb
Host smart-10e00013-7545-4e6a-9d21-98f4d1f64788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759490552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.759490552
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2367434777
Short name T464
Test name
Test status
Simulation time 495020687622 ps
CPU time 1179 seconds
Started Jan 14 01:37:49 PM PST 24
Finished Jan 14 01:57:29 PM PST 24
Peak memory 200972 kb
Host smart-1c94746d-eee0-499e-bdc9-543169f233eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367434777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2367434777
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3628734034
Short name T709
Test name
Test status
Simulation time 492974667869 ps
CPU time 1156.19 seconds
Started Jan 14 01:37:52 PM PST 24
Finished Jan 14 01:57:09 PM PST 24
Peak memory 200888 kb
Host smart-c8086a6a-8b51-487d-8dbc-744bdfa2146a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628734034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3628734034
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.651101466
Short name T800
Test name
Test status
Simulation time 159430626373 ps
CPU time 372.26 seconds
Started Jan 14 01:37:54 PM PST 24
Finished Jan 14 01:44:07 PM PST 24
Peak memory 200872 kb
Host smart-57e9d6e0-d6a0-4051-95b2-b0282d8c34b3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651101466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.651101466
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2444603435
Short name T782
Test name
Test status
Simulation time 110612351534 ps
CPU time 585.36 seconds
Started Jan 14 01:37:53 PM PST 24
Finished Jan 14 01:47:39 PM PST 24
Peak memory 201312 kb
Host smart-9ef1eb5a-53e9-4c21-bff1-4b004bed148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444603435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2444603435
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3757296456
Short name T477
Test name
Test status
Simulation time 27820597640 ps
CPU time 44.23 seconds
Started Jan 14 01:37:53 PM PST 24
Finished Jan 14 01:38:38 PM PST 24
Peak memory 200744 kb
Host smart-05cf80ac-110e-4af4-8cef-11996cfa6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757296456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3757296456
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2151446982
Short name T445
Test name
Test status
Simulation time 3223792271 ps
CPU time 1.26 seconds
Started Jan 14 01:37:56 PM PST 24
Finished Jan 14 01:37:58 PM PST 24
Peak memory 200668 kb
Host smart-a9f5b9b0-1847-43e2-95e7-514504e88fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151446982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2151446982
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1849374639
Short name T511
Test name
Test status
Simulation time 6084781458 ps
CPU time 4.5 seconds
Started Jan 14 01:37:49 PM PST 24
Finished Jan 14 01:37:55 PM PST 24
Peak memory 200760 kb
Host smart-e4c628c1-d19e-4ef4-a003-1936fa6a2b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849374639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1849374639
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2279413644
Short name T304
Test name
Test status
Simulation time 497797258171 ps
CPU time 611.18 seconds
Started Jan 14 01:38:01 PM PST 24
Finished Jan 14 01:48:13 PM PST 24
Peak memory 200980 kb
Host smart-47f7018c-3037-48c3-ba2b-5ff0b53ae3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279413644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2279413644
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.182710967
Short name T854
Test name
Test status
Simulation time 360838962 ps
CPU time 1.41 seconds
Started Jan 14 01:38:13 PM PST 24
Finished Jan 14 01:38:15 PM PST 24
Peak memory 200596 kb
Host smart-c20b6921-374f-4a20-b7b5-edc3cc36d3de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182710967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.182710967
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.266790842
Short name T241
Test name
Test status
Simulation time 492074954510 ps
CPU time 557.77 seconds
Started Jan 14 01:38:13 PM PST 24
Finished Jan 14 01:47:31 PM PST 24
Peak memory 200792 kb
Host smart-034292ba-dce5-47d7-9b24-57c7c7b5f3ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266790842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.266790842
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3619816214
Short name T693
Test name
Test status
Simulation time 318652346520 ps
CPU time 698.14 seconds
Started Jan 14 01:38:10 PM PST 24
Finished Jan 14 01:49:50 PM PST 24
Peak memory 201012 kb
Host smart-2ffe4672-67d8-44a8-adc0-a3805e099619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619816214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3619816214
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3730684966
Short name T558
Test name
Test status
Simulation time 160161335491 ps
CPU time 30.95 seconds
Started Jan 14 01:38:01 PM PST 24
Finished Jan 14 01:38:33 PM PST 24
Peak memory 200800 kb
Host smart-06dcee83-8a99-43b1-994b-dbdbced779f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730684966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3730684966
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1306947810
Short name T553
Test name
Test status
Simulation time 330474329226 ps
CPU time 73.32 seconds
Started Jan 14 01:38:00 PM PST 24
Finished Jan 14 01:39:14 PM PST 24
Peak memory 200892 kb
Host smart-2b0d8c25-1da0-4ad2-81ef-3c5e96350f56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306947810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1306947810
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3767410758
Short name T617
Test name
Test status
Simulation time 488930844931 ps
CPU time 95.98 seconds
Started Jan 14 01:38:00 PM PST 24
Finished Jan 14 01:39:37 PM PST 24
Peak memory 200896 kb
Host smart-4c0db813-5355-4cce-811c-ff5e7e76ffd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767410758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3767410758
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1333189946
Short name T270
Test name
Test status
Simulation time 325610644877 ps
CPU time 346.39 seconds
Started Jan 14 01:38:02 PM PST 24
Finished Jan 14 01:43:49 PM PST 24
Peak memory 200952 kb
Host smart-96d57e6a-30ec-47a0-985e-4bbcd1ba21f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333189946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1333189946
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2639571920
Short name T470
Test name
Test status
Simulation time 500323946102 ps
CPU time 1197.66 seconds
Started Jan 14 01:38:00 PM PST 24
Finished Jan 14 01:57:59 PM PST 24
Peak memory 200832 kb
Host smart-268fb58b-87c4-42cb-8cdc-8df47302d342
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639571920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2639571920
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.655704855
Short name T828
Test name
Test status
Simulation time 93382368632 ps
CPU time 342.7 seconds
Started Jan 14 01:38:12 PM PST 24
Finished Jan 14 01:43:55 PM PST 24
Peak memory 201348 kb
Host smart-5770fdb2-5911-45ea-8a26-8ae776fdf062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655704855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.655704855
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3476592910
Short name T486
Test name
Test status
Simulation time 37657831414 ps
CPU time 41.85 seconds
Started Jan 14 01:38:13 PM PST 24
Finished Jan 14 01:38:55 PM PST 24
Peak memory 200704 kb
Host smart-599f891c-6ab1-41d3-b14f-97cdf241d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476592910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3476592910
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3532768465
Short name T462
Test name
Test status
Simulation time 3251056753 ps
CPU time 2.62 seconds
Started Jan 14 01:38:10 PM PST 24
Finished Jan 14 01:38:13 PM PST 24
Peak memory 200760 kb
Host smart-2e3cea6f-c6c1-457c-a849-e591a45f38ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532768465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3532768465
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3264697220
Short name T647
Test name
Test status
Simulation time 5641436101 ps
CPU time 6.82 seconds
Started Jan 14 01:38:03 PM PST 24
Finished Jan 14 01:38:11 PM PST 24
Peak memory 200704 kb
Host smart-9d2a0775-8e33-4550-b528-5e865698fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264697220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3264697220
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1258295903
Short name T278
Test name
Test status
Simulation time 111423768083 ps
CPU time 121.47 seconds
Started Jan 14 01:38:11 PM PST 24
Finished Jan 14 01:40:13 PM PST 24
Peak memory 209176 kb
Host smart-e514fb6b-e273-4822-9699-6ec01d61be9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258295903 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1258295903
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.573071295
Short name T586
Test name
Test status
Simulation time 389248234 ps
CPU time 1.5 seconds
Started Jan 14 01:38:18 PM PST 24
Finished Jan 14 01:38:21 PM PST 24
Peak memory 200368 kb
Host smart-5b55d2d9-6e55-45cd-960b-8716bf622496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573071295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.573071295
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.542474645
Short name T806
Test name
Test status
Simulation time 540217254736 ps
CPU time 1301.26 seconds
Started Jan 14 01:38:15 PM PST 24
Finished Jan 14 01:59:57 PM PST 24
Peak memory 201008 kb
Host smart-a9f7b1c9-8f21-42c5-99ee-e89b68178db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542474645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.542474645
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1836415282
Short name T313
Test name
Test status
Simulation time 334308701049 ps
CPU time 439.93 seconds
Started Jan 14 01:38:12 PM PST 24
Finished Jan 14 01:45:33 PM PST 24
Peak memory 200912 kb
Host smart-efb3dc14-91df-405b-a33d-ff58153d6cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836415282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1836415282
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3070130332
Short name T54
Test name
Test status
Simulation time 326293112138 ps
CPU time 84.83 seconds
Started Jan 14 01:38:14 PM PST 24
Finished Jan 14 01:39:39 PM PST 24
Peak memory 200936 kb
Host smart-c6f35e3c-49fd-47a2-9b28-19aae734a8c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070130332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3070130332
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.4023914010
Short name T253
Test name
Test status
Simulation time 161031569454 ps
CPU time 196.47 seconds
Started Jan 14 01:38:11 PM PST 24
Finished Jan 14 01:41:28 PM PST 24
Peak memory 200820 kb
Host smart-fe30f68c-a98d-4acf-8412-9742e64bc3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023914010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.4023914010
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2738762354
Short name T444
Test name
Test status
Simulation time 493727751509 ps
CPU time 319.36 seconds
Started Jan 14 01:38:10 PM PST 24
Finished Jan 14 01:43:31 PM PST 24
Peak memory 200848 kb
Host smart-27b9a4cd-09f1-44a7-a4ac-302f34947443
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738762354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2738762354
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1601551505
Short name T190
Test name
Test status
Simulation time 340647078570 ps
CPU time 89.72 seconds
Started Jan 14 01:38:16 PM PST 24
Finished Jan 14 01:39:46 PM PST 24
Peak memory 201024 kb
Host smart-c85713fe-57ea-431e-be67-a324285ddebb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601551505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1601551505
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1850029511
Short name T786
Test name
Test status
Simulation time 322953100248 ps
CPU time 57.18 seconds
Started Jan 14 01:38:11 PM PST 24
Finished Jan 14 01:39:09 PM PST 24
Peak memory 200848 kb
Host smart-451c9f7f-cd38-43d7-a705-50b963349bf9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850029511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1850029511
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.152103554
Short name T835
Test name
Test status
Simulation time 102141415075 ps
CPU time 304.26 seconds
Started Jan 14 01:38:17 PM PST 24
Finished Jan 14 01:43:22 PM PST 24
Peak memory 201388 kb
Host smart-8036597d-9af0-4a7f-88a7-5b22219d4b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152103554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.152103554
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2508083362
Short name T420
Test name
Test status
Simulation time 28916078693 ps
CPU time 34.26 seconds
Started Jan 14 01:38:18 PM PST 24
Finished Jan 14 01:38:53 PM PST 24
Peak memory 200712 kb
Host smart-5b30c08d-2238-463f-9ab6-1dafb60b6aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508083362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2508083362
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1048620479
Short name T538
Test name
Test status
Simulation time 3915275819 ps
CPU time 10.25 seconds
Started Jan 14 01:38:18 PM PST 24
Finished Jan 14 01:38:29 PM PST 24
Peak memory 200668 kb
Host smart-c2c25963-bc3e-424d-88db-60fc509e0720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048620479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1048620479
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3597635757
Short name T776
Test name
Test status
Simulation time 5764877532 ps
CPU time 3.85 seconds
Started Jan 14 01:38:19 PM PST 24
Finished Jan 14 01:38:24 PM PST 24
Peak memory 200740 kb
Host smart-1f4404d3-a46c-4695-ab59-576525b88b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597635757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3597635757
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1515263704
Short name T722
Test name
Test status
Simulation time 161939873873 ps
CPU time 112.33 seconds
Started Jan 14 01:38:20 PM PST 24
Finished Jan 14 01:40:12 PM PST 24
Peak memory 200944 kb
Host smart-18c90b4c-95b9-40bf-819f-0f3ac71fa089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515263704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1515263704
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3297831075
Short name T234
Test name
Test status
Simulation time 60498293494 ps
CPU time 49.07 seconds
Started Jan 14 01:38:17 PM PST 24
Finished Jan 14 01:39:07 PM PST 24
Peak memory 209156 kb
Host smart-cb601fdc-f433-485a-af6d-4d219cde750a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297831075 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3297831075
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.18588475
Short name T593
Test name
Test status
Simulation time 466660918 ps
CPU time 1.12 seconds
Started Jan 14 01:33:34 PM PST 24
Finished Jan 14 01:33:35 PM PST 24
Peak memory 200540 kb
Host smart-30f7809c-5e22-4d70-8b07-fca944a5cd3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18588475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.18588475
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3704263372
Short name T139
Test name
Test status
Simulation time 491505857822 ps
CPU time 309.16 seconds
Started Jan 14 01:35:18 PM PST 24
Finished Jan 14 01:40:28 PM PST 24
Peak memory 200836 kb
Host smart-4529c571-2571-4f32-8c2c-e263749d565e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704263372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3704263372
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2692178249
Short name T55
Test name
Test status
Simulation time 164848827499 ps
CPU time 194.56 seconds
Started Jan 14 01:33:42 PM PST 24
Finished Jan 14 01:36:57 PM PST 24
Peak memory 200904 kb
Host smart-9ed09f7a-0c5e-46ff-858f-b4d698dab708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692178249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2692178249
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3451989123
Short name T301
Test name
Test status
Simulation time 167122750972 ps
CPU time 367.43 seconds
Started Jan 14 01:33:40 PM PST 24
Finished Jan 14 01:39:48 PM PST 24
Peak memory 200968 kb
Host smart-3048a510-0472-4b19-888e-7b4009434c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451989123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3451989123
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2827088848
Short name T536
Test name
Test status
Simulation time 329733311803 ps
CPU time 226.31 seconds
Started Jan 14 01:33:47 PM PST 24
Finished Jan 14 01:37:34 PM PST 24
Peak memory 200780 kb
Host smart-dd59e0ce-61c1-44d0-a45a-bc7855ef4100
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827088848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2827088848
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.279105332
Short name T352
Test name
Test status
Simulation time 491148270914 ps
CPU time 1122.38 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:52:27 PM PST 24
Peak memory 200776 kb
Host smart-2f9bad61-33d1-4c40-b549-09e4dd63c66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279105332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.279105332
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1673852536
Short name T492
Test name
Test status
Simulation time 327221723966 ps
CPU time 729.83 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:45:55 PM PST 24
Peak memory 200884 kb
Host smart-7545d65e-f0f1-47e0-bd60-6afabf39c552
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673852536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1673852536
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3189909192
Short name T692
Test name
Test status
Simulation time 331909120848 ps
CPU time 819.37 seconds
Started Jan 14 01:33:43 PM PST 24
Finished Jan 14 01:47:23 PM PST 24
Peak memory 201016 kb
Host smart-99f19867-7ba7-45f7-8231-f78c1d8a40e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189909192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3189909192
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2065417835
Short name T473
Test name
Test status
Simulation time 165579203423 ps
CPU time 164.11 seconds
Started Jan 14 01:33:49 PM PST 24
Finished Jan 14 01:36:34 PM PST 24
Peak memory 200896 kb
Host smart-58028d06-f9c2-416c-bd09-d826b7f82577
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065417835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2065417835
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4016572992
Short name T753
Test name
Test status
Simulation time 40684533353 ps
CPU time 99.3 seconds
Started Jan 14 01:33:38 PM PST 24
Finished Jan 14 01:35:17 PM PST 24
Peak memory 200760 kb
Host smart-5d3d10fe-007f-499e-b62c-2d5046ae5eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016572992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4016572992
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3164685216
Short name T681
Test name
Test status
Simulation time 4926065842 ps
CPU time 2.28 seconds
Started Jan 14 01:33:50 PM PST 24
Finished Jan 14 01:33:53 PM PST 24
Peak memory 200756 kb
Host smart-7d4431d2-9702-42a3-9b65-f5943fada8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164685216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3164685216
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3944693628
Short name T45
Test name
Test status
Simulation time 8187858645 ps
CPU time 19.55 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:34:05 PM PST 24
Peak memory 217040 kb
Host smart-8556e46c-448f-49c2-b83e-4138faecbd2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944693628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3944693628
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1227489810
Short name T530
Test name
Test status
Simulation time 6095668102 ps
CPU time 3.46 seconds
Started Jan 14 01:33:35 PM PST 24
Finished Jan 14 01:33:39 PM PST 24
Peak memory 200644 kb
Host smart-9d874e58-ce35-4d38-8598-b7a5e56961dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227489810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1227489810
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2537000378
Short name T716
Test name
Test status
Simulation time 520901722773 ps
CPU time 330.37 seconds
Started Jan 14 01:33:57 PM PST 24
Finished Jan 14 01:39:29 PM PST 24
Peak memory 200876 kb
Host smart-c4904ac5-9e35-4122-9f51-00b33d50c14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537000378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2537000378
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3120452225
Short name T339
Test name
Test status
Simulation time 1069310699210 ps
CPU time 510.33 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:42:27 PM PST 24
Peak memory 209592 kb
Host smart-f298ae9e-3d55-4633-91b6-0cb87c9609a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120452225 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3120452225
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3641630362
Short name T454
Test name
Test status
Simulation time 549490663 ps
CPU time 0.76 seconds
Started Jan 14 01:38:36 PM PST 24
Finished Jan 14 01:38:38 PM PST 24
Peak memory 200652 kb
Host smart-2145b9bc-53bf-4e1b-b267-3d64f15da682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641630362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3641630362
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.183402238
Short name T131
Test name
Test status
Simulation time 165332715115 ps
CPU time 91.73 seconds
Started Jan 14 01:38:29 PM PST 24
Finished Jan 14 01:40:01 PM PST 24
Peak memory 200972 kb
Host smart-37121bf8-191a-4944-b1f8-3c4eff5c92cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183402238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.183402238
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1204647375
Short name T769
Test name
Test status
Simulation time 164680421114 ps
CPU time 101.02 seconds
Started Jan 14 01:38:20 PM PST 24
Finished Jan 14 01:40:01 PM PST 24
Peak memory 200968 kb
Host smart-ef31b2ff-7283-4e3e-831d-c35749a1deb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204647375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1204647375
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1302278312
Short name T639
Test name
Test status
Simulation time 166617499823 ps
CPU time 359.6 seconds
Started Jan 14 01:38:20 PM PST 24
Finished Jan 14 01:44:21 PM PST 24
Peak memory 200944 kb
Host smart-674ed220-4b40-409c-814a-94fbb0a41d88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302278312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1302278312
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.799282332
Short name T726
Test name
Test status
Simulation time 497015666309 ps
CPU time 322.17 seconds
Started Jan 14 01:38:20 PM PST 24
Finished Jan 14 01:43:42 PM PST 24
Peak memory 200864 kb
Host smart-0ca1e1b5-2c43-4653-8339-007191259078
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=799282332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.799282332
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4037037419
Short name T683
Test name
Test status
Simulation time 165219955250 ps
CPU time 98.69 seconds
Started Jan 14 01:38:32 PM PST 24
Finished Jan 14 01:40:11 PM PST 24
Peak memory 200856 kb
Host smart-c7811bb9-fa36-467c-b3ec-eba0c695dc1a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037037419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4037037419
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1322221329
Short name T453
Test name
Test status
Simulation time 98575704808 ps
CPU time 399.21 seconds
Started Jan 14 01:38:29 PM PST 24
Finished Jan 14 01:45:09 PM PST 24
Peak memory 201308 kb
Host smart-b3dfcf9b-ac00-4762-9093-7f79f084e549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322221329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1322221329
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2764849814
Short name T472
Test name
Test status
Simulation time 41075445848 ps
CPU time 25.96 seconds
Started Jan 14 01:38:28 PM PST 24
Finished Jan 14 01:38:55 PM PST 24
Peak memory 200768 kb
Host smart-cf57e702-2093-43fc-b75d-429e9ecbf63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764849814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2764849814
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.313582112
Short name T449
Test name
Test status
Simulation time 3109220334 ps
CPU time 4.37 seconds
Started Jan 14 01:38:29 PM PST 24
Finished Jan 14 01:38:34 PM PST 24
Peak memory 200772 kb
Host smart-8261d179-401e-426e-b3f4-611fce2bea91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313582112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.313582112
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3932592114
Short name T795
Test name
Test status
Simulation time 5828016970 ps
CPU time 11.15 seconds
Started Jan 14 01:38:19 PM PST 24
Finished Jan 14 01:38:31 PM PST 24
Peak memory 200680 kb
Host smart-53a23d16-89a1-4daa-bbac-ce04c5839a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932592114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3932592114
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2882954652
Short name T513
Test name
Test status
Simulation time 6336041229 ps
CPU time 14.91 seconds
Started Jan 14 01:38:32 PM PST 24
Finished Jan 14 01:38:47 PM PST 24
Peak memory 200700 kb
Host smart-22d1a619-5e76-46e9-933b-0ede5d55b5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882954652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2882954652
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2037517215
Short name T643
Test name
Test status
Simulation time 589337048699 ps
CPU time 144.02 seconds
Started Jan 14 01:38:31 PM PST 24
Finished Jan 14 01:40:55 PM PST 24
Peak memory 209120 kb
Host smart-bb12c824-b235-4679-9875-2305d155b587
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037517215 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2037517215
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1326364438
Short name T821
Test name
Test status
Simulation time 412203432 ps
CPU time 1.48 seconds
Started Jan 14 01:38:46 PM PST 24
Finished Jan 14 01:38:48 PM PST 24
Peak memory 200676 kb
Host smart-7eb18f2e-63bc-47fe-90bb-ab9ea0a630d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326364438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1326364438
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1700438111
Short name T866
Test name
Test status
Simulation time 485534680993 ps
CPU time 290.61 seconds
Started Jan 14 01:38:37 PM PST 24
Finished Jan 14 01:43:28 PM PST 24
Peak memory 201024 kb
Host smart-f7238103-074b-4449-9619-f2e6a5ce7a2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700438111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1700438111
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2527135756
Short name T734
Test name
Test status
Simulation time 161946797211 ps
CPU time 97.76 seconds
Started Jan 14 01:38:33 PM PST 24
Finished Jan 14 01:40:11 PM PST 24
Peak memory 200960 kb
Host smart-9ae930ef-b960-4855-9941-9cf51073edc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527135756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2527135756
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2904295655
Short name T331
Test name
Test status
Simulation time 495577779695 ps
CPU time 1011.31 seconds
Started Jan 14 01:38:34 PM PST 24
Finished Jan 14 01:55:27 PM PST 24
Peak memory 200880 kb
Host smart-df47fc5f-c86e-4057-a9db-fb4f1afb0127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904295655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2904295655
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3409526593
Short name T739
Test name
Test status
Simulation time 170683024478 ps
CPU time 98.68 seconds
Started Jan 14 01:38:34 PM PST 24
Finished Jan 14 01:40:13 PM PST 24
Peak memory 200868 kb
Host smart-b89cbc4b-b69e-4c55-8f82-caf7798dfd67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409526593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3409526593
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2932987247
Short name T353
Test name
Test status
Simulation time 504893098427 ps
CPU time 1069.15 seconds
Started Jan 14 01:38:34 PM PST 24
Finished Jan 14 01:56:25 PM PST 24
Peak memory 200980 kb
Host smart-284e00a7-84d0-4caf-ab37-6b24258f7f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932987247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2932987247
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3171526447
Short name T566
Test name
Test status
Simulation time 492786394337 ps
CPU time 65.58 seconds
Started Jan 14 01:38:33 PM PST 24
Finished Jan 14 01:39:39 PM PST 24
Peak memory 200860 kb
Host smart-2c0c6c85-85ed-46b2-8631-31d60aa4fd61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171526447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3171526447
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2193246211
Short name T299
Test name
Test status
Simulation time 500211633338 ps
CPU time 307.38 seconds
Started Jan 14 01:38:36 PM PST 24
Finished Jan 14 01:43:44 PM PST 24
Peak memory 200852 kb
Host smart-95e67601-0f02-4dba-be4e-b4c61b354ff0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193246211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2193246211
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2371560993
Short name T644
Test name
Test status
Simulation time 165218873464 ps
CPU time 97.48 seconds
Started Jan 14 01:38:35 PM PST 24
Finished Jan 14 01:40:13 PM PST 24
Peak memory 200888 kb
Host smart-c4071536-7b78-4fd2-a4f4-8f2bee3da1ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371560993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2371560993
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1963459111
Short name T360
Test name
Test status
Simulation time 115158327768 ps
CPU time 399.91 seconds
Started Jan 14 01:38:34 PM PST 24
Finished Jan 14 01:45:15 PM PST 24
Peak memory 201424 kb
Host smart-092399b3-31c1-43ac-8329-ebbdb7be9d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963459111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1963459111
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1955968894
Short name T539
Test name
Test status
Simulation time 22591702809 ps
CPU time 25.46 seconds
Started Jan 14 01:38:33 PM PST 24
Finished Jan 14 01:38:59 PM PST 24
Peak memory 200748 kb
Host smart-9fdeb916-f117-49c9-8a3b-46fe00beeac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955968894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1955968894
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2369346818
Short name T767
Test name
Test status
Simulation time 3048877582 ps
CPU time 3.97 seconds
Started Jan 14 01:38:34 PM PST 24
Finished Jan 14 01:38:38 PM PST 24
Peak memory 200724 kb
Host smart-30cc8376-ed06-4d8f-b690-31cff4c37e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369346818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2369346818
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1521363928
Short name T430
Test name
Test status
Simulation time 5979695928 ps
CPU time 5.15 seconds
Started Jan 14 01:38:35 PM PST 24
Finished Jan 14 01:38:41 PM PST 24
Peak memory 200660 kb
Host smart-245de864-e18c-4a2e-a508-f51af24dcf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521363928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1521363928
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3085701601
Short name T525
Test name
Test status
Simulation time 67523304660 ps
CPU time 145.46 seconds
Started Jan 14 01:38:47 PM PST 24
Finished Jan 14 01:41:13 PM PST 24
Peak memory 200672 kb
Host smart-ff6b5de5-5c05-4e70-8c2d-d4705068b6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085701601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3085701601
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2248988226
Short name T664
Test name
Test status
Simulation time 31599256858 ps
CPU time 116.63 seconds
Started Jan 14 01:38:34 PM PST 24
Finished Jan 14 01:40:32 PM PST 24
Peak memory 209636 kb
Host smart-7a1340b2-1956-4879-b529-b13c13bcf40b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248988226 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2248988226
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2603422568
Short name T784
Test name
Test status
Simulation time 427868999 ps
CPU time 1.53 seconds
Started Jan 14 01:38:52 PM PST 24
Finished Jan 14 01:38:54 PM PST 24
Peak memory 200676 kb
Host smart-2877281f-4d5a-4265-ad4b-a43196275b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603422568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2603422568
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2984223957
Short name T255
Test name
Test status
Simulation time 181839840099 ps
CPU time 51.84 seconds
Started Jan 14 01:38:46 PM PST 24
Finished Jan 14 01:39:38 PM PST 24
Peak memory 200944 kb
Host smart-1878a18c-a23d-462c-854e-122fe19dc5e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984223957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2984223957
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2022284588
Short name T729
Test name
Test status
Simulation time 328510625635 ps
CPU time 196.69 seconds
Started Jan 14 01:38:44 PM PST 24
Finished Jan 14 01:42:02 PM PST 24
Peak memory 200936 kb
Host smart-027b09c2-2dd5-4635-baef-4a38b0876238
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022284588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2022284588
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3754865005
Short name T719
Test name
Test status
Simulation time 321086345417 ps
CPU time 48.66 seconds
Started Jan 14 01:38:49 PM PST 24
Finished Jan 14 01:39:38 PM PST 24
Peak memory 200852 kb
Host smart-2449464b-a5b1-43b4-9efa-575df92e2a10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754865005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3754865005
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.4110477507
Short name T198
Test name
Test status
Simulation time 367291825534 ps
CPU time 205.44 seconds
Started Jan 14 01:38:49 PM PST 24
Finished Jan 14 01:42:15 PM PST 24
Peak memory 200928 kb
Host smart-9bb1f60f-47eb-4130-8344-2b69e6b20135
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110477507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.4110477507
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.4175140427
Short name T443
Test name
Test status
Simulation time 164572445630 ps
CPU time 127.35 seconds
Started Jan 14 01:38:47 PM PST 24
Finished Jan 14 01:40:55 PM PST 24
Peak memory 200924 kb
Host smart-a9485bc7-b14f-4b74-bf07-c7e4fb83a7bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175140427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.4175140427
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2011785119
Short name T770
Test name
Test status
Simulation time 119176913790 ps
CPU time 613.59 seconds
Started Jan 14 01:38:47 PM PST 24
Finished Jan 14 01:49:02 PM PST 24
Peak memory 201396 kb
Host smart-4c85a69a-9a97-468a-911b-5e4082f61fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011785119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2011785119
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2869184085
Short name T507
Test name
Test status
Simulation time 41053098436 ps
CPU time 25.73 seconds
Started Jan 14 01:38:50 PM PST 24
Finished Jan 14 01:39:16 PM PST 24
Peak memory 200744 kb
Host smart-22c36493-a42c-4af4-a0af-c7ab50219fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869184085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2869184085
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3326117055
Short name T510
Test name
Test status
Simulation time 3197952151 ps
CPU time 8.55 seconds
Started Jan 14 01:38:45 PM PST 24
Finished Jan 14 01:38:54 PM PST 24
Peak memory 200704 kb
Host smart-4a21d9ef-ce2e-4c66-b4c2-64acf304f9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326117055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3326117055
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3382821466
Short name T711
Test name
Test status
Simulation time 5816469791 ps
CPU time 14.53 seconds
Started Jan 14 01:38:46 PM PST 24
Finished Jan 14 01:39:02 PM PST 24
Peak memory 200692 kb
Host smart-596b31cd-226a-4f33-9671-5035779a21df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382821466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3382821466
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.698891528
Short name T348
Test name
Test status
Simulation time 460296590496 ps
CPU time 384.16 seconds
Started Jan 14 01:38:51 PM PST 24
Finished Jan 14 01:45:16 PM PST 24
Peak memory 211072 kb
Host smart-43251d0e-5549-4005-a42c-62bc22157d0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698891528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
698891528
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3070129668
Short name T351
Test name
Test status
Simulation time 38683684787 ps
CPU time 34.41 seconds
Started Jan 14 01:38:47 PM PST 24
Finished Jan 14 01:39:22 PM PST 24
Peak memory 209284 kb
Host smart-faea18bd-e019-47d3-ae48-4db8c3f8e86d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070129668 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3070129668
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2512788897
Short name T478
Test name
Test status
Simulation time 333248844 ps
CPU time 0.7 seconds
Started Jan 14 01:38:59 PM PST 24
Finished Jan 14 01:39:00 PM PST 24
Peak memory 200656 kb
Host smart-3d5589c9-08fb-4c02-b120-76455b7974a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512788897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2512788897
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.361238522
Short name T698
Test name
Test status
Simulation time 167662345503 ps
CPU time 100.73 seconds
Started Jan 14 01:38:51 PM PST 24
Finished Jan 14 01:40:32 PM PST 24
Peak memory 200816 kb
Host smart-8e59a249-7f22-4ff3-a49f-7d14e70b59c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361238522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.361238522
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3298772999
Short name T773
Test name
Test status
Simulation time 494879808136 ps
CPU time 645.54 seconds
Started Jan 14 01:38:49 PM PST 24
Finished Jan 14 01:49:35 PM PST 24
Peak memory 200964 kb
Host smart-670dbf14-af83-461c-ab65-38c7ad35229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298772999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3298772999
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.983442754
Short name T846
Test name
Test status
Simulation time 167882220839 ps
CPU time 60.1 seconds
Started Jan 14 01:38:53 PM PST 24
Finished Jan 14 01:39:54 PM PST 24
Peak memory 200868 kb
Host smart-8115d2b9-76d4-47e3-bd20-efe2820360bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=983442754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.983442754
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3968886004
Short name T149
Test name
Test status
Simulation time 487638369389 ps
CPU time 300.68 seconds
Started Jan 14 01:38:52 PM PST 24
Finished Jan 14 01:43:54 PM PST 24
Peak memory 200908 kb
Host smart-6b0012db-2d95-4b23-a667-af29cde70969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968886004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3968886004
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3012939947
Short name T657
Test name
Test status
Simulation time 490551237394 ps
CPU time 1117.81 seconds
Started Jan 14 01:38:49 PM PST 24
Finished Jan 14 01:57:28 PM PST 24
Peak memory 200824 kb
Host smart-f6cd6c33-e407-4ba9-86eb-736699e1d93b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012939947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3012939947
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2655334696
Short name T249
Test name
Test status
Simulation time 488997235950 ps
CPU time 512.2 seconds
Started Jan 14 01:38:49 PM PST 24
Finished Jan 14 01:47:22 PM PST 24
Peak memory 200752 kb
Host smart-7266cd6d-a54c-4c1e-9ea2-e005c55a0857
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655334696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2655334696
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.35752019
Short name T601
Test name
Test status
Simulation time 164843943804 ps
CPU time 198.31 seconds
Started Jan 14 01:38:51 PM PST 24
Finished Jan 14 01:42:10 PM PST 24
Peak memory 200892 kb
Host smart-17733eee-1279-4d71-8ca0-98d75ad3a963
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35752019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
dc_ctrl_filters_wakeup_fixed.35752019
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3070691467
Short name T116
Test name
Test status
Simulation time 126457836056 ps
CPU time 525.2 seconds
Started Jan 14 01:38:58 PM PST 24
Finished Jan 14 01:47:44 PM PST 24
Peak memory 201292 kb
Host smart-0b782ead-d36b-4e6e-be06-13637b7b492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070691467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3070691467
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4188668765
Short name T57
Test name
Test status
Simulation time 26030571476 ps
CPU time 29.8 seconds
Started Jan 14 01:39:09 PM PST 24
Finished Jan 14 01:39:40 PM PST 24
Peak memory 200660 kb
Host smart-63daefc1-451b-4273-9347-4dbdc451d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188668765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.4188668765
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.857470738
Short name T765
Test name
Test status
Simulation time 4412682585 ps
CPU time 1.29 seconds
Started Jan 14 01:38:53 PM PST 24
Finished Jan 14 01:38:55 PM PST 24
Peak memory 200740 kb
Host smart-de80f86b-d052-409d-bf11-c68d7a257384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857470738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.857470738
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2096998402
Short name T143
Test name
Test status
Simulation time 5992371106 ps
CPU time 4.27 seconds
Started Jan 14 01:38:48 PM PST 24
Finished Jan 14 01:38:53 PM PST 24
Peak memory 200740 kb
Host smart-3586faca-7e02-41ee-873b-916d2e9f4821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096998402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2096998402
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2535864755
Short name T868
Test name
Test status
Simulation time 87147187996 ps
CPU time 116.41 seconds
Started Jan 14 01:39:00 PM PST 24
Finished Jan 14 01:40:57 PM PST 24
Peak memory 209640 kb
Host smart-47914e29-56a6-4135-a424-29ab2b135d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535864755 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2535864755
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.580181948
Short name T170
Test name
Test status
Simulation time 532031960 ps
CPU time 0.86 seconds
Started Jan 14 01:39:07 PM PST 24
Finished Jan 14 01:39:08 PM PST 24
Peak memory 200656 kb
Host smart-b8867a73-a73d-4d3d-b628-78a93a8707b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580181948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.580181948
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2611531166
Short name T332
Test name
Test status
Simulation time 488485874627 ps
CPU time 540.39 seconds
Started Jan 14 01:39:09 PM PST 24
Finished Jan 14 01:48:10 PM PST 24
Peak memory 200380 kb
Host smart-2bd80b9b-3e07-48fc-98a2-218f85528678
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611531166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2611531166
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3642174562
Short name T355
Test name
Test status
Simulation time 172846595935 ps
CPU time 215.06 seconds
Started Jan 14 01:38:58 PM PST 24
Finished Jan 14 01:42:34 PM PST 24
Peak memory 200872 kb
Host smart-94b232af-1718-4dd2-be73-4e561e8412b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642174562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3642174562
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1327391773
Short name T58
Test name
Test status
Simulation time 163755186497 ps
CPU time 191.32 seconds
Started Jan 14 01:39:01 PM PST 24
Finished Jan 14 01:42:13 PM PST 24
Peak memory 200964 kb
Host smart-a5c0c03c-b3f5-43e7-8620-44576411f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327391773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1327391773
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.775312918
Short name T115
Test name
Test status
Simulation time 486652013966 ps
CPU time 604.03 seconds
Started Jan 14 01:38:58 PM PST 24
Finished Jan 14 01:49:03 PM PST 24
Peak memory 200832 kb
Host smart-b6a3dd0f-f4d8-4bb4-993d-64827787812c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=775312918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.775312918
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.27024672
Short name T309
Test name
Test status
Simulation time 166576816346 ps
CPU time 391.21 seconds
Started Jan 14 01:39:00 PM PST 24
Finished Jan 14 01:45:32 PM PST 24
Peak memory 200880 kb
Host smart-039f2f7d-803a-47ee-b249-f0ff86a75830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27024672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.27024672
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.84312440
Short name T823
Test name
Test status
Simulation time 490860083201 ps
CPU time 1139.67 seconds
Started Jan 14 01:38:59 PM PST 24
Finished Jan 14 01:58:00 PM PST 24
Peak memory 200892 kb
Host smart-e58a71e4-e33c-498c-98f0-b59cdb8589a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=84312440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixed
.84312440
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3702974441
Short name T663
Test name
Test status
Simulation time 479086333687 ps
CPU time 1088.54 seconds
Started Jan 14 01:38:59 PM PST 24
Finished Jan 14 01:57:08 PM PST 24
Peak memory 200952 kb
Host smart-9c4da60f-236d-434f-b323-774c14ef08d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702974441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3702974441
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3305667313
Short name T588
Test name
Test status
Simulation time 100704471367 ps
CPU time 542.24 seconds
Started Jan 14 01:39:09 PM PST 24
Finished Jan 14 01:48:12 PM PST 24
Peak memory 201328 kb
Host smart-7d808380-9ef7-42f1-aed2-df23bdea353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305667313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3305667313
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.784198415
Short name T424
Test name
Test status
Simulation time 31668658876 ps
CPU time 75.4 seconds
Started Jan 14 01:39:09 PM PST 24
Finished Jan 14 01:40:25 PM PST 24
Peak memory 200748 kb
Host smart-23eb600d-5d93-4e46-b052-94d17f49870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784198415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.784198415
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.997306388
Short name T496
Test name
Test status
Simulation time 2980476134 ps
CPU time 7.13 seconds
Started Jan 14 01:39:10 PM PST 24
Finished Jan 14 01:39:18 PM PST 24
Peak memory 200672 kb
Host smart-c5f7bd4f-af24-4446-afc2-63f656009322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997306388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.997306388
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2730735615
Short name T674
Test name
Test status
Simulation time 6014513667 ps
CPU time 7.97 seconds
Started Jan 14 01:39:09 PM PST 24
Finished Jan 14 01:39:17 PM PST 24
Peak memory 200612 kb
Host smart-8eac1692-44ec-43e7-9a0c-3ec948437ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730735615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2730735615
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3621630707
Short name T364
Test name
Test status
Simulation time 298781969835 ps
CPU time 549.14 seconds
Started Jan 14 01:39:06 PM PST 24
Finished Jan 14 01:48:16 PM PST 24
Peak memory 201388 kb
Host smart-dc583200-bf35-4300-8dcf-5158f11ed0f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621630707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3621630707
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2410351673
Short name T172
Test name
Test status
Simulation time 315653764482 ps
CPU time 400.48 seconds
Started Jan 14 01:39:06 PM PST 24
Finished Jan 14 01:45:48 PM PST 24
Peak memory 209620 kb
Host smart-4e0d0231-9ddc-4f51-856f-46273284a719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410351673 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2410351673
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1696898670
Short name T768
Test name
Test status
Simulation time 359702282 ps
CPU time 1.45 seconds
Started Jan 14 01:39:28 PM PST 24
Finished Jan 14 01:39:41 PM PST 24
Peak memory 200632 kb
Host smart-d84e670d-42ca-46dc-8c03-147791d03c7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696898670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1696898670
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1398237045
Short name T840
Test name
Test status
Simulation time 335704325326 ps
CPU time 322.65 seconds
Started Jan 14 01:39:16 PM PST 24
Finished Jan 14 01:44:40 PM PST 24
Peak memory 200976 kb
Host smart-38f7cdda-e500-482f-ba66-531a03eddab9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398237045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1398237045
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4294100136
Short name T125
Test name
Test status
Simulation time 171269179596 ps
CPU time 109.61 seconds
Started Jan 14 01:39:16 PM PST 24
Finished Jan 14 01:41:06 PM PST 24
Peak memory 200904 kb
Host smart-c7c117f2-69dd-4db0-ab69-2f28aebf73aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294100136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4294100136
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.275576015
Short name T613
Test name
Test status
Simulation time 166246686634 ps
CPU time 100.55 seconds
Started Jan 14 01:39:15 PM PST 24
Finished Jan 14 01:40:56 PM PST 24
Peak memory 200840 kb
Host smart-3f6929b0-b8ab-4915-aae8-62d3e6714032
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=275576015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.275576015
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1931343916
Short name T138
Test name
Test status
Simulation time 483840452138 ps
CPU time 1131.73 seconds
Started Jan 14 01:39:10 PM PST 24
Finished Jan 14 01:58:03 PM PST 24
Peak memory 200916 kb
Host smart-ddf603d7-2cb8-4ef2-9b85-9edb21aedff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931343916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1931343916
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1507777975
Short name T163
Test name
Test status
Simulation time 494724401255 ps
CPU time 839.42 seconds
Started Jan 14 01:39:07 PM PST 24
Finished Jan 14 01:53:07 PM PST 24
Peak memory 200964 kb
Host smart-57242bd2-3b9c-4e2e-88ce-122cae2524d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507777975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1507777975
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1562009051
Short name T298
Test name
Test status
Simulation time 333575598100 ps
CPU time 750.87 seconds
Started Jan 14 01:39:15 PM PST 24
Finished Jan 14 01:51:47 PM PST 24
Peak memory 200888 kb
Host smart-121787ec-0587-45f2-be6f-1ece6c77f849
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562009051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1562009051
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3468240065
Short name T565
Test name
Test status
Simulation time 169451476406 ps
CPU time 369.16 seconds
Started Jan 14 01:39:29 PM PST 24
Finished Jan 14 01:45:49 PM PST 24
Peak memory 200804 kb
Host smart-77bafbe2-3848-4306-aa9d-298469204cff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468240065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3468240065
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3813038061
Short name T465
Test name
Test status
Simulation time 86407484954 ps
CPU time 439.61 seconds
Started Jan 14 01:39:26 PM PST 24
Finished Jan 14 01:46:54 PM PST 24
Peak memory 201328 kb
Host smart-cfc58792-d7d7-4467-ad58-cbc7ff5b2065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813038061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3813038061
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.365607676
Short name T52
Test name
Test status
Simulation time 28675502688 ps
CPU time 16.19 seconds
Started Jan 14 01:39:26 PM PST 24
Finished Jan 14 01:39:50 PM PST 24
Peak memory 200708 kb
Host smart-4a48d528-e863-4de7-b596-7f8bf77a3ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365607676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.365607676
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.22696824
Short name T824
Test name
Test status
Simulation time 3413830327 ps
CPU time 9.38 seconds
Started Jan 14 01:39:21 PM PST 24
Finished Jan 14 01:39:31 PM PST 24
Peak memory 200752 kb
Host smart-8fdd6210-24aa-4305-b272-0a6f17feb959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22696824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.22696824
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1168983949
Short name T548
Test name
Test status
Simulation time 6084276522 ps
CPU time 7.62 seconds
Started Jan 14 01:39:08 PM PST 24
Finished Jan 14 01:39:16 PM PST 24
Peak memory 200644 kb
Host smart-028b02da-3f32-4384-9035-5ec56360d605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168983949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1168983949
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.996514541
Short name T281
Test name
Test status
Simulation time 168827161443 ps
CPU time 406.2 seconds
Started Jan 14 01:39:27 PM PST 24
Finished Jan 14 01:46:20 PM PST 24
Peak memory 200812 kb
Host smart-617f42cb-623a-46e9-86eb-d05a15a5e5c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996514541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
996514541
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.958249875
Short name T568
Test name
Test status
Simulation time 186365227496 ps
CPU time 104.88 seconds
Started Jan 14 01:39:29 PM PST 24
Finished Jan 14 01:41:25 PM PST 24
Peak memory 209120 kb
Host smart-71d48f37-e3f0-40a2-ae09-c59ba816a38c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958249875 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.958249875
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2780845251
Short name T537
Test name
Test status
Simulation time 381259913 ps
CPU time 0.76 seconds
Started Jan 14 01:39:32 PM PST 24
Finished Jan 14 01:39:40 PM PST 24
Peak memory 200648 kb
Host smart-7d41e85f-b71e-4656-9da8-5193df46b3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780845251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2780845251
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2275591156
Short name T314
Test name
Test status
Simulation time 182534792519 ps
CPU time 50.12 seconds
Started Jan 14 01:39:27 PM PST 24
Finished Jan 14 01:40:30 PM PST 24
Peak memory 200776 kb
Host smart-d36c58bc-06a5-481a-a6f8-969699cf3190
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275591156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2275591156
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1485319702
Short name T633
Test name
Test status
Simulation time 165472970252 ps
CPU time 193.29 seconds
Started Jan 14 01:39:35 PM PST 24
Finished Jan 14 01:42:58 PM PST 24
Peak memory 200944 kb
Host smart-6c1182e9-386a-432e-8aaf-d497539b2667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485319702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1485319702
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.88185212
Short name T687
Test name
Test status
Simulation time 324833168667 ps
CPU time 197.5 seconds
Started Jan 14 01:39:26 PM PST 24
Finished Jan 14 01:42:51 PM PST 24
Peak memory 200956 kb
Host smart-8c4813b7-b00f-45a0-9c36-d81bc71b732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88185212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.88185212
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3964752122
Short name T612
Test name
Test status
Simulation time 486078051440 ps
CPU time 1141.9 seconds
Started Jan 14 01:39:27 PM PST 24
Finished Jan 14 01:58:42 PM PST 24
Peak memory 200916 kb
Host smart-f959c3e3-1f02-42ff-9649-913445079d83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964752122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3964752122
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3469340220
Short name T680
Test name
Test status
Simulation time 327951857799 ps
CPU time 45.68 seconds
Started Jan 14 01:39:26 PM PST 24
Finished Jan 14 01:40:19 PM PST 24
Peak memory 200952 kb
Host smart-f3ee660c-7efd-4fe6-a6f9-250f74d5e238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469340220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3469340220
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3232037359
Short name T735
Test name
Test status
Simulation time 161520659378 ps
CPU time 64.67 seconds
Started Jan 14 01:39:25 PM PST 24
Finished Jan 14 01:40:31 PM PST 24
Peak memory 200864 kb
Host smart-a07335a0-c791-4786-9f05-17fd942b1801
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232037359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3232037359
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.422575218
Short name T146
Test name
Test status
Simulation time 164330977674 ps
CPU time 184.66 seconds
Started Jan 14 01:39:27 PM PST 24
Finished Jan 14 01:42:44 PM PST 24
Peak memory 200884 kb
Host smart-4bb5cb86-b1f4-404c-b5ef-a38e2b75d07c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422575218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.422575218
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1901970676
Short name T605
Test name
Test status
Simulation time 158678126507 ps
CPU time 386.26 seconds
Started Jan 14 01:39:29 PM PST 24
Finished Jan 14 01:46:06 PM PST 24
Peak memory 200420 kb
Host smart-7fba4983-1ca7-456e-b195-01f2606c66a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901970676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1901970676
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1967577743
Short name T850
Test name
Test status
Simulation time 118344996408 ps
CPU time 454.78 seconds
Started Jan 14 01:39:32 PM PST 24
Finished Jan 14 01:47:15 PM PST 24
Peak memory 201328 kb
Host smart-dead7e23-3b1e-43c7-8283-f70d01f16047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967577743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1967577743
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4146707363
Short name T117
Test name
Test status
Simulation time 42717532035 ps
CPU time 25.72 seconds
Started Jan 14 01:39:35 PM PST 24
Finished Jan 14 01:40:10 PM PST 24
Peak memory 200732 kb
Host smart-faa26ec5-b829-4be5-aa79-e0c202a6c9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146707363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4146707363
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.71158556
Short name T19
Test name
Test status
Simulation time 4527356658 ps
CPU time 12.04 seconds
Started Jan 14 01:39:33 PM PST 24
Finished Jan 14 01:39:52 PM PST 24
Peak memory 200748 kb
Host smart-14ce161f-f5c6-4a21-8b66-cc87ba97f171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71158556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.71158556
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3399897756
Short name T562
Test name
Test status
Simulation time 5652426833 ps
CPU time 1.88 seconds
Started Jan 14 01:39:29 PM PST 24
Finished Jan 14 01:39:42 PM PST 24
Peak memory 200708 kb
Host smart-6df71eee-8a66-41ae-829b-8d3d5d27b32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399897756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3399897756
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1425459720
Short name T852
Test name
Test status
Simulation time 196854911796 ps
CPU time 230.38 seconds
Started Jan 14 01:39:32 PM PST 24
Finished Jan 14 01:43:30 PM PST 24
Peak memory 201012 kb
Host smart-b3a93a78-7d0a-4dc7-9dfc-4cb00500d7e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425459720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1425459720
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1582777592
Short name T193
Test name
Test status
Simulation time 152152429720 ps
CPU time 158.4 seconds
Started Jan 14 01:39:32 PM PST 24
Finished Jan 14 01:42:18 PM PST 24
Peak memory 217868 kb
Host smart-437d58b6-1e42-483f-8aa9-d8a5b9f60905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582777592 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1582777592
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.467753146
Short name T476
Test name
Test status
Simulation time 505921693 ps
CPU time 0.88 seconds
Started Jan 14 01:39:40 PM PST 24
Finished Jan 14 01:39:48 PM PST 24
Peak memory 200692 kb
Host smart-3b906af8-a38d-497b-a046-eb688ba91a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467753146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.467753146
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1732940561
Short name T869
Test name
Test status
Simulation time 164270972077 ps
CPU time 159.04 seconds
Started Jan 14 01:39:40 PM PST 24
Finished Jan 14 01:42:27 PM PST 24
Peak memory 200944 kb
Host smart-7afd8550-d31a-4ea9-8c5c-7dbda9fc25c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732940561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1732940561
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1241442930
Short name T516
Test name
Test status
Simulation time 322413757071 ps
CPU time 693.02 seconds
Started Jan 14 01:39:40 PM PST 24
Finished Jan 14 01:51:20 PM PST 24
Peak memory 200896 kb
Host smart-2c144195-3fad-401e-962e-afdf0419322c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241442930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1241442930
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.375578105
Short name T290
Test name
Test status
Simulation time 485628384317 ps
CPU time 277.66 seconds
Started Jan 14 01:39:42 PM PST 24
Finished Jan 14 01:44:26 PM PST 24
Peak memory 200924 kb
Host smart-3c6c67a7-fd66-451a-937e-f813816d45e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375578105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.375578105
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3837333054
Short name T702
Test name
Test status
Simulation time 324427404946 ps
CPU time 170.6 seconds
Started Jan 14 01:39:39 PM PST 24
Finished Jan 14 01:42:37 PM PST 24
Peak memory 200732 kb
Host smart-7ec1ff65-80ec-4fa4-b8fe-57303b06bb53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837333054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3837333054
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1912162510
Short name T830
Test name
Test status
Simulation time 167175325941 ps
CPU time 206.6 seconds
Started Jan 14 01:39:51 PM PST 24
Finished Jan 14 01:43:19 PM PST 24
Peak memory 200736 kb
Host smart-958b2207-219b-4bc2-9509-829e5a1ed93e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912162510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1912162510
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1690406554
Short name T564
Test name
Test status
Simulation time 166249980974 ps
CPU time 343.49 seconds
Started Jan 14 01:39:51 PM PST 24
Finished Jan 14 01:45:35 PM PST 24
Peak memory 200892 kb
Host smart-877b7ea2-a4c4-4038-b781-26a9cfb6dc18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690406554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1690406554
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.445043101
Short name T144
Test name
Test status
Simulation time 148974700680 ps
CPU time 709.91 seconds
Started Jan 14 01:39:41 PM PST 24
Finished Jan 14 01:51:38 PM PST 24
Peak memory 201348 kb
Host smart-76edde04-102d-41a3-bd40-ef00a184823e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445043101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.445043101
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.4271918285
Short name T794
Test name
Test status
Simulation time 39458530357 ps
CPU time 46 seconds
Started Jan 14 01:39:40 PM PST 24
Finished Jan 14 01:40:33 PM PST 24
Peak memory 200752 kb
Host smart-38939577-ab74-4794-ac8a-a79509386748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271918285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.4271918285
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2272698605
Short name T474
Test name
Test status
Simulation time 4206122228 ps
CPU time 3.15 seconds
Started Jan 14 01:39:41 PM PST 24
Finished Jan 14 01:39:51 PM PST 24
Peak memory 200752 kb
Host smart-91bc29a9-d5b5-4daa-ab96-aee14c3c90bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272698605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2272698605
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1391989242
Short name T754
Test name
Test status
Simulation time 6131804572 ps
CPU time 4.16 seconds
Started Jan 14 01:39:41 PM PST 24
Finished Jan 14 01:39:52 PM PST 24
Peak memory 200768 kb
Host smart-36caf27c-70cc-434d-b924-ee5b8703ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391989242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1391989242
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1123354594
Short name T333
Test name
Test status
Simulation time 250899861466 ps
CPU time 566 seconds
Started Jan 14 01:39:39 PM PST 24
Finished Jan 14 01:49:13 PM PST 24
Peak memory 200892 kb
Host smart-55d30d6e-6937-4d77-aa7e-49f0b827f498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123354594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1123354594
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1609542157
Short name T273
Test name
Test status
Simulation time 27063686356 ps
CPU time 115.73 seconds
Started Jan 14 01:39:40 PM PST 24
Finished Jan 14 01:41:43 PM PST 24
Peak memory 209672 kb
Host smart-9d325e93-2ea1-41b4-81bd-be9c788611f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609542157 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1609542157
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2441654716
Short name T686
Test name
Test status
Simulation time 339473427 ps
CPU time 0.81 seconds
Started Jan 14 01:39:57 PM PST 24
Finished Jan 14 01:39:59 PM PST 24
Peak memory 200676 kb
Host smart-808b6b8c-2856-401b-97a7-7d7255b2afa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441654716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2441654716
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.370636397
Short name T232
Test name
Test status
Simulation time 327703082617 ps
CPU time 743.44 seconds
Started Jan 14 01:39:48 PM PST 24
Finished Jan 14 01:52:13 PM PST 24
Peak memory 200860 kb
Host smart-c2443489-89df-482e-bdcc-b7c2a4a69ee2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370636397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.370636397
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1611437685
Short name T166
Test name
Test status
Simulation time 501603374093 ps
CPU time 283.11 seconds
Started Jan 14 01:39:55 PM PST 24
Finished Jan 14 01:44:39 PM PST 24
Peak memory 200936 kb
Host smart-7e3a8e54-ba92-493b-acd4-69c568cdfbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611437685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1611437685
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1022539102
Short name T16
Test name
Test status
Simulation time 171204281482 ps
CPU time 426.92 seconds
Started Jan 14 01:39:57 PM PST 24
Finished Jan 14 01:47:05 PM PST 24
Peak memory 200952 kb
Host smart-50644e63-b4ff-422b-a9ca-a207de00a6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022539102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1022539102
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3450288715
Short name T616
Test name
Test status
Simulation time 326865778958 ps
CPU time 626.6 seconds
Started Jan 14 01:39:54 PM PST 24
Finished Jan 14 01:50:22 PM PST 24
Peak memory 200832 kb
Host smart-eb075940-2b7c-4303-bc3a-0eba3f7b0482
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450288715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3450288715
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2530754780
Short name T194
Test name
Test status
Simulation time 492032176632 ps
CPU time 286.31 seconds
Started Jan 14 01:39:51 PM PST 24
Finished Jan 14 01:44:38 PM PST 24
Peak memory 200904 kb
Host smart-1decde27-b456-4a22-a580-6bb7afb2e3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530754780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2530754780
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.536154204
Short name T660
Test name
Test status
Simulation time 323955814947 ps
CPU time 804.75 seconds
Started Jan 14 01:39:55 PM PST 24
Finished Jan 14 01:53:20 PM PST 24
Peak memory 200908 kb
Host smart-b7c0b6ba-adc8-47cc-8c86-62b71693f467
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=536154204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.536154204
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.4248459792
Short name T700
Test name
Test status
Simulation time 159675150704 ps
CPU time 192.92 seconds
Started Jan 14 01:39:54 PM PST 24
Finished Jan 14 01:43:08 PM PST 24
Peak memory 200884 kb
Host smart-0c72949e-6d18-4ee9-8c5e-6208a1b0f8a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248459792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.4248459792
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.809182494
Short name T712
Test name
Test status
Simulation time 327317209277 ps
CPU time 79.34 seconds
Started Jan 14 01:39:55 PM PST 24
Finished Jan 14 01:41:15 PM PST 24
Peak memory 200964 kb
Host smart-60efa23d-cdf0-42b2-a609-600e29ed1521
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809182494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.809182494
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4079537700
Short name T834
Test name
Test status
Simulation time 32780874400 ps
CPU time 74.33 seconds
Started Jan 14 01:39:57 PM PST 24
Finished Jan 14 01:41:13 PM PST 24
Peak memory 200748 kb
Host smart-c4cd3e4e-1439-4596-a2de-fc5abff3a966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079537700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.4079537700
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1107142628
Short name T819
Test name
Test status
Simulation time 4123310672 ps
CPU time 11.58 seconds
Started Jan 14 01:39:55 PM PST 24
Finished Jan 14 01:40:07 PM PST 24
Peak memory 200760 kb
Host smart-b4f48a56-3475-4f96-93ae-2148488a986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107142628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1107142628
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3525064220
Short name T104
Test name
Test status
Simulation time 5998580613 ps
CPU time 4.9 seconds
Started Jan 14 01:39:40 PM PST 24
Finished Jan 14 01:39:52 PM PST 24
Peak memory 200748 kb
Host smart-174f9449-3ca3-4459-bb0a-1d25903f43ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525064220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3525064220
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.536370129
Short name T226
Test name
Test status
Simulation time 185424308242 ps
CPU time 415.91 seconds
Started Jan 14 01:39:54 PM PST 24
Finished Jan 14 01:46:51 PM PST 24
Peak memory 200904 kb
Host smart-3d394acf-54fb-4d90-9a8a-17fa769f9acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536370129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
536370129
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1141867730
Short name T583
Test name
Test status
Simulation time 236908601581 ps
CPU time 267.47 seconds
Started Jan 14 01:39:54 PM PST 24
Finished Jan 14 01:44:23 PM PST 24
Peak memory 217740 kb
Host smart-4dc50864-bdef-4c80-b81b-3a1d4acf143e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141867730 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1141867730
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1146131453
Short name T471
Test name
Test status
Simulation time 560299896 ps
CPU time 0.93 seconds
Started Jan 14 01:40:05 PM PST 24
Finished Jan 14 01:40:11 PM PST 24
Peak memory 200696 kb
Host smart-b97c8d0b-b656-4c53-a573-545fc8ecccea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146131453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1146131453
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1531742483
Short name T621
Test name
Test status
Simulation time 163447996226 ps
CPU time 31.77 seconds
Started Jan 14 01:39:57 PM PST 24
Finished Jan 14 01:40:30 PM PST 24
Peak memory 200876 kb
Host smart-15cdddd9-cf2a-41a8-96c5-260b5a05b993
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531742483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1531742483
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1736168924
Short name T239
Test name
Test status
Simulation time 164949192922 ps
CPU time 100.69 seconds
Started Jan 14 01:40:00 PM PST 24
Finished Jan 14 01:41:42 PM PST 24
Peak memory 200892 kb
Host smart-0fb0b5a5-3f1d-4304-b4f6-ef50a0e3f8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736168924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1736168924
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3818634511
Short name T326
Test name
Test status
Simulation time 324944122210 ps
CPU time 771.79 seconds
Started Jan 14 01:39:57 PM PST 24
Finished Jan 14 01:52:50 PM PST 24
Peak memory 200924 kb
Host smart-12e4c8d2-408d-40a6-a331-e8d6d1ac12e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818634511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3818634511
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.343968824
Short name T760
Test name
Test status
Simulation time 162874839356 ps
CPU time 358.09 seconds
Started Jan 14 01:40:00 PM PST 24
Finished Jan 14 01:46:01 PM PST 24
Peak memory 200848 kb
Host smart-09505416-85fd-4be2-ad75-f8f0a8f1e144
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=343968824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.343968824
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.224204571
Short name T184
Test name
Test status
Simulation time 489861163178 ps
CPU time 1223.01 seconds
Started Jan 14 01:39:58 PM PST 24
Finished Jan 14 02:00:22 PM PST 24
Peak memory 200856 kb
Host smart-5e4480d3-e3a6-4db1-9d01-42059092e99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224204571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.224204571
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.774719394
Short name T667
Test name
Test status
Simulation time 490186267843 ps
CPU time 382.7 seconds
Started Jan 14 01:39:59 PM PST 24
Finished Jan 14 01:46:22 PM PST 24
Peak memory 200880 kb
Host smart-4d8f3e15-f171-4704-8d74-a81098060046
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=774719394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.774719394
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.562232077
Short name T814
Test name
Test status
Simulation time 326182264489 ps
CPU time 50.33 seconds
Started Jan 14 01:40:01 PM PST 24
Finished Jan 14 01:40:53 PM PST 24
Peak memory 200888 kb
Host smart-ada8f574-d5a2-4ae0-a9c9-cd44becbcb55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562232077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.562232077
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1514987180
Short name T174
Test name
Test status
Simulation time 111626875675 ps
CPU time 590.69 seconds
Started Jan 14 01:40:06 PM PST 24
Finished Jan 14 01:50:01 PM PST 24
Peak memory 201340 kb
Host smart-8372dbd6-327d-4679-a810-a66d2997f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514987180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1514987180
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.4264557225
Short name T630
Test name
Test status
Simulation time 37530443504 ps
CPU time 86.25 seconds
Started Jan 14 01:40:00 PM PST 24
Finished Jan 14 01:41:28 PM PST 24
Peak memory 200756 kb
Host smart-5ddfbbe6-6dbd-4aaf-a5b0-ec4480026dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264557225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4264557225
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2189704754
Short name T690
Test name
Test status
Simulation time 4883859282 ps
CPU time 3.73 seconds
Started Jan 14 01:40:04 PM PST 24
Finished Jan 14 01:40:14 PM PST 24
Peak memory 200692 kb
Host smart-d98c175e-bbf8-47e3-9670-fd4683779860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189704754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2189704754
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1835629874
Short name T441
Test name
Test status
Simulation time 6000825824 ps
CPU time 2.57 seconds
Started Jan 14 01:40:01 PM PST 24
Finished Jan 14 01:40:06 PM PST 24
Peak memory 200700 kb
Host smart-0d068ada-5173-484e-ad09-bf3a040420ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835629874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1835629874
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1518007056
Short name T818
Test name
Test status
Simulation time 397829168339 ps
CPU time 455.65 seconds
Started Jan 14 01:40:07 PM PST 24
Finished Jan 14 01:47:46 PM PST 24
Peak memory 209508 kb
Host smart-9f660347-7ba2-4cb0-8b49-18a6dae46005
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518007056 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1518007056
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.904489120
Short name T533
Test name
Test status
Simulation time 341375031 ps
CPU time 1.29 seconds
Started Jan 14 01:33:46 PM PST 24
Finished Jan 14 01:33:48 PM PST 24
Peak memory 200688 kb
Host smart-7163685e-9bb3-4303-aa0d-1fa239cb3856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904489120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.904489120
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2690154727
Short name T142
Test name
Test status
Simulation time 334333023602 ps
CPU time 65.01 seconds
Started Jan 14 01:33:50 PM PST 24
Finished Jan 14 01:34:56 PM PST 24
Peak memory 200848 kb
Host smart-f44061e1-8b46-4c79-bafb-d2f7ad9dfaad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690154727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2690154727
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3795915814
Short name T266
Test name
Test status
Simulation time 164561740501 ps
CPU time 173.75 seconds
Started Jan 14 01:33:41 PM PST 24
Finished Jan 14 01:36:35 PM PST 24
Peak memory 200916 kb
Host smart-d72c236f-ead1-4861-84b4-01e33ba0fb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795915814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3795915814
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2025250050
Short name T679
Test name
Test status
Simulation time 330142939010 ps
CPU time 748.58 seconds
Started Jan 14 01:33:40 PM PST 24
Finished Jan 14 01:46:09 PM PST 24
Peak memory 200972 kb
Host smart-ffbd7890-c4bf-4e15-8089-97d8cbc4b309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025250050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2025250050
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4055997464
Short name T701
Test name
Test status
Simulation time 165092805623 ps
CPU time 68.47 seconds
Started Jan 14 01:33:42 PM PST 24
Finished Jan 14 01:34:51 PM PST 24
Peak memory 200944 kb
Host smart-e4dfd519-510d-4624-b3ed-b4cbaa6a8c52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055997464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4055997464
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.266758539
Short name T603
Test name
Test status
Simulation time 165893204957 ps
CPU time 187.39 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:36:52 PM PST 24
Peak memory 200808 kb
Host smart-2035a1e7-7db3-4613-9e6c-1158c5838ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266758539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.266758539
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.938984684
Short name T437
Test name
Test status
Simulation time 491053978884 ps
CPU time 1187.31 seconds
Started Jan 14 01:33:41 PM PST 24
Finished Jan 14 01:53:29 PM PST 24
Peak memory 200880 kb
Host smart-ba6e37ea-3e1d-4696-ad35-d3cd182020ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=938984684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.938984684
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1596643877
Short name T128
Test name
Test status
Simulation time 163435171045 ps
CPU time 93.63 seconds
Started Jan 14 01:33:40 PM PST 24
Finished Jan 14 01:35:14 PM PST 24
Peak memory 200868 kb
Host smart-1199c369-b8fa-449e-b9a9-963e8557fa19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596643877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1596643877
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2744290609
Short name T604
Test name
Test status
Simulation time 496104363367 ps
CPU time 602.89 seconds
Started Jan 14 01:33:47 PM PST 24
Finished Jan 14 01:43:50 PM PST 24
Peak memory 200988 kb
Host smart-9038b1b0-a2df-40ba-81e3-6db083ecbe7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744290609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2744290609
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3116646078
Short name T838
Test name
Test status
Simulation time 120537874638 ps
CPU time 438.55 seconds
Started Jan 14 01:33:49 PM PST 24
Finished Jan 14 01:41:08 PM PST 24
Peak memory 201408 kb
Host smart-1f580150-5b66-425c-8d63-67f55fa0e563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116646078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3116646078
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3774685272
Short name T653
Test name
Test status
Simulation time 29315848957 ps
CPU time 18.56 seconds
Started Jan 14 01:33:55 PM PST 24
Finished Jan 14 01:34:14 PM PST 24
Peak memory 200756 kb
Host smart-642a54e8-d35e-475e-b072-2962d1745751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774685272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3774685272
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2743124658
Short name T842
Test name
Test status
Simulation time 3499073281 ps
CPU time 4.8 seconds
Started Jan 14 01:33:45 PM PST 24
Finished Jan 14 01:33:50 PM PST 24
Peak memory 200724 kb
Host smart-d9985de4-792c-4d9d-8b03-1977c2b77c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743124658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2743124658
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.797710200
Short name T489
Test name
Test status
Simulation time 6276509330 ps
CPU time 1.59 seconds
Started Jan 14 01:33:39 PM PST 24
Finished Jan 14 01:33:42 PM PST 24
Peak memory 200704 kb
Host smart-cf7776b3-111d-4f81-b45a-ff8ad4b8c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797710200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.797710200
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2161152808
Short name T792
Test name
Test status
Simulation time 42456432999 ps
CPU time 46.65 seconds
Started Jan 14 01:33:46 PM PST 24
Finished Jan 14 01:34:33 PM PST 24
Peak memory 200944 kb
Host smart-b40e4592-fcbb-4b3d-818f-01b70342a878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161152808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2161152808
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1615950686
Short name T500
Test name
Test status
Simulation time 370363388 ps
CPU time 0.94 seconds
Started Jan 14 01:33:53 PM PST 24
Finished Jan 14 01:33:55 PM PST 24
Peak memory 200692 kb
Host smart-43b348be-e50e-4487-b108-843897720fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615950686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1615950686
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3009014515
Short name T294
Test name
Test status
Simulation time 323675800983 ps
CPU time 253.26 seconds
Started Jan 14 01:33:46 PM PST 24
Finished Jan 14 01:38:00 PM PST 24
Peak memory 200948 kb
Host smart-c705d6c5-8584-480b-85d1-9e1563469e24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009014515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3009014515
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3074398585
Short name T337
Test name
Test status
Simulation time 165603024072 ps
CPU time 204.36 seconds
Started Jan 14 01:33:54 PM PST 24
Finished Jan 14 01:37:19 PM PST 24
Peak memory 200956 kb
Host smart-e633c67e-9cb8-4739-aef9-535c452d5837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074398585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3074398585
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3293489274
Short name T285
Test name
Test status
Simulation time 488957369845 ps
CPU time 1087.52 seconds
Started Jan 14 01:33:53 PM PST 24
Finished Jan 14 01:52:01 PM PST 24
Peak memory 200968 kb
Host smart-1fce99dc-9cb1-4004-99d7-63fb049a58e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293489274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3293489274
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.4291738315
Short name T848
Test name
Test status
Simulation time 164168178192 ps
CPU time 356.67 seconds
Started Jan 14 01:33:52 PM PST 24
Finished Jan 14 01:39:50 PM PST 24
Peak memory 200896 kb
Host smart-eb73dda2-f59d-4990-92eb-d1bcd682ae4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291738315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.4291738315
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.421911715
Short name T189
Test name
Test status
Simulation time 494865118366 ps
CPU time 245.49 seconds
Started Jan 14 01:33:43 PM PST 24
Finished Jan 14 01:37:49 PM PST 24
Peak memory 200976 kb
Host smart-0e343aa6-b6ee-437d-be32-11d7694af25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421911715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.421911715
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2027831326
Short name T853
Test name
Test status
Simulation time 497250065113 ps
CPU time 547.39 seconds
Started Jan 14 01:33:45 PM PST 24
Finished Jan 14 01:42:53 PM PST 24
Peak memory 200876 kb
Host smart-58491028-44ce-4f57-9324-1fd589cd9c6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027831326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2027831326
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1412515461
Short name T109
Test name
Test status
Simulation time 495440856072 ps
CPU time 554.58 seconds
Started Jan 14 01:33:54 PM PST 24
Finished Jan 14 01:43:09 PM PST 24
Peak memory 200896 kb
Host smart-fbbf29ff-27ad-4857-9235-bbca759dfe34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412515461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1412515461
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2438437084
Short name T614
Test name
Test status
Simulation time 162257636578 ps
CPU time 223.17 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:37:28 PM PST 24
Peak memory 200708 kb
Host smart-25be846e-bfcd-4219-9606-b602f1be0731
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438437084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2438437084
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1271290162
Short name T171
Test name
Test status
Simulation time 122875250615 ps
CPU time 405.36 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:40:42 PM PST 24
Peak memory 201332 kb
Host smart-c6eeddba-e158-4a09-8071-1f94c125cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271290162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1271290162
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3656532373
Short name T466
Test name
Test status
Simulation time 37824146793 ps
CPU time 90.95 seconds
Started Jan 14 01:33:44 PM PST 24
Finished Jan 14 01:35:16 PM PST 24
Peak memory 200688 kb
Host smart-19496ca0-1671-44b9-b356-6c2cee04791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656532373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3656532373
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2247970488
Short name T809
Test name
Test status
Simulation time 2742470142 ps
CPU time 5.36 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:34:02 PM PST 24
Peak memory 200740 kb
Host smart-6907b063-16d0-4e87-8267-d83f8e622d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247970488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2247970488
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.485302281
Short name T666
Test name
Test status
Simulation time 6022247127 ps
CPU time 1.49 seconds
Started Jan 14 01:33:47 PM PST 24
Finished Jan 14 01:33:49 PM PST 24
Peak memory 200800 kb
Host smart-eb966c9b-3efc-43b5-af23-abc193140f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485302281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.485302281
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3020596798
Short name T456
Test name
Test status
Simulation time 201429106148 ps
CPU time 114.03 seconds
Started Jan 14 01:33:41 PM PST 24
Finished Jan 14 01:35:36 PM PST 24
Peak memory 200848 kb
Host smart-3238fb61-3506-4693-b740-0f1997041ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020596798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3020596798
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2850759996
Short name T451
Test name
Test status
Simulation time 524118232 ps
CPU time 1.68 seconds
Started Jan 14 01:34:02 PM PST 24
Finished Jan 14 01:34:04 PM PST 24
Peak memory 200696 kb
Host smart-56502370-ae3f-45bd-aa4d-12fedb6706df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850759996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2850759996
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.305052465
Short name T176
Test name
Test status
Simulation time 325427761271 ps
CPU time 103.5 seconds
Started Jan 14 01:33:45 PM PST 24
Finished Jan 14 01:35:29 PM PST 24
Peak memory 200936 kb
Host smart-9fe4f2bc-77fb-4763-9f8e-1c6f50538498
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305052465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.305052465
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.985111634
Short name T258
Test name
Test status
Simulation time 486802130391 ps
CPU time 304.63 seconds
Started Jan 14 01:33:58 PM PST 24
Finished Jan 14 01:39:03 PM PST 24
Peak memory 200960 kb
Host smart-05dfa880-4da9-4bf7-b07c-79a665fcbce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985111634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.985111634
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1527061342
Short name T755
Test name
Test status
Simulation time 321314658276 ps
CPU time 226.65 seconds
Started Jan 14 01:33:49 PM PST 24
Finished Jan 14 01:37:36 PM PST 24
Peak memory 200872 kb
Host smart-ed1c718e-5452-4fba-be78-a39e988de58e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527061342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1527061342
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.4050689670
Short name T275
Test name
Test status
Simulation time 328780974175 ps
CPU time 393.45 seconds
Started Jan 14 01:33:50 PM PST 24
Finished Jan 14 01:40:24 PM PST 24
Peak memory 200796 kb
Host smart-d3c9bf34-90fb-4f27-b3b1-2a121515f7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050689670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.4050689670
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.165237546
Short name T23
Test name
Test status
Simulation time 491278924627 ps
CPU time 1151.75 seconds
Started Jan 14 01:33:57 PM PST 24
Finished Jan 14 01:53:09 PM PST 24
Peak memory 200844 kb
Host smart-4b0134b4-363d-4a93-bebf-20d3d8d5131a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=165237546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.165237546
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.104631359
Short name T246
Test name
Test status
Simulation time 506636921314 ps
CPU time 332.74 seconds
Started Jan 14 01:33:55 PM PST 24
Finished Jan 14 01:39:29 PM PST 24
Peak memory 200904 kb
Host smart-941ab5f1-2ad9-4a94-a4b6-ac1130d9b9c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104631359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.104631359
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3702102994
Short name T745
Test name
Test status
Simulation time 326655165993 ps
CPU time 197.32 seconds
Started Jan 14 01:33:49 PM PST 24
Finished Jan 14 01:37:07 PM PST 24
Peak memory 200884 kb
Host smart-650ea0e7-13ac-49dd-a2c0-8bb694b6798e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702102994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3702102994
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1327559239
Short name T359
Test name
Test status
Simulation time 132729035472 ps
CPU time 541.74 seconds
Started Jan 14 01:33:57 PM PST 24
Finished Jan 14 01:42:59 PM PST 24
Peak memory 201332 kb
Host smart-c392ce60-8d4d-49c1-ac21-51bbd9397b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327559239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1327559239
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1457660149
Short name T624
Test name
Test status
Simulation time 23007264778 ps
CPU time 52.96 seconds
Started Jan 14 01:33:53 PM PST 24
Finished Jan 14 01:34:46 PM PST 24
Peak memory 200712 kb
Host smart-cb22be7b-f2d7-4d46-ac3e-852a4dfb22a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457660149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1457660149
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2019769960
Short name T596
Test name
Test status
Simulation time 4622951002 ps
CPU time 6.98 seconds
Started Jan 14 01:33:55 PM PST 24
Finished Jan 14 01:34:03 PM PST 24
Peak memory 200804 kb
Host smart-2ecf128b-04bf-4491-9d36-8239e949653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019769960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2019769960
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2203872223
Short name T629
Test name
Test status
Simulation time 6014342544 ps
CPU time 15.1 seconds
Started Jan 14 01:33:46 PM PST 24
Finished Jan 14 01:34:02 PM PST 24
Peak memory 200760 kb
Host smart-f8f0a712-59f7-454b-9a17-1379d375804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203872223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2203872223
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1310542555
Short name T111
Test name
Test status
Simulation time 331947330808 ps
CPU time 243.43 seconds
Started Jan 14 01:34:01 PM PST 24
Finished Jan 14 01:38:05 PM PST 24
Peak memory 200956 kb
Host smart-bd0d2e4f-497d-4739-8ccf-8817767162c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310542555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1310542555
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2711177360
Short name T623
Test name
Test status
Simulation time 306525252 ps
CPU time 0.96 seconds
Started Jan 14 01:34:01 PM PST 24
Finished Jan 14 01:34:03 PM PST 24
Peak memory 200696 kb
Host smart-cb93e81b-480c-4679-99a2-b78844a6bd8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711177360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2711177360
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.435423460
Short name T572
Test name
Test status
Simulation time 160602278908 ps
CPU time 95.31 seconds
Started Jan 14 01:33:50 PM PST 24
Finished Jan 14 01:35:26 PM PST 24
Peak memory 200940 kb
Host smart-f49d388d-b423-4253-a47a-bae2b491a06b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435423460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.435423460
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2559066097
Short name T191
Test name
Test status
Simulation time 331226699255 ps
CPU time 183.61 seconds
Started Jan 14 01:36:28 PM PST 24
Finished Jan 14 01:39:32 PM PST 24
Peak memory 200924 kb
Host smart-41221870-ac29-47c6-b4a7-b3cbc3571a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559066097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2559066097
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2213847796
Short name T24
Test name
Test status
Simulation time 326341455017 ps
CPU time 725.27 seconds
Started Jan 14 01:33:52 PM PST 24
Finished Jan 14 01:45:59 PM PST 24
Peak memory 200968 kb
Host smart-b16b8807-ec18-41e0-811c-8db40889e40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213847796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2213847796
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2016602221
Short name T573
Test name
Test status
Simulation time 477467207354 ps
CPU time 245.24 seconds
Started Jan 14 01:33:52 PM PST 24
Finished Jan 14 01:37:58 PM PST 24
Peak memory 200864 kb
Host smart-11fdbe2c-2f91-4e76-8c82-e33572662e2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016602221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2016602221
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.484659837
Short name T646
Test name
Test status
Simulation time 314990945393 ps
CPU time 708.08 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:45:45 PM PST 24
Peak memory 200892 kb
Host smart-ae8a5421-6d25-47a6-9c97-af764ad490b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484659837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.484659837
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.817995896
Short name T789
Test name
Test status
Simulation time 332329398395 ps
CPU time 401.63 seconds
Started Jan 14 01:33:57 PM PST 24
Finished Jan 14 01:40:40 PM PST 24
Peak memory 199484 kb
Host smart-97e7de1e-fe73-4471-9f75-dd5b3b1321cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=817995896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.817995896
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.512165011
Short name T611
Test name
Test status
Simulation time 323400013744 ps
CPU time 146.48 seconds
Started Jan 14 01:33:52 PM PST 24
Finished Jan 14 01:36:19 PM PST 24
Peak memory 200904 kb
Host smart-b82e9a3e-0801-4a7a-b5ad-f43d083c8741
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512165011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.512165011
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.263499138
Short name T18
Test name
Test status
Simulation time 126787171535 ps
CPU time 631.4 seconds
Started Jan 14 01:34:00 PM PST 24
Finished Jan 14 01:44:32 PM PST 24
Peak memory 201336 kb
Host smart-3405c2ae-d20a-4d19-b8fd-30a827b2a145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263499138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.263499138
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.400917687
Short name T433
Test name
Test status
Simulation time 46683241191 ps
CPU time 109.29 seconds
Started Jan 14 01:34:00 PM PST 24
Finished Jan 14 01:35:50 PM PST 24
Peak memory 200752 kb
Host smart-6b3140fa-55da-4fe6-a29c-bf836f259cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400917687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.400917687
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.608727352
Short name T497
Test name
Test status
Simulation time 5156545338 ps
CPU time 3.89 seconds
Started Jan 14 01:33:58 PM PST 24
Finished Jan 14 01:34:02 PM PST 24
Peak memory 200748 kb
Host smart-bb79cd82-24bd-49f3-a4ac-ca7a1e68dbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608727352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.608727352
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1822862100
Short name T655
Test name
Test status
Simulation time 5838303941 ps
CPU time 3.26 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:34:08 PM PST 24
Peak memory 200764 kb
Host smart-66a8ca6f-4e2b-4b8e-81f9-76ff39f73f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822862100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1822862100
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3195344399
Short name T263
Test name
Test status
Simulation time 323903511177 ps
CPU time 375.49 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:40:20 PM PST 24
Peak memory 200896 kb
Host smart-c5e4ebb7-975c-4243-9a39-325dba27807f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195344399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3195344399
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3150973201
Short name T269
Test name
Test status
Simulation time 390788788085 ps
CPU time 361.97 seconds
Started Jan 14 01:36:12 PM PST 24
Finished Jan 14 01:42:15 PM PST 24
Peak memory 209560 kb
Host smart-422d3c0f-b0af-4c12-9795-d5be06a1ff6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150973201 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3150973201
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2064462609
Short name T468
Test name
Test status
Simulation time 376960526 ps
CPU time 1.47 seconds
Started Jan 14 01:33:59 PM PST 24
Finished Jan 14 01:34:01 PM PST 24
Peak memory 200692 kb
Host smart-c0c07c48-f846-4f95-9353-9dd8fc794af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064462609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2064462609
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.4293927688
Short name T122
Test name
Test status
Simulation time 327963601549 ps
CPU time 192.62 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:37:10 PM PST 24
Peak memory 200916 kb
Host smart-2d51ce7b-0b00-42a8-ab63-1882f1851eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293927688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.4293927688
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2792022164
Short name T127
Test name
Test status
Simulation time 334539950843 ps
CPU time 777.32 seconds
Started Jan 14 01:34:01 PM PST 24
Finished Jan 14 01:46:59 PM PST 24
Peak memory 200968 kb
Host smart-72d3e904-9800-4d65-8e83-70a12df5d974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792022164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2792022164
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1036955730
Short name T202
Test name
Test status
Simulation time 163545962973 ps
CPU time 101.92 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:35:39 PM PST 24
Peak memory 200844 kb
Host smart-8d7d56b7-e09a-4dba-96cb-71dd2a378e1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036955730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1036955730
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.366265825
Short name T766
Test name
Test status
Simulation time 168149714170 ps
CPU time 29.21 seconds
Started Jan 14 01:34:00 PM PST 24
Finished Jan 14 01:34:30 PM PST 24
Peak memory 200908 kb
Host smart-b8b5239b-39ec-4b3c-ae68-026768548d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366265825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.366265825
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.809325710
Short name T546
Test name
Test status
Simulation time 482075856394 ps
CPU time 1136.66 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:52:54 PM PST 24
Peak memory 200928 kb
Host smart-53e73d5b-4080-4d5f-9bb2-645962a0cd4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=809325710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.809325710
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1792131928
Short name T555
Test name
Test status
Simulation time 342045147531 ps
CPU time 188.65 seconds
Started Jan 14 01:33:55 PM PST 24
Finished Jan 14 01:37:04 PM PST 24
Peak memory 200940 kb
Host smart-fd91cb3d-30f3-45c3-86aa-da6d0964e622
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792131928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1792131928
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1399853231
Short name T457
Test name
Test status
Simulation time 327978436460 ps
CPU time 756.98 seconds
Started Jan 14 01:33:59 PM PST 24
Finished Jan 14 01:46:37 PM PST 24
Peak memory 200872 kb
Host smart-99bda200-7fe0-4b4b-a73c-782f75316bba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399853231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1399853231
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2614186377
Short name T569
Test name
Test status
Simulation time 115915100337 ps
CPU time 427.27 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:41:04 PM PST 24
Peak memory 201372 kb
Host smart-b058f563-cd10-4842-9b96-9e65c0f6e061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614186377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2614186377
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2136604006
Short name T859
Test name
Test status
Simulation time 38979697514 ps
CPU time 95.65 seconds
Started Jan 14 01:34:02 PM PST 24
Finished Jan 14 01:35:38 PM PST 24
Peak memory 200740 kb
Host smart-6d281efb-e3a3-45ba-8924-218353887dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136604006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2136604006
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1339436171
Short name T587
Test name
Test status
Simulation time 5070843201 ps
CPU time 12.24 seconds
Started Jan 14 01:34:00 PM PST 24
Finished Jan 14 01:34:13 PM PST 24
Peak memory 200684 kb
Host smart-cd635c19-9340-49b7-9208-046c508519a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339436171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1339436171
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3898425057
Short name T857
Test name
Test status
Simulation time 5884250425 ps
CPU time 3.38 seconds
Started Jan 14 01:33:52 PM PST 24
Finished Jan 14 01:33:56 PM PST 24
Peak memory 200664 kb
Host smart-e713d065-3f68-4d1d-ac75-d5770f90821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898425057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3898425057
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3200347842
Short name T783
Test name
Test status
Simulation time 369414491215 ps
CPU time 417.62 seconds
Started Jan 14 01:34:03 PM PST 24
Finished Jan 14 01:41:02 PM PST 24
Peak memory 200944 kb
Host smart-d548dcf7-7462-41e7-bead-18e91e2c13fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200347842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3200347842
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.243481006
Short name T517
Test name
Test status
Simulation time 18068201467 ps
CPU time 29.99 seconds
Started Jan 14 01:33:56 PM PST 24
Finished Jan 14 01:34:26 PM PST 24
Peak memory 200864 kb
Host smart-e0d4a9d5-e158-40ed-b303-e3e4529130f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243481006 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.243481006
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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