Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6562	1			T12	20		T19	33		T20	20
testmodes[AdcCtrlTestmodeNormal]	5437	1			T12	4		T13	2		T14	2
testmodes[AdcCtrlTestmodeLowpower]	5610	1			T12	1		T13	1		T16	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3429	1			T12	19		T19	27		T20	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1681	1			T12	1		T19	4		T89	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1338	1			T19	1		T24	1		T38	17
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1674	1			T12	1		T19	6		T89	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2044	1			T12	1		T13	1		T14	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1391	1			T12	1		T13	1		T17	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1357	1			T38	11		T39	19		T43	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1373	1			T12	1		T17	1		T19	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2628	1			T16	2		T18	17		T41	16