Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19850

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

5662

1

T13

26

T14

10

T15

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19626

1

T6

2

T26

2

T31

1

auto[1]

5886

1

T12

17

T13

52

T14

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	98	1			T149	1		T198	1		T59	13
values[1]	621	1			T23	1		T24	14		T100	13
values[2]	611	1			T93	1		T164	11		T199	13
values[3]	904	1			T12	74		T14	23		T24	14
values[4]	577	1			T104	8		T105	1		T114	10
values[5]	758	1			T13	28		T17	21		T21	1
values[6]	569	1			T15	1		T17	25		T35	11
values[7]	657	1			T13	26		T14	10		T17	12
values[8]	595	1			T13	24		T106	18		T100	3
values[9]	3431	1			T16	12		T19	1		T22	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	832	1			T24	14		T93	1		T100	13
values[1]	2836	1			T12	57		T14	23		T16	12
values[2]	687	1			T12	17		T92	22		T105	20
values[3]	742	1			T21	1		T22	1		T104	17
values[4]	617	1			T13	28		T15	1		T17	21
values[5]	622	1			T17	25		T35	11		T86	6
values[6]	706	1			T13	26		T14	10		T17	12
values[7]	591	1			T106	21		T164	11		T112	9
values[8]	1012	1			T13	24		T19	1		T22	1
values[9]	175	1			T107	1		T200	15		T201	14
minimum	16692	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T202	8		T113	1		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T24	1		T93	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T12	30		T14	13		T24	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1273	1			T16	12		T203	3		T111	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	9		T105	1		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T92	10		T105	1		T106	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T21	1		T105	1		T36	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T22	1		T104	17		T43	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	12		T204	16		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	1		T17	10		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T86	1		T96	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T17	13		T35	3		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T17	7		T100	1		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	13		T14	3		T204	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T106	3		T205	1		T94	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T106	10		T164	11		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T13	12		T62	1		T164	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T19	1		T22	1		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T200	7		T201	10		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T107	1		T206	18		T207	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16565	1			T12	20		T18	18		T19	44
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T99	9		T156	1		T208	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T24	13		T100	12		T209	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	27		T14	10		T24	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1072	1			T210	10		T211	15		T212	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	8		T150	14		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T92	12		T105	18		T106	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T105	4		T36	11		T87	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T43	2		T36	11		T44	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	16		T204	8		T102	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T17	11		T98	20		T116	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T86	5		T181	9		T114	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	12		T35	8		T214	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T17	5		T100	2		T209	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	13		T14	7		T204	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T205	2		T94	9		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T106	8		T112	8		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T13	12		T62	15		T114	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T216	15		T115	12		T217	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T200	8		T201	4		T218	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T206	13		T207	6		T219	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T149	1		T198	1		T59	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T220	2		T221	12		T222	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T23	1		T202	8		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T24	1		T100	1		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T94	13		T98	2		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T93	1		T164	11		T199	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	39		T14	13		T24	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T92	10		T105	1		T106	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T105	1		T114	6		T223	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T104	8		T44	3		T103	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	12		T21	1		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	10		T22	1		T104	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T86	1		T96	1		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	1		T17	13		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T17	7		T133	12		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	13		T14	3		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	12		T100	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T106	10		T44	1		T204	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T62	1		T106	3		T164	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1494	1			T16	12		T19	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T59	1		T224	4		T225	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T221	12		T222	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T99	9		T156	1		T208	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T24	13		T100	12		T209	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T94	12		T116	8		T59	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T102	6		T107	13		T226	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	35		T14	10		T24	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T92	12		T105	18		T106	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T114	4		T142	14		T227	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T44	11		T217	8		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	16		T105	4		T36	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	11		T43	2		T36	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T86	5		T102	13		T209	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	12		T35	8		T214	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T17	5		T133	14		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	13		T14	7		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T13	12		T100	2		T209	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T106	8		T44	1		T204	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T62	15		T205	2		T94	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1246	1			T112	8		T210	10		T211	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T202	1		T113	1		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T24	14		T93	1		T100	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T12	29		T14	11		T24	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1411	1			T16	3		T203	3		T111	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	11		T105	1		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T92	13		T105	19		T106	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T21	1		T105	5		T36	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T22	1		T104	3		T43	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	17		T204	9		T102	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	1		T17	12		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T86	6		T96	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T17	13		T35	9		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T17	6		T100	3		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	14		T14	8		T204	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T106	1		T205	3		T94	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T106	9		T164	1		T112	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T13	13		T62	16		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T19	1		T22	1		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T200	9		T201	5		T148	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T107	1		T206	14		T207	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16692	1			T6	2		T26	2		T31	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T202	7		T230	6		T208	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T209	11		T120	9		T231	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	28		T14	12		T24	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	934	1			T16	9		T111	12		T164	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T12	6		T223	9		T228	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T92	9		T106	13		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T36	10		T87	3		T114	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T104	14		T43	5		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	11		T204	15		T117	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T17	9		T98	4		T116	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T181	13		T114	9		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	12		T35	2		T116	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	6		T209	11		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	12		T14	2		T204	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T106	2		T94	7		T182	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T106	9		T164	10		T213	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	11		T164	1		T114	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T199	4		T115	13		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T200	6		T201	9		T218	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T206	17		T207	7		T233	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T149	1		T198	1		T59	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T220	2		T221	13		T222	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T23	1		T202	1		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T24	14		T100	13		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T94	13		T98	1		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T93	1		T164	1		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	40		T14	11		T24	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T92	13		T105	19		T106	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T105	1		T114	5		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T104	2		T44	14		T103	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	17		T21	1		T105	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T17	12		T22	1		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T86	6		T96	1		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	1		T17	13		T35	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	6		T133	15		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	14		T14	8		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	13		T100	3		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T106	9		T44	2		T204	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T62	16		T106	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1626	1			T16	3		T19	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T59	11		T225	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T221	11		T222	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T202	7		T230	6		T208	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T209	11		T120	9		T231	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T94	12		T98	1		T116	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T164	10		T199	12		T234	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	34		T14	12		T24	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T92	9		T106	13		T133	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T114	5		T223	9		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T104	6		T217	7		T228	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	11		T36	10		T87	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	9		T104	8		T43	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T209	12		T232	10		T235	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T17	12		T35	2		T116	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T17	6		T133	11		T55	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	12		T14	2		T236	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	11		T209	11		T180	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T106	9		T204	2		T237	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T106	2		T164	1		T94	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1114	1			T16	9		T111	12		T164	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21753

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3759

1

T12

74

T13

28

T14

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19866

1

T6

2

T26

2

T31

1

auto[1]

5646

1

T12

57

T13

54

T14

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	250	1			T101	1		T133	20		T44	2
values[0]	1	1			T238	1		-	-		-	-
values[1]	751	1			T13	26		T19	1		T22	1
values[2]	853	1			T12	17		T15	1		T100	10
values[3]	548	1			T14	10		T164	11		T94	25
values[4]	642	1			T24	14		T104	8		T36	22
values[5]	2841	1			T16	12		T93	1		T105	19
values[6]	655	1			T12	57		T14	23		T106	18
values[7]	577	1			T17	21		T22	1		T92	22
values[8]	526	1			T13	52		T17	25		T23	1
values[9]	1177	1			T17	12		T21	1		T104	9
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	736	1			T13	26		T15	1		T24	14
values[1]	749	1			T100	10		T98	1		T133	26
values[2]	682	1			T12	17		T14	10		T24	14
values[3]	2664	1			T16	12		T104	8		T93	1
values[4]	755	1			T12	57		T105	19		T106	3
values[5]	632	1			T14	23		T22	1		T106	18
values[6]	636	1			T17	21		T92	22		T43	10
values[7]	568	1			T13	52		T17	37		T21	1
values[8]	983	1			T104	9		T35	11		T199	13
values[9]	208	1			T101	1		T133	20		T44	2
minimum	16899	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	13		T15	1		T24	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T105	1		T164	11		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T98	1		T102	1		T209	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T100	1		T133	12		T204	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	3		T94	13		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	9		T24	12		T164	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T16	12		T203	3		T111	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T104	8		T93	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T113	1		T216	1		T98	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	30		T105	1		T106	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T106	10		T100	1		T202	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	13		T22	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T209	13		T217	8		T240	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	10		T92	10		T43	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	12		T21	1		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	12		T17	20		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T104	9		T35	3		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T199	13		T36	6		T209	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T101	1		T108	5		T241	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T133	9		T44	1		T118	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16625	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T19	1		T106	14		T205	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	13		T24	13		T62	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T87	5		T181	9		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T102	6		T209	10		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T100	9		T133	14		T204	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	7		T94	12		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	8		T24	2		T94	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T210	10		T211	15		T212	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T36	11		T98	20		T214	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T216	15		T180	8		T213	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	27		T105	18		T115	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T106	8		T100	12		T86	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	10		T114	10		T204	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T209	10		T217	8		T240	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	11		T92	12		T43	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T13	12		T105	4		T112	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	16		T17	17		T100	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T35	8		T217	10		T231	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T36	11		T209	2		T182	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T108	9		T241	3		T242	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T133	11		T44	1		T118	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T106	14		T205	2		T137	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T101	1		T108	5		T243	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T133	9		T44	1		T129	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T238	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	13		T22	1		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T19	1		T105	1		T106	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T15	1		T209	12		T217	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	9		T100	1		T164	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	3		T94	13		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T164	11		T116	11		T208	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T113	1		T96	1		T114	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T24	12		T104	8		T36	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T16	12		T203	3		T111	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T93	1		T105	1		T106	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T106	10		T100	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	30		T14	13		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T202	8		T86	1		T217	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	10		T22	1		T92	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	12		T23	1		T105	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	12		T17	13		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T21	1		T104	9		T35	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T17	7		T199	13		T36	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T108	9		T243	4		T244	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T133	11		T44	1		T221	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	13		T24	13		T62	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T106	14		T205	2		T87	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T209	10		T217	10		T200	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	8		T100	9		T181	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	7		T94	12		T102	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T116	10		T208	1		T53	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T114	10		T102	13		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T24	2		T36	11		T94	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T210	10		T211	15		T212	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T105	18		T115	12		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T106	8		T100	12		T150	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	27		T14	10		T114	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T86	5		T217	8		T127	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	11		T92	12		T43	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	12		T105	4		T209	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	16		T17	12		T100	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T35	8		T112	8		T217	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T17	5		T36	11		T209	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1