Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21894

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3618

1

T12

74

T13

50

T14

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19732

1

T6

2

T26

2

T31

1

auto[1]

5780

1

T12

57

T13

54

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	29	1			T109	1		T301	13		T137	15
values[0]	70	1			T87	11		T198	8		T117	8
values[1]	493	1			T15	1		T113	1		T95	1
values[2]	840	1			T12	57		T202	8		T37	1
values[3]	603	1			T14	10		T93	1		T105	1
values[4]	728	1			T13	24		T62	16		T104	16
values[5]	2658	1			T13	28		T16	12		T17	12
values[6]	888	1			T17	25		T24	14		T164	2
values[7]	602	1			T13	26		T19	1		T22	1
values[8]	702	1			T12	17		T104	1		T92	22
values[9]	1208	1			T14	23		T17	21		T21	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	718	1			T15	1		T113	1		T95	1
values[1]	726	1			T12	57		T105	1		T202	8
values[2]	830	1			T13	24		T14	10		T93	1
values[3]	2623	1			T16	12		T24	14		T104	7
values[4]	739	1			T13	28		T24	14		T62	16
values[5]	728	1			T13	26		T17	37		T19	1
values[6]	686	1			T12	17		T22	1		T100	3
values[7]	686	1			T23	1		T104	1		T92	22
values[8]	836	1			T21	1		T22	1		T105	19
values[9]	247	1			T14	23		T17	21		T114	42
minimum	16693	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	1		T113	1		T87	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T95	1		T107	12		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T181	14		T209	12		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	30		T105	1		T202	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T93	1		T106	3		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T13	12		T14	3		T106	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T16	12		T24	1		T203	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T104	7		T105	1		T164	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	12		T24	12		T199	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T62	1		T104	9		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T19	1		T239	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	13		T17	20		T164	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T112	1		T86	1		T149	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	9		T22	1		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T23	1		T104	1		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T92	10		T106	14		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T21	1		T22	1		T105	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T216	1		T98	2		T204	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T114	10		T230	11		T247	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T14	13		T17	10		T114	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T302	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T87	5		T133	14		T217	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T107	13		T229	10		T235	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T181	9		T209	10		T115	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	27		T209	2		T156	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T44	1		T255	7		T280	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	12		T14	7		T106	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1099	1			T24	13		T100	12		T36	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T105	4		T143	17		T240	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	16		T24	2		T94	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T62	15		T44	11		T120	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T98	20		T133	11		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	13		T17	17		T102	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T112	8		T86	5		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	8		T100	2		T217	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T100	9		T35	8		T217	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T92	12		T106	14		T182	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T105	18		T198	5		T268	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T216	15		T204	8		T99	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T114	10		T247	7		T303	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T14	10		T17	11		T114	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T301	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T109	1		T137	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T87	6		T198	1		T123	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T117	8		T148	1		T130	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T113	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T95	1		T229	1		T235	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T181	14		T209	12		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	30		T202	8		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T93	1		T134	11		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	3		T105	1		T36	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T106	3		T100	1		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	12		T62	1		T104	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T13	12		T16	12		T24	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	7		T93	1		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T24	12		T199	5		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T17	13		T164	2		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T19	1		T112	1		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	13		T22	1		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T104	1		T100	1		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	9		T92	10		T106	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T21	1		T22	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T14	13		T17	10		T216	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T301	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T137	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T87	5		T198	7		T123	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T130	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T133	14		T217	8		T228	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T229	10		T235	3		T261	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T181	9		T209	10		T115	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	27		T156	1		T107	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T134	8		T255	7		T280	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	7		T36	11		T209	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T100	12		T36	11		T114	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	12		T62	15		T106	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T13	16		T24	13		T210	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T17	5		T105	4		T44	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T24	2		T98	20		T133	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T17	12		T102	6		T214	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T112	8		T86	5		T180	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	13		T100	2		T217	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T100	9		T35	8		T217	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	8		T92	12		T106	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T105	18		T114	10		T198	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T14	10		T17	11		T216	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	1		T113	1		T87	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T95	1		T107	14		T229	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T181	10		T209	11		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	29		T105	1		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T93	1		T106	1		T44	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	13		T14	8		T106	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T16	3		T24	14		T203	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T104	1		T105	5		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	17		T24	3		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T62	16		T104	1		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T19	1		T239	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	14		T17	19		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T112	9		T86	6		T149	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	11		T22	1		T100	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T23	1		T104	1		T100	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T92	13		T106	15		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T21	1		T22	1		T105	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T216	16		T98	1		T204	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T114	11		T230	1		T247	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T14	11		T17	12		T114	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T302	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T87	3		T133	11		T217	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T107	11		T235	8		T117	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T181	13		T209	11		T115	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	28		T202	7		T209	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T106	2		T255	6		T291	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	11		T14	2		T106	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T16	9		T111	12		T36	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T104	6		T164	10		T199	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	11		T24	11		T199	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T104	8		T120	21		T57	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T98	4		T133	8		T117	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	12		T17	18		T164	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T149	4		T116	15		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	6		T164	10		T217	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T35	2		T59	11		T236	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T92	9		T106	13		T182	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T180	4		T213	2		T129	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T98	1		T204	15		T245	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T114	9		T230	10		T247	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T14	12		T17	9		T114	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T301	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T109	1		T137	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T87	8		T198	8		T123	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T117	1		T148	1		T130	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	1		T113	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T95	1		T229	11		T235	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T181	10		T209	11		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	29		T202	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T93	1		T134	9		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	8		T105	1		T36	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T106	1		T100	13		T36	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	13		T62	16		T104	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T13	17		T16	3		T24	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T17	6		T93	1		T105	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T24	3		T199	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T17	13		T164	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T19	1		T112	9		T86	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	14		T22	1		T100	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T104	1		T100	10		T35	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	11		T92	13		T106	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T21	1		T22	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	426	1			T14	11		T17	12		T216	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T301	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T87	3		T304	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T117	7		T130	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T133	11		T217	7		T223	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T235	8		T128	9		T261	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T181	13		T209	11		T115	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	28		T202	7		T107	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T134	10		T255	6		T291	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	2		T36	10		T209	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T106	2		T36	5		T114	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	11		T104	14		T106	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T13	11		T16	9		T111	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	6		T164	10		T120	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T24	11		T199	4		T98	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T17	12		T164	1		T57	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T302	2		T305	1		T119	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	12		T164	10		T217	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T35	2		T149	4		T116	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	6		T92	9		T106	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T114	9		T230	10		T236	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T14	12		T17	9		T114	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14