Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21843

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3669

1

T12

57

T13

50

T14

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19952

1

T6

2

T26

2

T31

1

auto[1]

5560

1

T12

57

T13

24

T14

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	280	1			T15	1		T22	1		T93	1
values[0]	4	1			T97	1		T44	2		T238	1
values[1]	786	1			T24	14		T104	1		T106	28
values[2]	474	1			T14	23		T105	20		T96	1
values[3]	477	1			T17	25		T105	5		T164	11
values[4]	2852	1			T13	28		T16	12		T104	9
values[5]	668	1			T13	24		T17	12		T22	1
values[6]	789	1			T104	7		T199	5		T36	17
values[7]	843	1			T12	17		T23	1		T24	14
values[8]	734	1			T12	57		T13	26		T14	10
values[9]	914	1			T19	1		T62	16		T93	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	688	1			T104	1		T105	19		T106	28
values[1]	439	1			T14	23		T105	6		T97	1
values[2]	561	1			T13	28		T17	25		T164	13
values[3]	2907	1			T16	12		T104	9		T106	18
values[4]	621	1			T13	24		T17	12		T22	1
values[5]	773	1			T12	17		T23	1		T104	7
values[6]	861	1			T13	26		T14	10		T21	1
values[7]	690	1			T12	57		T17	21		T19	1
values[8]	932	1			T22	1		T62	16		T93	2
values[9]	100	1			T15	1		T36	22		T232	13
minimum	16940	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T104	1		T106	14		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T105	1		T202	8		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	13		T105	1		T97	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T105	1		T223	10		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	12		T164	11		T230	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T17	13		T164	2		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T16	12		T104	9		T106	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T239	1		T209	13		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T100	1		T113	1		T209	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	12		T17	7		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T12	9		T104	7		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T23	1		T199	5		T94	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T24	1		T114	10		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T13	13		T14	3		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T19	1		T106	3		T209	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	30		T17	10		T86	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T22	1		T93	1		T100	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T62	1		T93	1		T199	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T36	11		T232	11		T117	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T15	1		T306	1		T275	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16620	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T24	12		T97	1		T114	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T106	14		T204	11		T217	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T105	18		T102	13		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T14	10		T105	4		T228	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T237	9		T250	9		T152	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	16		T201	10		T127	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T17	12		T134	8		T200	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T106	8		T112	8		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T209	10		T99	9		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T100	9		T209	2		T200	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	12		T17	5		T92	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	8		T36	11		T216	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T94	12		T102	6		T259	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T24	13		T114	10		T226	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	13		T14	7		T43	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T209	10		T217	8		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	27		T17	11		T86	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T100	14		T35	8		T215	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T62	15		T87	5		T44	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T36	11		T232	2		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T306	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T24	2		T114	14		T278	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T22	1		T100	1		T164	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T15	1		T93	1		T199	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T44	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T97	1		T238	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T104	1		T106	14		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T24	12		T202	8		T114	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	13		T97	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T105	2		T96	1		T223	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T105	1		T164	11		T98	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T17	13		T107	1		T200	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T13	12		T16	12		T104	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T239	1		T164	2		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T100	1		T205	1		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	12		T17	7		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T104	7		T36	6		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T199	5		T94	13		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	9		T24	1		T114	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T23	1		T43	8		T94	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T209	12		T103	2		T217	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	30		T13	13		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T19	1		T93	1		T106	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T62	1		T87	6		T44	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T100	12		T307	9		T256	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T227	8		T207	5		T192	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T44	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T106	14		T204	19		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T24	2		T114	14		T102	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	10		T228	2		T59	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T105	18		T231	12		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T105	4		T228	9		T206	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	12		T200	8		T53	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T13	16		T106	8		T112	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T99	9		T134	8		T198	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T100	9		T205	2		T209	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	12		T17	5		T92	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T36	11		T216	15		T98	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T94	12		T116	10		T259	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	8		T24	13		T114	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T43	2		T94	9		T181	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T209	10		T217	8		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	27		T13	13		T14	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T100	2		T35	8		T36	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T62	15		T87	5		T44	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T104	1		T106	15		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T105	19		T202	1		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	11		T105	5		T97	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T105	1		T223	1		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	17		T164	1		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	13		T164	1		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T16	3		T104	1		T106	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T239	1		T209	11		T99	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T100	10		T113	1		T209	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	13		T17	6		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	11		T104	1		T36	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T23	1		T199	1		T94	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T24	14		T114	11		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T13	14		T14	8		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T19	1		T106	1		T209	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	29		T17	12		T86	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T22	1		T93	1		T100	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T62	16		T93	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T36	12		T232	3		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T15	1		T306	11		T275	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16752	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T24	3		T97	1		T114	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T106	13		T204	2		T217	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T202	7		T231	14		T126	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T14	12		T98	1		T228	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T223	9		T237	9		T152	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	11		T164	10		T230	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	12		T164	1		T134	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T16	9		T104	8		T106	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T209	12		T143	15		T57	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T209	11		T150	6		T237	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	11		T17	6		T92	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	6		T104	6		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T199	4		T94	12		T128	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T114	9		T227	11		T226	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	12		T14	2		T43	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T106	2		T209	11		T217	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	28		T17	9		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T35	2		T164	10		T182	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T199	12		T87	3		T116	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T36	10		T232	10		T117	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T275	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T204	15		T256	10		T285	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T24	11		T114	16		T278	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T22	1		T100	13		T164	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T15	1		T93	1		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T44	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T97	1		T238	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T104	1		T106	15		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T24	3		T202	1		T114	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	11		T97	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T105	20		T96	1		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T105	5		T164	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	13		T107	1		T200	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1418	1			T13	17		T16	3		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T239	1		T164	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T100	10		T205	3		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	13		T17	6		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T104	1		T36	12		T216	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T199	1		T94	13		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	11		T24	14		T114	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T23	1		T43	5		T94	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T209	11		T103	2		T217	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	29		T13	14		T14	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T19	1		T93	1		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T62	16		T87	8		T44	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T164	10		T307	10		T256	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T199	12		T227	10		T207	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T106	13		T204	17		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T24	11		T202	7		T114	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	12		T228	9		T59	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T223	9		T231	14		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T164	10		T98	1		T230	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T17	12		T200	6		T53	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T13	11		T16	9		T104	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T164	1		T134	10		T57	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T209	11		T150	6		T291	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	11		T17	6		T92	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T104	6		T36	5		T98	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T199	4		T94	12		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	6		T114	9		T245	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T43	5		T94	7		T181	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T209	11		T217	7		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	28		T13	12		T14	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T106	2		T35	2		T36	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T87	3		T234	7		T116	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14