Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22010

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3502

1

T12

57

T13

26

T14

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19680

1

T6

2

T26

2

T31

1

auto[1]

5832

1

T12

74

T13

50

T14

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T198	6		T308	1		T309	12
values[0]	44	1			T116	21		T278	6		T251	15
values[1]	739	1			T24	14		T93	2		T100	3
values[2]	2580	1			T14	23		T16	12		T17	12
values[3]	929	1			T13	24		T104	1		T105	19
values[4]	620	1			T12	17		T13	26		T199	13
values[5]	651	1			T12	57		T21	1		T23	1
values[6]	636	1			T15	1		T62	16		T44	2
values[7]	731	1			T14	10		T22	1		T24	14
values[8]	678	1			T13	28		T19	1		T22	1
values[9]	1194	1			T17	46		T92	22		T105	5
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	909	1			T24	14		T93	2		T43	10
values[1]	2656	1			T16	12		T17	12		T105	20
values[2]	803	1			T13	24		T14	23		T104	1
values[3]	883	1			T12	74		T13	26		T21	1
values[4]	520	1			T23	1		T104	7		T106	28
values[5]	546	1			T14	10		T15	1		T62	16
values[6]	826	1			T13	28		T22	1		T24	14
values[7]	610	1			T19	1		T22	1		T104	9
values[8]	812	1			T17	46		T92	22		T105	5
values[9]	242	1			T199	5		T95	1		T133	20
minimum	16705	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T43	8		T114	6		T204	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T24	1		T93	2		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T16	12		T105	1		T203	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T17	7		T105	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T13	12		T216	1		T209	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	13		T104	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	9		T21	1		T199	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T12	30		T13	13		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T104	7		T164	11		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T23	1		T106	14		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	1		T62	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	3		T94	8		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	12		T114	10		T209	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T22	1		T24	12		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	1		T106	10		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T19	1		T104	9		T36	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T105	1		T100	1		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T17	23		T92	10		T106	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T199	5		T133	9		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T95	1		T142	1		T292	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T253	3		T310	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T43	2		T114	4		T204	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T24	13		T204	8		T149	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T112	8		T210	10		T211	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	5		T105	18		T100	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	12		T216	15		T209	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	10		T217	10		T200	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	8		T98	20		T133	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	27		T13	13		T114	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T36	11		T94	12		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T106	14		T208	1		T259	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T62	15		T102	13		T53	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	7		T94	9		T294	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	16		T114	10		T209	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T24	2		T205	2		T181	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T106	8		T100	12		T86	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	11		T228	2		T245	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T105	4		T100	9		T35	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	23		T92	12		T87	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T133	11		T182	6		T198	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T142	14		T292	13		T219	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T253	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T198	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T308	1		T309	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T116	11		T311	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T278	3		T251	15		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T43	8		T204	3		T234	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T24	1		T93	2		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T16	12		T105	1		T203	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	13		T17	7		T164	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T13	12		T95	1		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T104	1		T105	1		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	9		T199	13		T98	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	13		T97	1		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T21	1		T104	7		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	30		T23	1		T106	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	1		T62	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T208	3		T127	1		T294	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T97	1		T102	1		T209	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	3		T22	1		T24	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	12		T22	1		T106	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T19	1		T104	9		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T105	1		T100	2		T35	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T17	23		T92	10		T106	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T198	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T116	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T278	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T43	2		T204	11		T217	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T24	13		T100	2		T149	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T112	8		T210	10		T211	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	10		T17	5		T204	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	12		T216	15		T133	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T105	18		T217	10		T201	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	8		T98	20		T201	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	13		T107	13		T228	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T36	11		T94	12		T115	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	27		T106	14		T114	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T62	15		T44	1		T121	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T208	1		T127	17		T294	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T102	13		T209	2		T53	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	7		T24	2		T94	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	16		T106	8		T86	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T36	11		T205	2		T181	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T105	4		T100	21		T35	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T17	23		T92	12		T87	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T43	5		T114	5		T204	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T24	14		T93	2		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T16	3		T105	1		T203	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	6		T105	19		T100	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T13	13		T216	16		T209	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	11		T104	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	11		T21	1		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	29		T13	14		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T104	1		T164	1		T36	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T23	1		T106	15		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	1		T62	16		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	8		T94	10		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	17		T114	11		T209	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T22	1		T24	3		T205	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T22	1		T106	9		T100	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	1		T104	1		T36	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T105	5		T100	10		T35	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	25		T92	13		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T199	1		T133	12		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T95	1		T142	15		T292	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T253	11		T310	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T43	5		T114	5		T204	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T204	15		T149	4		T228	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	895	1			T16	9		T111	12		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	6		T164	1		T209	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	11		T209	11		T230	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	12		T217	10		T200	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	6		T199	12		T98	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	28		T13	12		T114	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T104	6		T164	10		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T106	13		T208	1		T242	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T53	8		T313	12		T249	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	2		T94	7		T291	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	11		T114	9		T209	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T24	11		T181	13		T256	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T106	9		T223	9		T59	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T104	8		T36	10		T230	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	2		T164	10		T116	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	21		T92	9		T106	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T199	4		T133	8		T182	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T292	15		T314	8		T297	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T253	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T198	6		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T308	1		T309	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T116	11		T311	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T278	4		T251	1		T312	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	5		T204	12		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T24	14		T93	2		T100	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T16	3		T105	1		T203	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	11		T17	6		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T13	13		T95	1		T216	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T104	1		T105	19		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	11		T199	1		T98	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	14		T97	1		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T21	1		T104	1		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	29		T23	1		T106	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	1		T62	16		T44	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T208	3		T127	18		T294	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T97	1		T102	14		T209	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	8		T22	1		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	17		T22	1		T106	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T19	1		T104	1		T36	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	400	1			T105	5		T100	23		T35	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T17	25		T92	13		T106	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T309	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T116	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T278	2		T251	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T43	5		T204	2		T234	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T149	4		T228	9		T120	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T16	9		T111	12		T246	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	12		T17	6		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	11		T133	11		T209	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T217	10		T57	13		T201	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	6		T199	12		T98	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	12		T107	11		T200	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T104	6		T164	10		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	28		T106	13		T114	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T313	12		T249	2		T221	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T208	1		T247	11		T305	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T209	11		T228	10		T53	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	2		T24	11		T94	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	11		T106	9		T114	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T104	8		T36	10		T181	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T35	2		T164	10		T199	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T17	21		T92	9		T106	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14