Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22154

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3358

1

T12

74

T13

54

T14

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19906

1

T6

2

T26

2

T31

1

auto[1]

5606

1

T13

28

T14

23

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	182	1			T55	1		T57	12		T108	1
values[0]	58	1			T62	16		T239	1		T258	24
values[1]	820	1			T12	57		T100	10		T164	13
values[2]	633	1			T13	50		T17	12		T21	1
values[3]	925	1			T105	19		T106	28		T94	17
values[4]	787	1			T14	10		T22	1		T100	3
values[5]	641	1			T17	21		T19	1		T24	14
values[6]	496	1			T14	23		T93	1		T35	11
values[7]	622	1			T22	1		T36	22		T113	1
values[8]	573	1			T12	17		T15	1		T92	22
values[9]	3084	1			T13	28		T16	12		T17	25
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	785	1			T12	57		T13	26		T24	14
values[1]	797	1			T13	24		T17	12		T21	1
values[2]	816	1			T106	28		T94	17		T216	16
values[3]	783	1			T14	10		T22	1		T104	7
values[4]	577	1			T17	21		T19	1		T24	14
values[5]	550	1			T14	23		T93	1		T35	11
values[6]	2727	1			T16	12		T22	1		T203	3
values[7]	605	1			T12	17		T15	1		T92	22
values[8]	893	1			T13	28		T17	25		T23	1
values[9]	73	1			T57	12		T268	17		T278	6
minimum	16906	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T24	1		T164	2		T114	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	30		T13	13		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	12		T21	1		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	7		T95	1		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T106	14		T94	8		T114	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T216	1		T44	1		T102	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T105	1		T100	1		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	3		T22	1		T104	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	10		T93	1		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T19	1		T24	12		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	13		T93	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T35	3		T199	13		T107	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T16	12		T203	3		T111	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	1		T95	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	1		T92	10		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	9		T164	11		T96	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T17	13		T23	1		T104	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	12		T87	6		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T57	12		T278	3		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T268	1		T218	7		T316	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16610	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T62	1		T164	11		T112	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T24	13		T114	4		T44	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	27		T13	13		T100	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	12		T105	18		T106	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T17	5		T98	20		T116	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T106	14		T94	9		T114	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T216	15		T44	1		T102	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T105	4		T100	2		T133	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	7		T232	2		T55	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T17	11		T100	12		T43	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T24	2		T133	11		T200	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	10		T204	11		T102	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T35	8		T107	13		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T36	11		T210	10		T211	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T198	7		T245	1		T121	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T92	12		T36	11		T274	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	8		T136	6		T317	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	12		T86	5		T116	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	16		T87	5		T204	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T278	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T268	16		T218	7		T316	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T62	15		T112	8		T205	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T55	1		T57	12		T108	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T241	13		T318	1		T218	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T258	13		T265	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T62	1		T239	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T164	2		T114	6		T44	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T12	30		T100	1		T164	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	12		T21	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	13		T17	7		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T105	1		T106	14		T94	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T95	1		T98	10		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T100	1		T209	13		T53	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	3		T22	1		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T17	10		T93	1		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T19	1		T24	12		T104	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	13		T93	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T35	3		T199	13		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T36	11		T113	1		T228	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T22	1		T97	1		T234	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	1		T92	10		T36	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	9		T164	11		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T16	12		T17	13		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T13	12		T96	1		T87	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T278	3		T247	13		T244	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T241	15		T318	1		T218	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T258	11		T265	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T62	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T114	4		T44	11		T217	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	27		T100	9		T112	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	12		T24	13		T106	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	13		T17	5		T116	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T105	18		T106	14		T94	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T98	20		T44	1		T102	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T100	2		T209	10		T53	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	7		T216	15		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T17	11		T105	4		T100	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T24	2		T133	11		T232	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	10		T204	11		T102	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T35	8		T107	13		T227	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	11		T228	2		T150	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T198	7		T245	1		T261	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T92	12		T36	11		T259	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	8		T121	2		T319	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T17	12		T210	10		T86	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	16		T87	5		T204	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T24	14		T164	1		T114	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	29		T13	14		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	13		T21	1		T105	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T17	6		T95	1		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T106	15		T94	10		T114	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T216	16		T44	2		T102	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T105	5		T100	3		T133	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	8		T22	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T17	12		T93	1		T100	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T19	1		T24	3		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	11		T93	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T35	9		T199	1		T107	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T16	3		T203	3		T111	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	1		T95	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	1		T92	13		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	11		T164	1		T96	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T17	13		T23	1		T104	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T13	17		T87	8		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T57	1		T278	4		T315	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T268	17		T218	8		T316	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16726	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T62	16		T164	1		T112	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T164	1		T114	5		T217	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	28		T13	12		T181	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	11		T106	11		T202	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T17	6		T98	4		T116	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T106	13		T94	7		T114	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T209	11		T217	10		T223	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T133	11		T209	12		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	2		T104	6		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T17	9		T199	4		T43	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T24	11		T133	8		T200	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	12		T204	2		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T35	2		T199	12		T107	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T16	9		T111	12		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T234	7		T245	1		T126	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T92	9		T36	5		T274	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	6		T164	10		T236	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T17	12		T104	8		T116	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	11		T87	3		T204	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T57	11		T278	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T218	6		T316	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T57	8		T161	10		T265	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T164	10		T94	12		T134	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T55	1		T57	1		T108	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T241	16		T318	2		T218	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T258	12		T265	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T62	16		T239	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T164	1		T114	5		T44	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	29		T100	10		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	13		T21	1		T24	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	14		T17	6		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T105	19		T106	15		T94	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T95	1		T98	26		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T100	3		T209	11		T53	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	8		T22	1		T216	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T17	12		T93	1		T105	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T19	1		T24	3		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	11		T93	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T35	9		T199	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	12		T113	1		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T22	1		T97	1		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	1		T92	13		T36	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	11		T164	1		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T16	3		T17	13		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T13	17		T96	1		T87	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T57	11		T278	2		T247	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T241	12		T218	6		T183	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T258	12		T265	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T164	1		T114	5		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	28		T164	10		T94	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	11		T106	11		T202	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	12		T17	6		T98	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T106	13		T94	7		T114	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T98	4		T209	11		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T209	12		T53	8		T237	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	2		T55	10		T59	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	9		T199	4		T43	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T24	11		T104	6		T133	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T14	12		T204	2		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T35	2		T199	12		T107	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T36	10		T228	6		T150	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T234	7		T245	1		T57	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T92	9		T36	5		T256	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	6		T164	10		T126	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T16	9		T17	12		T104	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	11		T87	3		T204	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14