Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21992

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3520

1

T12

74

T13

50

T14

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19681

1

T6

2

T26

2

T31

1

auto[1]

5831

1

T12

74

T13

54

T16

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	262	1			T22	1		T216	16		T114	42
values[0]	61	1			T87	11		T117	8		T123	3
values[1]	497	1			T15	1		T113	1		T95	1
values[2]	818	1			T12	57		T105	1		T202	8
values[3]	593	1			T14	10		T93	1		T36	22
values[4]	762	1			T13	24		T62	16		T104	7
values[5]	2671	1			T13	28		T16	12		T24	28
values[6]	906	1			T17	37		T239	1		T164	2
values[7]	584	1			T12	17		T13	26		T19	1
values[8]	705	1			T104	1		T92	22		T106	28
values[9]	962	1			T14	23		T17	21		T21	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	576	1			T15	1		T113	1		T133	26
values[1]	712	1			T12	57		T105	1		T202	8
values[2]	816	1			T13	24		T14	10		T93	1
values[3]	2614	1			T16	12		T24	14		T104	7
values[4]	699	1			T13	28		T24	14		T62	16
values[5]	784	1			T13	26		T17	37		T19	1
values[6]	645	1			T12	17		T22	1		T100	3
values[7]	669	1			T23	1		T104	1		T92	22
values[8]	915	1			T14	23		T21	1		T105	19
values[9]	188	1			T17	21		T22	1		T114	20
minimum	16894	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T113	1		T133	12		T223	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	1		T217	8		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T181	14		T209	12		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	30		T105	1		T202	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T93	1		T106	3		T36	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	12		T14	3		T106	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T16	12		T24	1		T104	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T105	1		T164	11		T199	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	12		T24	12		T104	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T62	1		T93	1		T199	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T97	1		T98	10		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	13		T17	20		T19	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T86	1		T217	11		T116	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	9		T22	1		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T104	1		T100	1		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T23	1		T92	10		T106	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T21	1		T105	1		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T14	13		T216	1		T114	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T22	1		T114	10		T230	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T17	10		T228	10		T109	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16642	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T95	1		T87	6		T148	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T133	14		T228	2		T252	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T217	8		T156	1		T107	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T181	9		T209	2		T115	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	27		T209	10		T53	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T36	11		T215	9		T231	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	12		T14	7		T106	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T24	13		T100	12		T36	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T105	4		T204	11		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	16		T24	2		T94	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T62	15		T44	11		T120	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T98	20		T133	11		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	13		T17	17		T102	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T86	5		T217	10		T116	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	8		T100	2		T112	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T100	9		T35	8		T149	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T92	12		T106	14		T217	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T105	18		T198	5		T268	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	10		T216	15		T114	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T114	10		T180	8		T247	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T17	11		T228	2		T256	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T87	5		T261	8		T130	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T22	1		T114	10		T129	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T216	1		T114	12		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T117	8		T123	2		T304	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T87	6		T130	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T113	1		T101	1		T133	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	1		T95	1		T217	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T181	14		T209	12		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	30		T105	1		T202	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T93	1		T36	11		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	3		T143	16		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T104	7		T106	3		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	12		T62	1		T106	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T13	12		T16	12		T24	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T93	1		T105	1		T164	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T239	1		T97	1		T98	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T17	20		T164	2		T199	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T86	1		T217	11		T305	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	9		T13	13		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T104	1		T100	1		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T92	10		T106	14		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T21	1		T105	1		T215	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T14	13		T17	10		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T114	10		T152	17		T320	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T216	15		T114	10		T245	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T123	1		T304	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T87	5		T130	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T133	14		T228	2		T198	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T217	8		T229	10		T235	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T181	9		T209	2		T115	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	27		T209	10		T156	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	11		T134	8		T255	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	7		T143	17		T127	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T100	12		T36	11		T114	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	12		T62	15		T106	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T13	16		T24	15		T210	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T105	4		T44	11		T232	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T98	20		T133	11		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T17	17		T102	6		T214	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T86	5		T217	10		T305	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	8		T13	13		T100	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T100	9		T35	8		T149	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T92	12		T106	14		T217	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T105	18		T198	5		T268	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T14	10		T17	11		T204	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T113	1		T133	15		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	1		T217	9		T156	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T181	10		T209	3		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	29		T105	1		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T93	1		T106	1		T36	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	13		T14	8		T106	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T16	3		T24	14		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T105	5		T164	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	17		T24	3		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T62	16		T93	1		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T97	1		T98	26		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	14		T17	19		T19	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T86	6		T217	11		T116	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	11		T22	1		T100	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T104	1		T100	10		T35	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T23	1		T92	13		T106	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T21	1		T105	19		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	11		T216	16		T114	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T22	1		T114	11		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T17	12		T228	3		T109	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16733	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T95	1		T87	8		T148	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T133	11		T223	9		T228	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T217	7		T107	11		T228	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T181	13		T209	11		T115	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	28		T202	7		T209	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T106	2		T36	10		T231	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	11		T14	2		T106	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T16	9		T104	6		T111	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T164	10		T199	12		T204	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	11		T24	11		T104	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T199	4		T120	21		T57	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T98	4		T133	8		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	12		T17	18		T164	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T217	10		T116	15		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	6		T164	10		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T35	2		T149	4		T59	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T92	9		T106	13		T182	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T129	24		T226	6		T152	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	12		T114	11		T98	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T114	9		T230	10		T180	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T17	9		T228	9		T256	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T117	7		T321	9		T304	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T87	3		T261	9		T130	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T22	1		T114	11		T129	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T216	16		T114	11		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T117	1		T123	3		T304	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T87	8		T130	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T113	1		T101	1		T133	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	1		T95	1		T217	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T181	10		T209	3		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	29		T105	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T93	1		T36	12		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	8		T143	18		T127	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T104	1		T106	1		T100	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	13		T62	16		T106	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1403	1			T13	17		T16	3		T24	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T93	1		T105	5		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T239	1		T97	1		T98	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T17	19		T164	1		T199	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T86	6		T217	11		T305	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	11		T13	14		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T104	1		T100	10		T35	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T92	13		T106	15		T217	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T21	1		T105	19		T215	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T14	11		T17	12		T23	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T114	9		T129	11		T152	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T114	11		T245	1		T319	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T117	7		T304	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T87	3		T130	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T133	11		T223	9		T228	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T217	7		T235	8		T128	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T181	13		T209	11		T115	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	28		T202	7		T209	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	10		T134	10		T255	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T14	2		T143	15		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T104	6		T106	2		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	11		T106	9		T199	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T13	11		T16	9		T24	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T164	10		T232	10		T120	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T98	4		T133	8		T150	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	18		T164	1		T199	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T217	10		T305	1		T322	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	6		T13	12		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	2		T149	4		T116	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T92	9		T106	13		T182	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T230	10		T180	4		T129	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	12		T17	9		T98	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14