Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22131

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3381

1

T12

17

T13

28

T14

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19891

1

T6

2

T26

2

T31

1

auto[1]

5621

1

T12

57

T13

78

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	224	1			T21	1		T209	36		T230	18
values[0]	37	1			T204	14		T323	23		-	-
values[1]	712	1			T13	26		T19	1		T22	1
values[2]	767	1			T100	13		T199	5		T205	3
values[3]	838	1			T14	23		T24	14		T105	5
values[4]	935	1			T12	74		T13	24		T23	1
values[5]	800	1			T14	10		T17	21		T106	18
values[6]	649	1			T93	1		T95	1		T96	1
values[7]	533	1			T17	25		T104	7		T239	1
values[8]	2624	1			T13	28		T16	12		T22	1
values[9]	702	1			T15	1		T17	12		T24	14
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	724	1			T13	26		T104	1		T35	11
values[1]	843	1			T14	23		T22	1		T100	13
values[2]	803	1			T23	1		T24	14		T105	5
values[3]	919	1			T12	74		T13	24		T14	10
values[4]	702	1			T17	21		T106	18		T164	11
values[5]	638	1			T93	1		T95	1		T97	1
values[6]	2683	1			T13	28		T16	12		T17	25
values[7]	551	1			T62	16		T104	9		T93	1
values[8]	633	1			T15	1		T17	12		T21	1
values[9]	107	1			T208	4		T55	24		T201	11
minimum	16909	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	13		T104	1		T35	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T113	1		T98	10		T44	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T199	5		T205	1		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	13		T22	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T23	1		T105	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T24	1		T106	14		T199	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T12	30		T13	12		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	9		T14	3		T164	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T106	10		T36	6		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	10		T164	11		T43	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T93	1		T95	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T204	1		T107	12		T237	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T16	12		T17	13		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	12		T104	7		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T62	1		T93	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T104	9		T105	1		T106	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T15	1		T17	7		T24	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T21	1		T96	2		T87	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T285	7		T286	1		T324	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T208	3		T55	11		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16619	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T19	1		T100	1		T204	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	13		T35	8		T216	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T98	20		T44	11		T245	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T205	2		T99	9		T116	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	10		T100	12		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T105	4		T44	1		T204	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T24	13		T106	14		T181	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	27		T13	12		T112	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	8		T14	7		T209	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T106	8		T36	11		T114	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	11		T43	2		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T229	10		T278	11		T241	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T107	13		T237	9		T118	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T17	12		T210	10		T211	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	16		T86	5		T94	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T62	15		T217	10		T150	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T105	18		T100	2		T36	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T17	5		T24	2		T92	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T87	5		T102	13		T209	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T285	1		T286	7		T287	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T208	1		T55	13		T201	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T100	9		T204	11		T201	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T209	12		T230	11		T122	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T21	1		T209	12		T230	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T323	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T204	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	13		T104	1		T35	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T19	1		T22	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T199	5		T205	1		T234	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T100	1		T113	1		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T105	1		T44	1		T204	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	13		T24	1		T199	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T12	30		T13	12		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	9		T106	14		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T106	10		T36	6		T114	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	3		T17	10		T164	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T93	1		T95	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T204	1		T107	12		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T17	13		T156	1		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T104	7		T239	1		T164	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T16	12		T22	1		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	12		T104	9		T106	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	1		T17	7		T24	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T105	1		T100	1		T96	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T209	10		T317	15		T264	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T209	2		T201	10		T240	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T323	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T204	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	13		T35	8		T216	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T100	9		T98	20		T44	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T205	2		T99	9		T116	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T100	12		T133	14		T200	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T105	4		T44	1		T204	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	10		T24	13		T181	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	27		T13	12		T112	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	8		T106	14		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T106	8		T36	11		T114	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	7		T17	11		T43	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T217	8		T229	10		T259	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T107	13		T237	9		T118	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T17	12		T156	1		T228	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T86	5		T94	9		T116	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T210	10		T211	15		T212	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	16		T36	11		T114	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	5		T24	2		T62	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T105	18		T100	2		T87	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	14		T104	1		T35	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T113	1		T98	26		T44	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T199	1		T205	3		T99	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T14	11		T22	1		T100	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T23	1		T105	5		T44	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T24	14		T106	15		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	29		T13	13		T112	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	11		T14	8		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T106	9		T36	12		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	12		T164	1		T43	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T93	1		T95	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T204	1		T107	14		T237	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T16	3		T17	13		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	17		T104	1		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T62	16		T93	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T104	1		T105	19		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T15	1		T17	6		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T21	1		T96	2		T87	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T285	2		T286	8		T324	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T208	3		T55	14		T201	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16756	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T19	1		T100	10		T204	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	12		T35	2		T114	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T98	4		T228	10		T245	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T199	4		T223	9		T116	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	12		T133	11		T120	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T204	15		T57	13		T135	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T106	13		T199	12		T181	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T12	28		T13	11		T228	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	6		T14	2		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T106	9		T36	5		T114	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	9		T164	10		T43	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T129	13		T278	11		T119	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T107	11		T237	9		T180	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	868	1			T16	9		T17	12		T111	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	11		T104	6		T164	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T217	10		T150	6		T227	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T104	8		T106	2		T36	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T17	6		T24	11		T92	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T87	3		T209	11		T230	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T285	6		T287	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T208	1		T55	10		T255	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T57	8		T325	6		T326	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T204	2		T201	9		T313	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T209	11		T230	1		T122	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T21	1		T209	3		T230	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T323	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T204	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	14		T104	1		T35	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T19	1		T22	1		T100	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T199	1		T205	3		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T100	13		T113	1		T133	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T105	5		T44	2		T204	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	11		T24	14		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	29		T13	13		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	11		T106	15		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T106	9		T36	12		T114	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	8		T17	12		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T93	1		T95	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T204	1		T107	14		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T17	13		T156	2		T228	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T104	1		T239	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T16	3		T22	1		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	17		T104	1		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T15	1		T17	6		T24	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T105	19		T100	3		T96	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T209	11		T230	10		T131	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T209	11		T230	6		T126	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T323	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T204	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	12		T35	2		T114	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T98	4		T228	10		T245	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T199	4		T234	7		T223	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T133	11		T120	12		T117	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T204	15		T116	5		T57	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	12		T199	12		T181	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	28		T13	11		T228	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	6		T106	13		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T106	9		T36	5		T114	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	2		T17	9		T164	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T217	7		T236	15		T256	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T107	11		T237	9		T180	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T17	12		T129	13		T301	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T104	6		T164	1		T94	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T16	9		T111	12		T246	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	11		T104	8		T106	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T17	6		T24	11		T92	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T87	3		T208	1		T55	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14