Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19860

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

5652

1

T13

26

T14

10

T15

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19668

1

T6

2

T26

2

T31

1

auto[1]

5844

1

T12

17

T13

52

T14

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	268	1			T96	1		T245	3		T200	15
values[0]	50	1			T220	2		T221	24		T225	24
values[1]	654	1			T23	1		T24	14		T93	1
values[2]	634	1			T14	23		T164	11		T199	13
values[3]	890	1			T12	74		T24	14		T92	22
values[4]	580	1			T104	8		T43	10		T114	10
values[5]	767	1			T13	28		T17	21		T21	1
values[6]	566	1			T15	1		T17	25		T35	11
values[7]	674	1			T13	26		T14	10		T17	12
values[8]	633	1			T106	18		T100	3		T37	1
values[9]	3105	1			T13	24		T16	12		T19	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	690	1			T23	1		T24	14		T93	1
values[1]	2775	1			T12	57		T14	23		T16	12
values[2]	722	1			T12	17		T92	22		T105	20
values[3]	776	1			T21	1		T22	1		T104	17
values[4]	573	1			T13	28		T15	1		T17	21
values[5]	610	1			T17	25		T35	11		T86	6
values[6]	709	1			T13	26		T14	10		T17	12
values[7]	617	1			T106	18		T164	11		T112	9
values[8]	1036	1			T13	24		T19	1		T22	1
values[9]	137	1			T93	1		T107	1		T201	14
minimum	16867	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T23	1		T113	1		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T24	1		T93	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	30		T14	13		T24	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1262	1			T16	12		T203	3		T111	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	9		T105	1		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T92	10		T105	1		T106	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T21	1		T105	1		T36	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T22	1		T104	17		T43	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	12		T204	16		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	1		T17	10		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T86	1		T96	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	13		T35	3		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T17	7		T100	1		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	13		T14	3		T204	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T94	8		T114	12		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T106	10		T164	11		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T13	12		T62	1		T106	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T19	1		T22	1		T199	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T201	10		T148	2		T327	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T93	1		T107	1		T206	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16612	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T215	1		T120	10		T263	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T156	1		T208	1		T59	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T24	13		T100	12		T209	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	27		T14	10		T24	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1060	1			T210	10		T211	15		T212	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	8		T150	14		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T92	12		T105	18		T106	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T105	4		T36	11		T87	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T43	2		T36	11		T44	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	16		T204	8		T102	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	11		T98	20		T116	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T86	5		T181	9		T114	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	12		T35	8		T214	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	5		T100	2		T209	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	13		T14	7		T204	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T94	9		T114	10		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T106	8		T112	8		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T13	12		T62	15		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T216	15		T115	12		T217	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T201	4		T139	10		T183	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T206	13		T207	6		T287	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T120	11		T221	12		T286	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T245	2		T200	7		T201	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T96	1		T120	13		T150	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T225	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T220	2		T221	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T23	1		T202	8		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	1		T93	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	13		T94	13		T98	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T164	11		T199	13		T234	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	39		T24	12		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T92	10		T105	1		T106	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T114	6		T223	10		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T104	8		T43	8		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	12		T21	1		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T17	10		T22	1		T104	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T86	1		T96	1		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	1		T17	13		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	7		T133	12		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	13		T14	3		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T100	1		T37	1		T209	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T106	10		T44	1		T204	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T13	12		T62	1		T106	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1374	1			T16	12		T19	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T245	1		T200	8		T201	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T120	12		T150	9		T207	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T225	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T221	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T99	9		T156	1		T208	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T24	13		T100	12		T209	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	10		T94	12		T116	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T102	6		T107	13		T280	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	35		T24	2		T100	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T92	12		T105	18		T106	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T114	4		T142	14		T227	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T43	2		T133	11		T44	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	16		T105	4		T36	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	11		T36	11		T98	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T86	5		T181	9		T114	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T17	12		T35	8		T214	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T17	5		T133	14		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	13		T14	7		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T100	2		T209	10		T215	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T106	8		T44	1		T204	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	12		T62	15		T205	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1156	1			T112	8		T210	10		T211	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T23	1		T113	1		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T24	14		T93	1		T100	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	29		T14	11		T24	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1396	1			T16	3		T203	3		T111	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	11		T105	1		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T92	13		T105	19		T106	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T21	1		T105	5		T36	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T22	1		T104	3		T43	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	17		T204	9		T102	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	1		T17	12		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T86	6		T96	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T17	13		T35	9		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	6		T100	3		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	14		T14	8		T204	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T94	10		T114	11		T215	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T106	9		T164	1		T112	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T13	13		T62	16		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T19	1		T22	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T201	5		T148	2		T327	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T93	1		T107	1		T206	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16745	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T215	1		T120	12		T263	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T230	6		T208	1		T59	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T209	11		T231	14		T227	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	28		T14	12		T24	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	926	1			T16	9		T111	12		T164	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T12	6		T223	9		T228	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T92	9		T106	13		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T36	10		T87	3		T114	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T104	14		T43	5		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	11		T204	15		T117	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T17	9		T98	4		T116	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T181	13		T114	9		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	12		T35	2		T116	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T17	6		T209	11		T55	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	12		T14	2		T204	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T94	7		T114	11		T182	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T106	9		T164	10		T126	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	11		T106	2		T164	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T199	4		T115	13		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T201	9		T139	11		T183	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T206	17		T207	7		T275	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T202	7		T53	8		T301	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T120	9		T221	11		T222	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T245	2		T200	9		T201	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T96	1		T120	13		T150	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T225	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T220	2		T221	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T23	1		T202	1		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T24	14		T93	1		T100	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	11		T94	13		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T164	1		T199	1		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	40		T24	3		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T92	13		T105	19		T106	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T114	5		T223	1		T142	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T104	2		T43	5		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	17		T21	1		T105	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T17	12		T22	1		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T86	6		T96	1		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	1		T17	13		T35	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	6		T133	15		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	14		T14	8		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T100	3		T37	1		T209	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T106	9		T44	2		T204	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T13	13		T62	16		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1521	1			T16	3		T19	1		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T245	1		T200	6		T201	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T120	12		T150	9		T119	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T225	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T221	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T202	7		T230	6		T208	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T209	11		T120	9		T231	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	12		T94	12		T98	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T164	10		T199	12		T234	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	34		T24	11		T228	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T92	9		T106	13		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T114	5		T223	9		T260	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T104	6		T43	5		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	11		T36	10		T87	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	9		T104	8		T36	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T181	13		T114	9		T209	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	12		T35	2		T116	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T17	6		T133	11		T55	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	12		T14	2		T319	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T209	11		T182	2		T291	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T106	9		T204	2		T237	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T13	11		T106	2		T164	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1009	1			T16	9		T111	12		T164	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14