Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21804

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3708

1

T12

17

T14

10

T15

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19149

1

T6

2

T26

2

T31

1

auto[1]

6363

1

T12

17

T13

54

T14

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	530	1			T38	1		T39	2		T40	5
values[0]	34	1			T164	2		T234	8		T119	15
values[1]	646	1			T12	17		T13	26		T17	25
values[2]	2750	1			T15	1		T16	12		T19	1
values[3]	586	1			T14	10		T24	14		T92	22
values[4]	741	1			T164	22		T113	1		T204	24
values[5]	673	1			T105	19		T106	3		T86	6
values[6]	612	1			T13	24		T24	14		T104	7
values[7]	730	1			T14	23		T22	1		T105	1
values[8]	702	1			T12	57		T13	28		T100	3
values[9]	1328	1			T17	33		T21	1		T104	9
minimum	16180	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	782	1			T12	17		T13	26		T17	25
values[1]	2777	1			T14	10		T15	1		T16	12
values[2]	556	1			T22	1		T24	14		T113	1
values[3]	898	1			T92	22		T164	22		T113	1
values[4]	570	1			T24	14		T105	24		T106	3
values[5]	687	1			T104	7		T100	13		T35	11
values[6]	661	1			T13	24		T14	23		T105	1
values[7]	697	1			T12	57		T13	28		T22	1
values[8]	878	1			T17	33		T93	1		T106	28
values[9]	300	1			T21	1		T104	9		T100	10
minimum	16706	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	13		T17	13		T23	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	9		T104	1		T106	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T16	12		T203	3		T111	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	3		T15	1		T19	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T24	12		T96	1		T87	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	1		T113	1		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T214	4		T229	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T92	10		T164	22		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T105	1		T106	3		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T24	1		T105	1		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T35	3		T94	8		T116	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T104	7		T100	1		T107	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	12		T14	13		T36	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T105	1		T199	18		T36	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	30		T13	12		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T100	1		T216	1		T230	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T17	7		T93	1		T43	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T17	10		T106	14		T202	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T21	1		T104	9		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T44	3		T250	1		T249	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T251	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	13		T17	12		T114	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	8		T106	8		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T210	10		T211	15		T212	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	7		T62	15		T94	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T24	2		T87	5		T217	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T133	14		T209	10		T252	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T214	1		T229	10		T240	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T92	12		T204	8		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T105	18		T86	5		T110	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T24	13		T105	4		T198	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T35	8		T94	9		T116	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T100	12		T107	13		T200	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	12		T14	10		T36	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	11		T228	2		T120	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	27		T13	16		T114	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T100	2		T216	15		T116	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T17	5		T43	2		T112	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	11		T106	14		T114	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T100	9		T98	20		T59	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T44	11		T253	10		T225	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	511	1			T38	1		T39	2		T40	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T254	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T119	15		T138	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T164	2		T234	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	13		T17	13		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	9		T104	1		T106	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T16	12		T203	3		T111	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T15	1		T19	1		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T24	12		T96	1		T87	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	3		T92	10		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T214	4		T240	2		T117	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T164	22		T113	1		T204	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T105	1		T106	3		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T113	1		T96	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	12		T239	1		T94	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T24	1		T104	7		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	13		T22	1		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T105	1		T100	1		T199	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	30		T13	12		T114	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T100	1		T199	5		T36	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T17	7		T21	1		T104	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T17	10		T106	14		T202	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16053	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T254	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	13		T17	12		T114	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	8		T106	8		T205	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T210	10		T211	15		T212	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T62	15		T94	12		T133	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T24	2		T87	5		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	7		T92	12		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T214	1		T240	1		T152	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T204	8		T209	10		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T105	18		T86	5		T229	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T198	7		T120	11		T255	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	12		T94	9		T209	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T24	13		T105	4		T107	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	10		T35	8		T36	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T100	12		T228	2		T198	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	27		T13	16		T114	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T100	2		T36	11		T116	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T17	5		T100	9		T43	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T17	11		T106	14		T216	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	14		T17	13		T23	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	11		T104	1		T106	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T16	3		T203	3		T111	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T14	8		T15	1		T19	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T24	3		T96	1		T87	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	1		T113	1		T133	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T214	5		T229	11		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T92	13		T164	2		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T105	19		T106	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T24	14		T105	5		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	9		T94	10		T116	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T104	1		T100	13		T107	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	13		T14	11		T36	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T105	1		T199	2		T36	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	29		T13	17		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T100	3		T216	16		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T17	6		T93	1		T43	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T17	12		T106	15		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T21	1		T104	1		T100	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T44	14		T250	1		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T251	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	12		T17	12		T114	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	6		T106	9		T164	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T16	9		T111	12		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	2		T94	12		T133	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T24	11		T87	3		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T133	11		T209	11		T135	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T117	7		T255	6		T256	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T92	9		T164	20		T204	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T106	2		T252	5		T191	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T57	11		T117	13		T257	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T35	2		T94	7		T116	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T104	6		T107	11		T120	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	11		T14	12		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T199	16		T36	5		T228	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	28		T13	11		T114	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T230	10		T116	13		T57	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	6		T43	5		T181	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T17	9		T106	13		T202	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T104	8		T98	4		T59	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T249	2		T253	2		T225	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T251	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	511	1			T38	1		T39	2		T40	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T254	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T119	1		T138	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T164	1		T234	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	14		T17	13		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	11		T104	1		T106	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T16	3		T203	3		T111	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T15	1		T19	1		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T24	3		T96	1		T87	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	8		T92	13		T133	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T214	5		T240	3		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T164	2		T113	1		T204	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T105	19		T106	1		T86	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T113	1		T96	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	13		T239	1		T94	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T24	14		T104	1		T105	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	11		T22	1		T35	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T105	1		T100	13		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	29		T13	17		T114	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T100	3		T199	1		T36	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	420	1			T17	6		T21	1		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T17	12		T106	15		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16180	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T254	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T119	14		T138	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T164	1		T234	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	12		T17	12		T114	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	6		T106	9		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	887	1			T16	9		T111	12		T246	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T94	12		T133	8		T182	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T24	11		T87	3		T232	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	2		T92	9		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T117	7		T152	5		T241	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T164	20		T204	15		T209	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T106	2		T255	6		T252	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T120	9		T126	10		T117	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	11		T94	7		T209	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T104	6		T107	11		T57	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	12		T35	2		T36	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T199	12		T228	19		T213	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	28		T13	11		T114	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T199	4		T36	5		T116	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T17	6		T104	8		T43	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T17	9		T106	13		T202	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14