Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21769

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3743

1

T12

74

T13

28

T14

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19885

1

T6

2

T26

2

T31

1

auto[1]

5627

1

T12

57

T13

54

T14

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T258	24		-	-		-	-
values[0]	53	1			T205	3		T149	15		T259	12
values[1]	715	1			T13	26		T19	1		T22	1
values[2]	861	1			T15	1		T100	10		T164	11
values[3]	482	1			T12	17		T164	11		T94	25
values[4]	687	1			T14	10		T24	14		T104	8
values[5]	2856	1			T16	12		T93	1		T105	19
values[6]	618	1			T12	57		T14	23		T106	18
values[7]	520	1			T17	21		T22	1		T23	1
values[8]	607	1			T13	28		T17	25		T92	22
values[9]	1398	1			T13	24		T17	12		T21	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	936	1			T13	26		T15	1		T19	1
values[1]	714	1			T100	10		T98	1		T133	26
values[2]	740	1			T12	17		T14	10		T24	14
values[3]	2612	1			T16	12		T104	8		T93	1
values[4]	806	1			T12	57		T105	19		T106	3
values[5]	628	1			T14	23		T22	1		T106	18
values[6]	592	1			T17	21		T92	22		T199	5
values[7]	570	1			T13	52		T17	25		T21	1
values[8]	1007	1			T17	12		T104	9		T35	11
values[9]	187	1			T101	1		T108	14		T118	12
minimum	16720	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	13		T15	1		T22	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T19	1		T105	1		T106	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T98	1		T102	1		T209	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T100	1		T133	12		T204	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	3		T94	13		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	9		T24	12		T164	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T16	12		T203	3		T111	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T104	8		T93	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T113	1		T95	1		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T12	30		T105	1		T106	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T106	10		T100	1		T202	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	13		T22	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T199	5		T209	13		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T17	10		T92	10		T43	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	12		T21	1		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	12		T17	13		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T104	9		T35	3		T36	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T17	7		T199	13		T133	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T101	1		T108	5		T241	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T118	1		T247	7		T221	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T260	3		T137	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	13		T24	13		T62	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T106	14		T205	2		T87	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T102	6		T209	10		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T100	9		T133	14		T204	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	7		T94	12		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	8		T24	2		T36	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T210	10		T211	15		T212	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T98	20		T214	1		T261	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T216	15		T262	9		T180	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	27		T105	18		T115	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T106	8		T100	12		T86	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	10		T204	8		T107	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T209	10		T127	8		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T17	11		T92	12		T43	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T13	12		T105	4		T112	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	16		T17	12		T100	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T35	8		T36	11		T217	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T17	5		T133	11		T44	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T108	9		T241	3		T242	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T118	11		T247	11		T221	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T260	11		T137	14		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T258	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T149	5		T263	2		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T205	1		T259	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	13		T22	1		T24	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T19	1		T105	1		T106	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T15	1		T209	12		T217	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T100	1		T164	11		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T94	13		T101	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	9		T164	11		T116	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	3		T113	1		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T24	12		T104	8		T36	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T16	12		T203	3		T111	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T93	1		T105	1		T106	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T106	10		T100	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	30		T14	13		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T23	1		T202	8		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T17	10		T22	1		T43	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T105	1		T164	2		T199	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	12		T17	13		T92	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T13	12		T21	1		T104	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	431	1			T17	7		T199	13		T133	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T258	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T149	10		T264	3		T265	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T205	2		T259	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	13		T24	13		T62	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T106	14		T87	5		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T209	10		T217	10		T200	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T100	9		T181	9		T133	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T94	12		T102	6		T245	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	8		T116	10		T208	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T14	7		T114	10		T102	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T24	2		T36	11		T94	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1075	1			T210	10		T211	15		T212	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T105	18		T115	12		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T106	8		T100	12		T217	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	27		T14	10		T114	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T86	5		T127	8		T240	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	11		T43	2		T44	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T105	4		T209	10		T134	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	16		T17	12		T92	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T13	12		T35	8		T112	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T17	5		T133	11		T44	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T13	14		T15	1		T22	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T19	1		T105	1		T106	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T98	1		T102	7		T209	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T100	10		T133	15		T204	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	8		T94	13		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	11		T24	3		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T16	3		T203	3		T111	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T104	2		T93	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T113	1		T95	1		T216	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T12	29		T105	19		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T106	9		T100	13		T202	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	11		T22	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T199	1		T209	11		T127	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T17	12		T92	13		T43	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	13		T21	1		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	17		T17	13		T100	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T104	1		T35	9		T36	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T17	6		T199	1		T133	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T101	1		T108	10		T241	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T118	12		T247	12		T221	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T260	12		T137	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	12		T149	4		T236	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T106	13		T164	10		T87	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T209	11		T217	10		T200	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T133	11		T204	2		T232	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	2		T94	12		T245	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	6		T24	11		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T16	9		T111	12		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T104	6		T98	4		T230	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T98	1		T126	10		T180	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	28		T106	2		T115	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T106	9		T202	7		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	12		T204	15		T107	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T199	4		T209	12		T236	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T17	9		T92	9		T43	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	11		T164	1		T234	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	11		T17	12		T53	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T104	8		T35	2		T36	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T17	6		T199	12		T133	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T108	4		T241	3		T242	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T247	6		T221	1		T244	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T260	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T258	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T149	11		T263	2		T264	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T205	3		T259	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	14		T22	1		T24	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T19	1		T105	1		T106	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T15	1		T209	11		T217	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T100	10		T164	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T94	13		T101	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	11		T164	1		T116	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	8		T113	1		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	3		T104	2		T36	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T16	3		T203	3		T111	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T93	1		T105	19		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T106	9		T100	13		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	29		T14	11		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T23	1		T202	1		T86	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	12		T22	1		T43	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T105	5		T164	1		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	17		T17	13		T92	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T13	13		T21	1		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T17	6		T199	1		T133	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T258	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T149	4		T265	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T13	12		T236	15		T128	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T106	13		T87	3		T232	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T209	11		T217	10		T200	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T164	10		T181	13		T133	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T94	12		T245	1		T117	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	6		T164	10		T116	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	2		T114	11		T120	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T24	11		T104	6		T36	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	886	1			T16	9		T111	12		T246	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T106	2		T115	13		T228	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T106	9		T217	7		T126	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	28		T14	12		T114	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T202	7		T236	11		T117	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T17	9		T43	5		T228	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T164	1		T199	4		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	11		T17	12		T92	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T13	11		T104	8		T35	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T17	6		T199	12		T133	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14