Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21843

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3669

1

T12

57

T13

50

T14

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19966

1

T6

2

T26

2

T31

1

auto[1]

5546

1

T12

57

T13

24

T14

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	40	1			T266	25		T267	15		-	-
values[0]	75	1			T97	1		T44	2		T204	24
values[1]	648	1			T24	14		T104	1		T106	28
values[2]	580	1			T14	23		T105	20		T204	14
values[3]	372	1			T17	25		T105	5		T164	11
values[4]	2922	1			T13	28		T16	12		T104	9
values[5]	727	1			T13	24		T17	12		T22	1
values[6]	702	1			T23	1		T104	7		T199	5
values[7]	841	1			T12	17		T24	14		T43	10
values[8]	736	1			T12	57		T13	26		T14	10
values[9]	1178	1			T15	1		T19	1		T22	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	898	1			T24	14		T105	20		T202	8
values[1]	481	1			T14	23		T104	1		T105	5
values[2]	547	1			T13	28		T17	25		T164	2
values[3]	2868	1			T16	12		T104	9		T106	18
values[4]	686	1			T13	24		T17	12		T22	1
values[5]	716	1			T12	17		T24	14		T104	7
values[6]	878	1			T13	26		T14	10		T23	1
values[7]	707	1			T12	57		T17	21		T21	1
values[8]	914	1			T19	1		T22	1		T93	1
values[9]	126	1			T15	1		T36	22		T44	14
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T113	1		T95	1		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T24	12		T105	2		T202	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	13		T104	1		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T223	10		T107	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	12		T230	7		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T17	13		T164	2		T134	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T16	12		T104	9		T106	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T239	1		T96	1		T209	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T113	1		T209	12		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	12		T17	7		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	9		T24	1		T104	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T94	13		T37	1		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T114	10		T98	1		T103	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T13	13		T14	3		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T93	1		T106	3		T209	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	30		T17	10		T21	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T19	1		T22	1		T100	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T93	1		T199	13		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T36	11		T232	11		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T15	1		T44	3		T240	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T44	1		T204	19		T217	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T24	2		T105	18		T114	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	10		T105	4		T106	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T237	9		T268	16		T152	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	16		T201	10		T127	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T17	12		T134	8		T200	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T106	8		T112	8		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T209	10		T99	9		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T209	2		T200	10		T53	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	12		T17	5		T92	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	8		T24	13		T100	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T94	12		T102	6		T259	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T114	10		T226	5		T269	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	13		T14	7		T43	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T209	10		T217	8		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	27		T17	11		T62	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T100	14		T35	8		T215	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T87	5		T214	1		T116	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T36	11		T232	2		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T44	11		T240	1		T219	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T266	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T267	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T44	1		T204	16		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T97	1		T271	9		T272	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T104	1		T106	14		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T24	12		T202	8		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	13		T204	3		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T105	2		T223	10		T231	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T105	1		T164	11		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T17	13		T107	1		T259	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T13	12		T16	12		T104	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T164	2		T96	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T100	1		T113	1		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	12		T17	7		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T104	7		T36	6		T98	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T23	1		T199	5		T94	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	9		T24	1		T114	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T43	8		T95	1		T181	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T98	1		T209	12		T103	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	30		T13	13		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T19	1		T22	1		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T15	1		T62	1		T93	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T266	20		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T267	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T44	1		T204	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T271	9		T272	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T106	14		T217	10		T149	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T24	2		T114	14		T102	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	10		T204	11		T228	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T105	18		T231	12		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T105	4		T228	9		T206	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T17	12		T259	10		T235	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1097	1			T13	16		T106	8		T112	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T99	9		T134	8		T198	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T100	9		T216	15		T209	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	12		T17	5		T92	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T36	11		T98	20		T156	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T94	12		T116	10		T259	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	8		T24	13		T114	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T43	2		T181	9		T102	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T209	10		T217	8		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	27		T13	13		T14	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T100	14		T35	8		T36	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T62	15		T87	5		T44	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T113	1		T95	1		T44	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T24	3		T105	20		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	11		T104	1		T105	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T223	1		T107	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	17		T230	1		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	13		T164	1		T134	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T16	3		T104	1		T106	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T239	1		T96	1		T209	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T113	1		T209	3		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	13		T17	6		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	11		T24	14		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T94	13		T37	1		T102	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T114	11		T98	1		T103	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T13	14		T14	8		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T93	1		T106	1		T209	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	29		T17	12		T21	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T19	1		T22	1		T100	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T93	1		T199	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T36	12		T232	3		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T15	1		T44	14		T240	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T204	17		T217	10		T149	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T24	11		T202	7		T114	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T14	12		T106	13		T98	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T223	9		T237	9		T152	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	11		T230	6		T273	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T17	12		T164	1		T134	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T16	9		T104	8		T106	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T209	12		T143	15		T57	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T209	11		T150	6		T237	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	11		T17	6		T92	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	6		T104	6		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T94	12		T128	9		T274	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T114	9		T227	11		T226	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	12		T14	2		T43	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T106	2		T209	11		T217	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	28		T17	9		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T35	2		T164	10		T182	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T199	12		T87	3		T116	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T36	10		T232	10		T117	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T138	17		T275	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T266	21		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T267	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T44	2		T204	9		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T97	1		T271	10		T272	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T104	1		T106	15		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T24	3		T202	1		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	11		T204	12		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T105	20		T223	1		T231	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T105	5		T164	1		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T17	13		T107	1		T259	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1435	1			T13	17		T16	3		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T164	1		T96	1		T99	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T100	10		T113	1		T216	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	13		T17	6		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T104	1		T36	12		T98	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T23	1		T199	1		T94	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	11		T24	14		T114	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T43	5		T95	1		T181	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T98	1		T209	11		T103	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	29		T13	14		T14	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T19	1		T22	1		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T15	1		T62	16		T93	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T266	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T204	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T271	8		T272	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T106	13		T217	10		T149	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	11		T202	7		T114	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	12		T204	2		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T223	9		T231	14		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T164	10		T98	1		T230	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T17	12		T235	8		T129	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T13	11		T16	9		T104	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T164	1		T134	10		T200	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T209	11		T115	13		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	11		T17	6		T92	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T104	6		T36	5		T98	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T199	4		T94	12		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	6		T114	9		T245	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T43	5		T181	13		T180	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T209	11		T217	7		T150	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	28		T13	12		T14	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T106	2		T35	2		T164	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T199	12		T87	3		T234	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14