Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21979

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3533

1

T12

17

T13

24

T14

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19165

1

T6

2

T26

2

T31

1

auto[1]

6347

1

T12

17

T13

78

T16

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	809	1			T104	9		T38	1		T39	2
values[0]	9	1			T138	9		-	-		-	-
values[1]	691	1			T12	17		T13	26		T17	25
values[2]	2706	1			T15	1		T16	12		T19	1
values[3]	618	1			T14	10		T22	1		T24	14
values[4]	713	1			T164	22		T113	1		T204	24
values[5]	687	1			T105	19		T106	3		T239	1
values[6]	624	1			T24	14		T104	7		T105	5
values[7]	723	1			T13	24		T14	23		T22	1
values[8]	726	1			T12	57		T100	3		T36	17
values[9]	1026	1			T13	28		T17	33		T21	1
minimum	16180	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	608	1			T12	17		T13	26		T17	25
values[1]	2746	1			T14	10		T15	1		T16	12
values[2]	557	1			T22	1		T24	14		T92	22
values[3]	858	1			T164	22		T113	1		T204	24
values[4]	616	1			T24	14		T105	24		T106	3
values[5]	621	1			T104	7		T100	13		T94	17
values[6]	723	1			T13	24		T14	23		T22	1
values[7]	683	1			T12	57		T100	3		T216	16
values[8]	1023	1			T13	28		T17	33		T21	1
values[9]	173	1			T104	9		T113	1		T98	30
minimum	16904	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	13		T17	13		T23	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	9		T104	1		T106	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T16	12		T93	1		T203	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	3		T15	1		T19	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T22	1		T24	12		T92	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T113	1		T96	1		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T164	11		T214	4		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T164	11		T113	1		T204	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T105	1		T86	1		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T24	1		T105	1		T106	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T116	11		T200	1		T120	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T104	7		T100	1		T94	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	13		T22	1		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	12		T199	18		T36	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	30		T100	1		T114	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T216	1		T230	11		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T13	12		T17	7		T21	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T17	10		T93	1		T43	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T104	9		T113	1		T98	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T44	3		T118	1		T249	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16605	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T164	2		T234	8		T134	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	13		T17	12		T116	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	8		T106	8		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1093	1			T210	10		T94	12		T211	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	7		T62	15		T208	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T24	2		T92	12		T87	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T133	14		T209	10		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T214	1		T229	10		T259	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T204	8		T217	10		T200	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T105	18		T86	5		T110	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	13		T105	4		T198	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T116	10		T200	10		T120	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T100	12		T94	9		T107	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	10		T35	8		T36	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	12		T36	11		T120	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	27		T100	2		T114	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T216	15		T259	2		T180	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	16		T17	5		T106	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T17	11		T43	2		T181	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T98	20		T276	6		T277	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T44	11		T118	11		T254	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T134	8		T213	8		T278	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	563	1			T104	9		T38	1		T39	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T44	3		T53	9		T56	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T138	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	13		T17	13		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	9		T104	1		T106	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T16	12		T93	1		T203	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	1		T19	1		T62	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T22	1		T24	12		T92	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	3		T96	1		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T164	11		T214	4		T259	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T164	11		T113	1		T204	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T105	1		T86	1		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T106	3		T239	1		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T116	11		T121	3		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	1		T104	7		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	13		T22	1		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	12		T100	1		T199	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	30		T100	1		T114	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T36	6		T98	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T13	12		T17	7		T21	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T17	10		T93	1		T43	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16053	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T112	8		T98	20		T226	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T44	11		T53	11		T118	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	13		T17	12		T114	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	8		T106	8		T205	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T210	10		T94	12		T211	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T62	15		T208	1		T53	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T24	2		T92	12		T87	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	7		T133	14		T209	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T214	1		T259	10		T240	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T204	8		T217	10		T200	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T105	18		T86	5		T229	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T198	7		T255	11		T256	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T116	10		T121	2		T110	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T24	13		T105	4		T94	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	10		T35	8		T36	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	12		T100	12		T245	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	27		T100	2		T114	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	11		T120	12		T213	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	16		T17	5		T106	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	11		T43	2		T181	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	14		T17	13		T23	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	11		T104	1		T106	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T16	3		T93	1		T203	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	8		T15	1		T19	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T22	1		T24	3		T92	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T113	1		T96	1		T133	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T164	1		T214	5		T229	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T164	1		T113	1		T204	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T105	19		T86	6		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T24	14		T105	5		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T116	11		T200	11		T120	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T104	1		T100	13		T94	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	11		T22	1		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	13		T199	2		T36	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	29		T100	3		T114	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T216	16		T230	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T13	17		T17	6		T21	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T17	12		T93	1		T43	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T104	1		T113	1		T98	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T44	14		T118	12		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16743	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T164	1		T234	1		T134	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	12		T17	12		T116	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	6		T106	9		T128	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T16	9		T111	12		T94	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	2		T208	1		T128	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T24	11		T92	9		T87	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T133	11		T209	11		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T164	10		T117	7		T255	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T164	10		T204	15		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T252	5		T257	11		T273	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T106	2		T57	11		T117	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T116	10		T120	9		T247	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T104	6		T94	7		T107	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	12		T35	2		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	11		T199	16		T36	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	28		T114	5		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T230	10		T57	21		T180	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	11		T17	6		T106	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	9		T43	5		T181	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T104	8		T98	4		T279	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T249	2		T254	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T114	11		T204	2		T230	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T164	1		T234	7		T134	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	586	1			T104	1		T38	1		T39	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	14		T53	12		T56	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T138	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	14		T17	13		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	11		T104	1		T106	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T16	3		T93	1		T203	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T15	1		T19	1		T62	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T22	1		T24	3		T92	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	8		T96	1		T133	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T164	1		T214	5		T259	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T164	1		T113	1		T204	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T105	19		T86	6		T229	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T106	1		T239	1		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T116	11		T121	5		T110	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T24	14		T104	1		T105	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T14	11		T22	1		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	13		T100	13		T199	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	29		T100	3		T114	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T36	12		T98	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T13	17		T17	6		T21	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T17	12		T93	1		T43	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16180	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T104	8		T98	4		T144	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T53	8		T249	2		T130	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T138	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	12		T17	12		T114	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	6		T106	9		T164	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T16	9		T111	12		T94	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T208	1		T128	9		T280	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T24	11		T92	9		T87	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	2		T133	11		T209	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T164	10		T117	7		T255	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T164	10		T204	15		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T120	9		T252	5		T257	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T106	2		T117	13		T255	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T116	10		T251	2		T221	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T104	6		T94	7		T107	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	12		T35	2		T36	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	11		T199	16		T228	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	28		T114	5		T228	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T36	5		T120	12		T57	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T13	11		T17	6		T106	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	9		T43	5		T181	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14