Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22299

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3213

1

T12

74

T13

54

T14

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19738

1

T6

2

T26

2

T31

1

auto[1]

5774

1

T12

57

T13

28

T14

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T183	11		-	-		-	-
values[0]	103	1			T62	16		T239	1		T156	2
values[1]	781	1			T12	57		T100	10		T164	13
values[2]	579	1			T13	50		T17	12		T21	1
values[3]	966	1			T105	19		T106	46		T202	8
values[4]	757	1			T14	10		T22	1		T100	3
values[5]	614	1			T17	21		T19	1		T24	14
values[6]	564	1			T14	23		T93	1		T35	11
values[7]	612	1			T22	1		T36	22		T113	1
values[8]	579	1			T12	17		T13	28		T15	1
values[9]	3255	1			T16	12		T17	25		T23	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	915	1			T13	50		T62	16		T239	1
values[1]	826	1			T12	57		T17	12		T21	1
values[2]	900	1			T106	31		T94	17		T216	16
values[3]	716	1			T14	10		T22	1		T104	7
values[4]	575	1			T17	21		T19	1		T24	14
values[5]	521	1			T93	1		T35	11		T199	13
values[6]	2712	1			T14	23		T16	12		T22	1
values[7]	683	1			T12	17		T15	1		T92	22
values[8]	822	1			T13	28		T17	25		T23	1
values[9]	130	1			T87	11		T57	12		T268	17
minimum	16712	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	12		T62	1		T164	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T13	13		T239	1		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T21	1		T24	1		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	30		T17	7		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T106	17		T94	8		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T44	1		T102	1		T209	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T105	1		T133	12		T209	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	3		T22	1		T104	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T17	10		T24	12		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T19	1		T113	1		T133	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T93	1		T96	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T35	3		T199	13		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T14	13		T16	12		T203	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T22	1		T164	11		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	1		T92	10		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	9		T96	2		T245	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T17	13		T23	1		T104	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	12		T204	1		T209	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T57	12		T252	6		T183	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T87	6		T268	1		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T100	1		T164	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	12		T62	15		T114	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	13		T112	8		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T24	13		T105	18		T106	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	27		T17	5		T98	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T106	14		T94	9		T216	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T44	1		T102	6		T209	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T105	4		T133	14		T209	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	7		T232	2		T55	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T17	11		T24	2		T100	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T133	11		T200	8		T255	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T204	11		T102	13		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T35	8		T107	13		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T14	10		T210	10		T211	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T198	7		T121	2		T261	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T92	12		T36	22		T256	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	8		T245	1		T274	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T17	12		T86	5		T204	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	16		T209	10		T99	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T252	10		T183	6		T282	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T87	5		T268	16		T218	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T100	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T183	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T62	1		T229	1		T180	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T239	1		T156	1		T271	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T164	2		T114	6		T217	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	30		T100	1		T164	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	12		T21	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	13		T17	7		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T105	1		T106	24		T202	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T95	1		T98	10		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T100	1		T216	1		T209	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	3		T22	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T17	10		T24	12		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	1		T104	7		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	13		T93	1		T204	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T35	3		T199	13		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T36	11		T113	1		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T22	1		T97	1		T234	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	1		T36	6		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	9		T13	12		T164	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T16	12		T17	13		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T96	1		T87	6		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T183	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T62	15		T229	10		T180	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T156	1		T271	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T114	4		T217	18		T201	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	27		T100	9		T112	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	12		T24	13		T214	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T13	13		T17	5		T116	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T105	18		T106	22		T94	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T98	20		T44	1		T102	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T100	2		T216	15		T209	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	7		T215	9		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	11		T24	2		T105	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T133	11		T232	2		T200	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	10		T204	11		T228	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T35	8		T107	13		T227	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	11		T228	2		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T198	7		T245	1		T261	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T36	11		T259	10		T127	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	8		T13	16		T121	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T17	12		T92	12		T210	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T87	5		T209	10		T99	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	13		T62	16		T164	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T13	14		T239	1		T112	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T21	1		T24	14		T105	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	29		T17	6		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T106	16		T94	10		T216	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	2		T102	7		T209	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T105	5		T133	15		T209	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	8		T22	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	12		T24	3		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T19	1		T113	1		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T93	1		T96	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	9		T199	1		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T14	11		T16	3		T203	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	1		T164	1		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	1		T92	13		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	11		T96	2		T245	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T17	13		T23	1		T104	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T13	17		T204	1		T209	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T57	1		T252	11		T183	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T87	8		T268	17		T281	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T100	10		T164	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	11		T164	1		T114	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	12		T94	12		T181	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T106	9		T202	7		T149	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	28		T17	6		T98	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T106	15		T94	7		T114	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T209	11		T217	10		T223	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T133	11		T209	12		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	2		T104	6		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	9		T24	11		T199	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T133	8		T200	6		T255	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T204	2		T230	10		T228	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T35	2		T199	12		T107	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T14	12		T16	9		T111	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T164	10		T234	7		T261	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T92	9		T36	15		T256	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	6		T245	1		T274	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	12		T104	8		T204	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	11		T209	11		T120	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T57	11		T252	5		T183	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T87	3		T218	6		T283	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T164	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T183	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T62	16		T229	11		T180	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T239	1		T156	2		T271	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T164	1		T114	5		T217	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	29		T100	10		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	13		T21	1		T24	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	14		T17	6		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T105	19		T106	24		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T95	1		T98	26		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T100	3		T216	16		T209	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	8		T22	1		T215	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T17	12		T24	3		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T19	1		T104	1		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	11		T93	1		T204	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	9		T199	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	12		T113	1		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T22	1		T97	1		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	1		T36	12		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	11		T13	17		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T16	3		T17	13		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T96	1		T87	8		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T183	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T258	12		T265	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T271	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T164	1		T114	5		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	28		T164	10		T94	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T13	11		T106	2		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	12		T17	6		T98	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T106	22		T202	7		T94	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T98	4		T209	11		T115	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T209	12		T53	8		T237	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	2		T217	10		T182	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T17	9		T24	11		T199	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T104	6		T133	8		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	12		T204	2		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T35	2		T199	12		T107	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T36	10		T228	6		T57	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T234	7		T245	1		T261	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T36	5		T126	10		T256	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	6		T13	11		T164	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T16	9		T17	12		T104	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T87	3		T209	11		T120	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14