Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22019

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3493

1

T12

17

T13

28

T14

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19742

1

T6

2

T26

2

T31

1

auto[1]

5770

1

T12

57

T13

78

T15

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	45	1			T209	22		T201	11		T251	11
values[0]	30	1			T204	14		T163	1		T284	1
values[1]	678	1			T13	26		T19	1		T22	1
values[2]	864	1			T100	13		T199	5		T113	1
values[3]	758	1			T14	23		T24	14		T105	5
values[4]	959	1			T12	74		T13	24		T23	1
values[5]	795	1			T14	10		T17	21		T106	18
values[6]	664	1			T93	1		T86	6		T95	1
values[7]	529	1			T17	25		T104	7		T239	1
values[8]	2638	1			T13	28		T16	12		T22	1
values[9]	861	1			T15	1		T17	12		T21	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	991	1			T13	26		T19	1		T22	1
values[1]	868	1			T14	23		T100	13		T199	5
values[2]	776	1			T23	1		T24	14		T105	5
values[3]	854	1			T12	74		T14	10		T164	11
values[4]	730	1			T13	24		T17	21		T106	18
values[5]	645	1			T93	1		T86	6		T95	1
values[6]	2698	1			T13	28		T16	12		T17	25
values[7]	535	1			T22	1		T62	16		T104	9
values[8]	596	1			T15	1		T17	12		T21	1
values[9]	127	1			T208	4		T144	3		T201	11
minimum	16692	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	13		T104	1		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T19	1		T22	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T199	5		T205	1		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	13		T100	1		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T23	1		T105	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T24	1		T106	14		T199	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	30		T112	1		T228	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	9		T14	3		T164	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	12		T36	6		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	10		T106	10		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T93	1		T95	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T86	1		T204	1		T107	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T16	12		T17	13		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	12		T104	7		T164	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T22	1		T62	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T104	9		T105	1		T106	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	1		T17	7		T24	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T21	1		T96	2		T87	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T144	3		T285	7		T286	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T208	3		T201	1		T255	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T149	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	13		T216	15		T114	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T100	9		T35	8		T98	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T205	2		T99	9		T116	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	10		T100	12		T181	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T105	4		T44	1		T204	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	13		T106	14		T182	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	27		T112	8		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	8		T14	7		T209	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	12		T36	11		T114	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	11		T106	8		T43	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T228	9		T229	10		T278	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T86	5		T107	13		T237	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T17	12		T210	10		T211	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	16		T94	9		T114	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T62	15		T217	10		T150	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T105	18		T100	2		T36	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T17	5		T24	2		T92	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T87	5		T102	13		T209	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T285	1		T286	7		T287	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T208	1		T201	10		T255	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T209	12		T288	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T201	1		T251	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T163	1		T284	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T204	3		T289	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	13		T104	1		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T19	1		T22	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T199	5		T114	12		T234	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T100	1		T113	1		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T105	1		T205	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	13		T24	1		T199	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T12	30		T13	12		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	9		T106	14		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T36	6		T114	6		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	3		T17	10		T106	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T93	1		T95	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T86	1		T204	1		T107	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T17	13		T156	1		T121	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T104	7		T239	1		T164	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T16	12		T22	1		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	12		T104	9		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T15	1		T17	7		T24	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T21	1		T105	1		T106	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T209	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T201	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T204	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	13		T216	15		T214	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T100	9		T35	8		T98	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T114	10		T99	9		T149	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T100	12		T133	14		T200	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T105	4		T205	2		T44	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	10		T24	13		T181	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	27		T13	12		T112	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	8		T106	14		T43	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	11		T114	4		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	7		T17	11		T106	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T217	8		T228	9		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T86	5		T107	13		T237	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T17	12		T156	1		T121	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T94	9		T116	10		T53	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T210	10		T211	15		T212	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	16		T36	11		T114	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T17	5		T24	2		T62	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T105	18		T100	2		T87	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	14		T104	1		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T19	1		T22	1		T100	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T199	1		T205	3		T99	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T14	11		T100	13		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T23	1		T105	5		T44	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T24	14		T106	15		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	29		T112	9		T228	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	11		T14	8		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	13		T36	12		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	12		T106	9		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T93	1		T95	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T86	6		T204	1		T107	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T16	3		T17	13		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	17		T104	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T22	1		T62	16		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T104	1		T105	19		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	1		T17	6		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T21	1		T96	2		T87	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T144	1		T285	2		T286	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T208	3		T201	11		T255	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T149	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	12		T114	11		T234	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T35	2		T98	4		T204	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T199	4		T223	9		T116	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	12		T181	13		T133	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T204	15		T228	6		T57	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T106	13		T199	12		T182	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	28		T228	9		T143	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	6		T14	2		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	11		T36	5		T114	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	9		T106	9		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T129	13		T278	11		T119	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T107	11		T237	9		T180	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T16	9		T17	12		T111	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	11		T104	6		T164	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T217	10		T150	6		T237	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T104	8		T106	2		T36	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T17	6		T24	11		T92	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T87	3		T209	11		T230	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T144	2		T285	6		T287	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T208	1		T255	6		T248	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T209	11		T288	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T201	11		T251	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T163	1		T284	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T204	12		T289	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	14		T104	1		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T19	1		T22	1		T100	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T199	1		T114	11		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T100	13		T113	1		T133	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T105	5		T205	3		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	11		T24	14		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T12	29		T13	13		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	11		T106	15		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T36	12		T114	5		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	8		T17	12		T106	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T93	1		T95	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T86	6		T204	1		T107	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T17	13		T156	2		T121	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T104	1		T239	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T16	3		T22	1		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	17		T104	1		T36	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T15	1		T17	6		T24	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T21	1		T105	19		T106	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T209	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T251	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T204	2		T289	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	12		T115	13		T57	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T35	2		T98	4		T228	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T199	4		T114	11		T234	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T133	11		T120	12		T117	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T204	15		T228	6		T116	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	12		T199	12		T181	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	28		T13	11		T57	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	6		T106	13		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	5		T114	5		T228	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	2		T17	9		T106	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T217	7		T236	15		T256	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T107	11		T237	9		T180	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T17	12		T129	13		T290	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T104	6		T164	1		T94	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	866	1			T16	9		T111	12		T246	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	11		T104	8		T36	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T17	6		T24	11		T92	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T106	2		T87	3		T209	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14