Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25512

1

T6

2

T26

2

T31

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22021

1

T6

2

T26

2

T31

1

auto[ADC_CTRL_FILTER_COND_OUT]

3491

1

T12

57

T13

26

T14

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19688

1

T6

2

T26

2

T31

1

auto[1]

5824

1

T12

74

T13

50

T14

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21268

1

T12

59

T13

37

T14

16

auto[1]

4244

1

T6

2

T26

2

T31

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	317	1			T92	22		T106	3		T100	10
values[0]	6	1			T278	6		-	-		-	-
values[1]	790	1			T24	14		T93	2		T100	3
values[2]	2547	1			T16	12		T17	12		T105	1
values[3]	848	1			T14	23		T104	1		T105	19
values[4]	757	1			T12	17		T13	50		T21	1
values[5]	588	1			T12	57		T23	1		T104	7
values[6]	572	1			T15	1		T62	16		T94	17
values[7]	866	1			T14	10		T22	1		T24	14
values[8]	658	1			T13	28		T19	1		T22	1
values[9]	872	1			T17	46		T105	5		T239	1
minimum	16691	1			T6	2		T26	2		T31	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T24	14		T93	2		T100	3
values[1]	2662	1			T16	12		T17	12		T105	20
values[2]	766	1			T13	24		T14	23		T104	1
values[3]	834	1			T12	17		T13	26		T21	1
values[4]	623	1			T12	57		T23	1		T104	7
values[5]	545	1			T15	1		T62	16		T94	17
values[6]	815	1			T14	10		T22	1		T24	14
values[7]	575	1			T13	28		T19	1		T22	1
values[8]	912	1			T17	46		T92	22		T105	5
values[9]	170	1			T199	5		T95	1		T182	11
minimum	16937	1			T6	2		T26	2		T31	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

3659

1

T12

34

T13

34

T14

14

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T43	8		T114	6		T234	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T24	1		T93	2		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T16	12		T105	1		T203	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	7		T105	1		T164	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	12		T216	1		T209	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	13		T104	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	9		T21	1		T199	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	13		T96	1		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T104	7		T164	11		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	30		T23	1		T106	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T15	1		T62	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T94	8		T208	3		T291	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T114	10		T209	12		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	3		T22	1		T24	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	12		T22	1		T106	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T19	1		T104	9		T36	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T105	1		T100	2		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T17	23		T92	10		T106	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T199	5		T182	5		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T95	1		T142	1		T292	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16641	1			T12	20		T18	18		T19	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T131	3		T207	8		T293	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T43	2		T114	4		T99	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	13		T100	2		T204	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T112	8		T210	10		T211	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	5		T105	18		T209	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	12		T216	15		T209	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	10		T217	10		T200	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	8		T98	20		T133	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	13		T114	10		T107	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T36	11		T94	12		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	27		T106	14		T259	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T62	15		T102	13		T53	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T94	9		T208	1		T294	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T114	10		T209	2		T53	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	7		T24	2		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	16		T106	8		T86	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T36	11		T181	9		T245	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T105	4		T100	21		T35	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	23		T92	12		T87	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T182	6		T120	11		T295	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T142	14		T292	13		T219	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	2		T26	2		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T131	6		T207	6		T293	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T100	1		T199	5		T37	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T92	10		T106	3		T95	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T278	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	8		T204	3		T234	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T24	1		T93	2		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T16	12		T105	1		T203	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T17	7		T164	2		T209	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T216	1		T209	12		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	13		T104	1		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	9		T13	12		T21	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	13		T97	1		T114	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T104	7		T164	11		T36	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	30		T23	1		T106	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T15	1		T62	1		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T94	8		T208	3		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T97	1		T102	1		T209	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	3		T22	1		T24	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	12		T22	1		T106	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	1		T104	9		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T105	1		T100	1		T35	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T17	23		T239	1		T202	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T12	20		T18	18		T19	44
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T100	9		T215	9		T198	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T92	12		T292	13		T219	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T278	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	2		T204	11		T99	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T24	13		T100	2		T204	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T112	8		T210	10		T211	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T17	5		T209	10		T116	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T216	15		T209	10		T134	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	10		T105	18		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	8		T13	12		T98	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	13		T114	10		T107	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T36	11		T94	12		T115	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	27		T106	14		T259	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T62	15		T44	1		T121	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T94	9		T208	1		T127	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T102	13		T209	2		T53	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	7		T24	2		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	16		T106	8		T86	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T36	11		T205	2		T181	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T105	4		T100	12		T35	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	23		T87	5		T232	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	2		T26	2		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T43	5		T114	5		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T24	14		T93	2		T100	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T16	3		T105	1		T203	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	6		T105	19		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	13		T216	16		T209	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	11		T104	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	11		T21	1		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	14		T96	1		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T104	1		T164	1		T36	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	29		T23	1		T106	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	1		T62	16		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T94	10		T208	3		T291	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T114	11		T209	3		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	8		T22	1		T24	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	17		T22	1		T106	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T19	1		T104	1		T36	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T105	5		T100	23		T35	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	25		T92	13		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T199	1		T182	9		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T95	1		T142	15		T292	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16775	1			T6	2		T26	2		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T131	7		T207	7		T293	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T43	5		T114	5		T234	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T204	15		T228	9		T120	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	896	1			T16	9		T111	12		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T17	6		T164	1		T209	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	11		T209	11		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	12		T217	10		T200	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	6		T199	12		T98	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	12		T114	11		T107	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T104	6		T164	10		T36	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	28		T106	13		T242	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T53	8		T213	13		T296	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T94	7		T208	1		T291	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T114	9		T209	11		T228	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	2		T24	11		T228	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	11		T106	9		T223	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T104	8		T36	10		T181	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T35	2		T164	10		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T17	21		T92	9		T106	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T199	4		T182	2		T120	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T292	15		T297	4		T233	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T204	2		T217	7		T298	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T131	2		T207	7		T293	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T100	10		T199	1		T37	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T92	13		T106	1		T95	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T278	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	5		T204	12		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T24	14		T93	2		T100	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T16	3		T105	1		T203	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	6		T164	1		T209	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T216	16		T209	11		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	11		T104	1		T105	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	11		T13	13		T21	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	14		T97	1		T114	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T104	1		T164	1		T36	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	29		T23	1		T106	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	1		T62	16		T44	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T94	10		T208	3		T127	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T97	1		T102	14		T209	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	8		T22	1		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	17		T22	1		T106	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T19	1		T104	1		T36	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T105	5		T100	13		T35	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T17	25		T239	1		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16691	1			T6	2		T26	2		T31	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T199	4		T150	6		T299	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T92	9		T106	2		T292	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T278	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T43	5		T204	2		T234	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T204	15		T228	9		T120	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	906	1			T16	9		T111	12		T246	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T17	6		T164	1		T209	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T209	11		T134	10		T143	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	12		T217	10		T57	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	6		T13	11		T199	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	12		T114	11		T107	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T104	6		T164	10		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	28		T106	13		T129	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T249	2		T221	1		T300	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T94	7		T208	1		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T209	11		T228	10		T53	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	2		T24	11		T291	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	11		T106	9		T114	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T104	8		T36	10		T181	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T35	2		T164	10		T133	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T17	21		T202	7		T87	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21853

1

T6

2

T26

2

T31

1

auto[1]

auto[0]

3659

1

T12

34

T13

34

T14

14