Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.55 98.98 95.70 100.00 100.00 98.18 98.64 91.37


Total test records in report: 914
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T762 /workspace/coverage/default/34.adc_ctrl_clock_gating.1056495840 Jan 17 01:05:28 PM PST 24 Jan 17 01:24:24 PM PST 24 497455485256 ps
T763 /workspace/coverage/default/25.adc_ctrl_stress_all.1345064029 Jan 17 01:04:26 PM PST 24 Jan 17 01:10:23 PM PST 24 95929305159 ps
T764 /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4212498634 Jan 17 01:07:31 PM PST 24 Jan 17 01:10:38 PM PST 24 166228698434 ps
T765 /workspace/coverage/default/33.adc_ctrl_filters_interrupt.453660500 Jan 17 01:05:09 PM PST 24 Jan 17 01:08:30 PM PST 24 164811382111 ps
T312 /workspace/coverage/default/49.adc_ctrl_filters_polled.1115628733 Jan 17 01:07:46 PM PST 24 Jan 17 01:09:58 PM PST 24 325241401952 ps
T766 /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3364508033 Jan 17 01:05:18 PM PST 24 Jan 17 01:05:58 PM PST 24 166757274995 ps
T767 /workspace/coverage/default/42.adc_ctrl_fsm_reset.651649682 Jan 17 01:06:48 PM PST 24 Jan 17 01:13:27 PM PST 24 75574501220 ps
T768 /workspace/coverage/default/9.adc_ctrl_filters_polled.2572824517 Jan 17 01:03:13 PM PST 24 Jan 17 01:06:10 PM PST 24 497772707280 ps
T769 /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3732303859 Jan 17 01:04:06 PM PST 24 Jan 17 01:09:08 PM PST 24 502966139978 ps
T770 /workspace/coverage/default/41.adc_ctrl_filters_both.644709744 Jan 17 01:06:40 PM PST 24 Jan 17 01:20:11 PM PST 24 334686810547 ps
T771 /workspace/coverage/default/2.adc_ctrl_poweron_counter.427143203 Jan 17 01:03:03 PM PST 24 Jan 17 01:03:15 PM PST 24 4254492227 ps
T772 /workspace/coverage/default/37.adc_ctrl_alert_test.1506800444 Jan 17 01:05:59 PM PST 24 Jan 17 01:06:01 PM PST 24 368503921 ps
T773 /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2156782573 Jan 17 01:06:20 PM PST 24 Jan 17 01:08:01 PM PST 24 165420591433 ps
T774 /workspace/coverage/default/17.adc_ctrl_clock_gating.2308982427 Jan 17 01:03:48 PM PST 24 Jan 17 01:16:27 PM PST 24 336386729263 ps
T287 /workspace/coverage/default/43.adc_ctrl_stress_all.132603020 Jan 17 01:07:03 PM PST 24 Jan 17 01:12:36 PM PST 24 333128159429 ps
T775 /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.911830289 Jan 17 01:03:03 PM PST 24 Jan 17 01:04:43 PM PST 24 165608780813 ps
T289 /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2925680654 Jan 17 01:04:29 PM PST 24 Jan 17 01:10:43 PM PST 24 169176328490 ps
T776 /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.569098869 Jan 17 01:02:58 PM PST 24 Jan 17 01:05:05 PM PST 24 117131540170 ps
T777 /workspace/coverage/default/30.adc_ctrl_filters_both.1105850255 Jan 17 01:04:52 PM PST 24 Jan 17 01:17:36 PM PST 24 336591357863 ps
T778 /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3463305695 Jan 17 01:06:30 PM PST 24 Jan 17 01:06:46 PM PST 24 44580370971 ps
T310 /workspace/coverage/default/31.adc_ctrl_filters_polled.2067983242 Jan 17 01:05:04 PM PST 24 Jan 17 01:10:22 PM PST 24 484210866748 ps
T779 /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3855113447 Jan 17 01:02:47 PM PST 24 Jan 17 01:08:46 PM PST 24 166861859802 ps
T780 /workspace/coverage/default/13.adc_ctrl_smoke.3784045233 Jan 17 01:03:40 PM PST 24 Jan 17 01:03:44 PM PST 24 5843550197 ps
T781 /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.950317898 Jan 17 01:07:19 PM PST 24 Jan 17 01:26:26 PM PST 24 494887954528 ps
T782 /workspace/coverage/default/22.adc_ctrl_alert_test.1010641542 Jan 17 01:04:17 PM PST 24 Jan 17 01:04:18 PM PST 24 500223797 ps
T783 /workspace/coverage/default/22.adc_ctrl_smoke.4023713158 Jan 17 01:04:11 PM PST 24 Jan 17 01:04:16 PM PST 24 5720417970 ps
T784 /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3146507769 Jan 17 01:06:18 PM PST 24 Jan 17 01:13:19 PM PST 24 163961789889 ps
T336 /workspace/coverage/default/39.adc_ctrl_fsm_reset.431328733 Jan 17 01:06:20 PM PST 24 Jan 17 01:10:16 PM PST 24 71424619225 ps
T785 /workspace/coverage/default/7.adc_ctrl_filters_polled.2345121681 Jan 17 01:03:15 PM PST 24 Jan 17 01:06:46 PM PST 24 338862951899 ps
T786 /workspace/coverage/default/32.adc_ctrl_alert_test.1750475479 Jan 17 01:05:19 PM PST 24 Jan 17 01:05:22 PM PST 24 491553027 ps
T787 /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1926760859 Jan 17 01:05:33 PM PST 24 Jan 17 01:11:09 PM PST 24 99377259589 ps
T788 /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1196167485 Jan 17 01:02:57 PM PST 24 Jan 17 01:06:13 PM PST 24 324491849361 ps
T789 /workspace/coverage/default/16.adc_ctrl_filters_polled.443757980 Jan 17 01:03:44 PM PST 24 Jan 17 01:09:49 PM PST 24 162760330321 ps
T790 /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1963874305 Jan 17 01:03:18 PM PST 24 Jan 17 01:06:52 PM PST 24 335604128188 ps
T791 /workspace/coverage/default/13.adc_ctrl_poweron_counter.1432413757 Jan 17 01:03:51 PM PST 24 Jan 17 01:03:58 PM PST 24 4808209230 ps
T792 /workspace/coverage/default/39.adc_ctrl_filters_interrupt.360952345 Jan 17 01:06:19 PM PST 24 Jan 17 01:09:39 PM PST 24 330789610899 ps
T793 /workspace/coverage/default/27.adc_ctrl_poweron_counter.3988778727 Jan 17 01:04:34 PM PST 24 Jan 17 01:04:37 PM PST 24 3022313619 ps
T794 /workspace/coverage/default/13.adc_ctrl_filters_wakeup.340349339 Jan 17 01:03:45 PM PST 24 Jan 17 01:05:53 PM PST 24 167652271119 ps
T795 /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.645317550 Jan 17 01:03:51 PM PST 24 Jan 17 01:04:45 PM PST 24 22014793809 ps
T796 /workspace/coverage/default/5.adc_ctrl_lowpower_counter.850620273 Jan 17 01:03:01 PM PST 24 Jan 17 01:03:41 PM PST 24 34771423249 ps
T797 /workspace/coverage/default/45.adc_ctrl_filters_polled.556811288 Jan 17 01:07:11 PM PST 24 Jan 17 01:10:50 PM PST 24 331263667036 ps
T798 /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1211450550 Jan 17 01:03:07 PM PST 24 Jan 17 01:04:28 PM PST 24 162811678846 ps
T799 /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1780992053 Jan 17 01:07:21 PM PST 24 Jan 17 01:08:28 PM PST 24 28970044375 ps
T800 /workspace/coverage/default/43.adc_ctrl_filters_interrupt.898173461 Jan 17 01:07:06 PM PST 24 Jan 17 01:08:41 PM PST 24 168112067495 ps
T801 /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1494377451 Jan 17 01:07:03 PM PST 24 Jan 17 01:07:34 PM PST 24 26068178350 ps
T802 /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3963379127 Jan 17 01:04:17 PM PST 24 Jan 17 01:05:43 PM PST 24 38729946153 ps
T803 /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2128950664 Jan 17 01:04:17 PM PST 24 Jan 17 01:07:19 PM PST 24 164415163288 ps
T804 /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4173510837 Jan 17 01:05:16 PM PST 24 Jan 17 01:11:33 PM PST 24 169264712227 ps
T805 /workspace/coverage/default/8.adc_ctrl_poweron_counter.3649680025 Jan 17 01:03:18 PM PST 24 Jan 17 01:03:25 PM PST 24 5471685896 ps
T806 /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.748424916 Jan 17 01:04:43 PM PST 24 Jan 17 01:16:34 PM PST 24 332062309035 ps
T807 /workspace/coverage/default/41.adc_ctrl_fsm_reset.2624383729 Jan 17 01:06:41 PM PST 24 Jan 17 01:18:47 PM PST 24 133957699849 ps
T808 /workspace/coverage/default/22.adc_ctrl_filters_both.209205007 Jan 17 01:04:06 PM PST 24 Jan 17 01:10:52 PM PST 24 328461783364 ps
T254 /workspace/coverage/default/7.adc_ctrl_clock_gating.4131749423 Jan 17 01:03:17 PM PST 24 Jan 17 01:06:36 PM PST 24 330433335713 ps
T809 /workspace/coverage/default/36.adc_ctrl_poweron_counter.3331849896 Jan 17 01:05:48 PM PST 24 Jan 17 01:05:50 PM PST 24 3819120616 ps
T810 /workspace/coverage/default/38.adc_ctrl_smoke.3237240322 Jan 17 01:05:59 PM PST 24 Jan 17 01:06:14 PM PST 24 5883578012 ps
T811 /workspace/coverage/default/40.adc_ctrl_alert_test.322193160 Jan 17 01:06:28 PM PST 24 Jan 17 01:06:29 PM PST 24 509978053 ps
T812 /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3565522648 Jan 17 01:03:17 PM PST 24 Jan 17 01:09:32 PM PST 24 325011192556 ps
T813 /workspace/coverage/default/35.adc_ctrl_filters_wakeup.453908829 Jan 17 01:05:36 PM PST 24 Jan 17 01:24:41 PM PST 24 511000656008 ps
T814 /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3865098761 Jan 17 01:06:29 PM PST 24 Jan 17 01:12:25 PM PST 24 324817683381 ps
T815 /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3093274692 Jan 17 01:05:46 PM PST 24 Jan 17 01:11:59 PM PST 24 164477045991 ps
T816 /workspace/coverage/default/41.adc_ctrl_stress_all.1803422203 Jan 17 01:06:36 PM PST 24 Jan 17 01:18:29 PM PST 24 327280820626 ps
T817 /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1080914859 Jan 17 01:07:45 PM PST 24 Jan 17 01:27:18 PM PST 24 493363224692 ps
T818 /workspace/coverage/default/30.adc_ctrl_alert_test.3774138123 Jan 17 01:05:06 PM PST 24 Jan 17 01:05:08 PM PST 24 312146141 ps
T819 /workspace/coverage/default/23.adc_ctrl_lowpower_counter.637419310 Jan 17 01:04:17 PM PST 24 Jan 17 01:04:43 PM PST 24 38209651897 ps
T820 /workspace/coverage/default/35.adc_ctrl_poweron_counter.361424469 Jan 17 01:05:37 PM PST 24 Jan 17 01:05:47 PM PST 24 3688086946 ps
T288 /workspace/coverage/default/28.adc_ctrl_filters_polled.1628858186 Jan 17 01:04:33 PM PST 24 Jan 17 01:07:43 PM PST 24 338645534370 ps
T821 /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1411078784 Jan 17 01:05:07 PM PST 24 Jan 17 01:06:44 PM PST 24 164200495970 ps
T822 /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1757087551 Jan 17 01:03:24 PM PST 24 Jan 17 01:06:24 PM PST 24 333902760954 ps
T823 /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3736852795 Jan 17 01:07:45 PM PST 24 Jan 17 01:08:48 PM PST 24 168340949204 ps
T824 /workspace/coverage/default/29.adc_ctrl_lowpower_counter.973191823 Jan 17 01:04:51 PM PST 24 Jan 17 01:05:07 PM PST 24 28370325841 ps
T825 /workspace/coverage/default/1.adc_ctrl_stress_all.2522260851 Jan 17 01:02:54 PM PST 24 Jan 17 01:04:54 PM PST 24 504004554660 ps
T233 /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.15924365 Jan 17 01:03:22 PM PST 24 Jan 17 01:08:11 PM PST 24 449123419751 ps
T826 /workspace/coverage/default/20.adc_ctrl_filters_both.2290345011 Jan 17 01:04:11 PM PST 24 Jan 17 01:08:46 PM PST 24 320467357026 ps
T827 /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3614854408 Jan 17 01:06:37 PM PST 24 Jan 17 01:14:46 PM PST 24 488874145157 ps
T828 /workspace/coverage/default/36.adc_ctrl_stress_all.1823333183 Jan 17 01:05:44 PM PST 24 Jan 17 01:20:52 PM PST 24 389148020935 ps
T829 /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2746804624 Jan 17 01:06:29 PM PST 24 Jan 17 01:19:45 PM PST 24 319507366048 ps
T830 /workspace/coverage/default/15.adc_ctrl_poweron_counter.3697517359 Jan 17 01:04:08 PM PST 24 Jan 17 01:04:20 PM PST 24 3617048690 ps
T831 /workspace/coverage/default/26.adc_ctrl_filters_polled.3819233353 Jan 17 01:04:28 PM PST 24 Jan 17 01:06:26 PM PST 24 493481840179 ps
T832 /workspace/coverage/default/32.adc_ctrl_stress_all.3915898251 Jan 17 01:05:13 PM PST 24 Jan 17 01:08:46 PM PST 24 347638150992 ps
T833 /workspace/coverage/default/37.adc_ctrl_filters_polled.2891285048 Jan 17 01:05:45 PM PST 24 Jan 17 01:07:31 PM PST 24 161568392109 ps
T834 /workspace/coverage/default/33.adc_ctrl_poweron_counter.1242272160 Jan 17 01:05:23 PM PST 24 Jan 17 01:05:29 PM PST 24 4659756996 ps
T835 /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2372878896 Jan 17 01:07:07 PM PST 24 Jan 17 01:10:08 PM PST 24 160720038108 ps
T836 /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3281254873 Jan 17 01:03:09 PM PST 24 Jan 17 01:07:35 PM PST 24 495458199052 ps
T837 /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2333257607 Jan 17 01:03:00 PM PST 24 Jan 17 01:15:38 PM PST 24 321982138407 ps
T838 /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.707319205 Jan 17 01:03:46 PM PST 24 Jan 17 01:22:17 PM PST 24 492127509515 ps
T839 /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2489356909 Jan 17 01:07:47 PM PST 24 Jan 17 01:21:20 PM PST 24 329614534914 ps
T840 /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1077463735 Jan 17 01:03:08 PM PST 24 Jan 17 01:03:31 PM PST 24 39357155249 ps
T841 /workspace/coverage/default/48.adc_ctrl_filters_both.1455120053 Jan 17 01:07:44 PM PST 24 Jan 17 01:11:08 PM PST 24 160178134145 ps
T342 /workspace/coverage/default/38.adc_ctrl_stress_all.3063682982 Jan 17 01:06:21 PM PST 24 Jan 17 01:23:50 PM PST 24 287909821485 ps
T842 /workspace/coverage/default/7.adc_ctrl_poweron_counter.2762356934 Jan 17 01:03:15 PM PST 24 Jan 17 01:03:22 PM PST 24 4974193435 ps
T843 /workspace/coverage/default/17.adc_ctrl_alert_test.2982151216 Jan 17 01:03:56 PM PST 24 Jan 17 01:04:03 PM PST 24 460682781 ps
T844 /workspace/coverage/default/49.adc_ctrl_clock_gating.4015044687 Jan 17 01:07:52 PM PST 24 Jan 17 01:09:31 PM PST 24 160809301676 ps
T845 /workspace/coverage/default/33.adc_ctrl_alert_test.1503782103 Jan 17 01:05:32 PM PST 24 Jan 17 01:05:35 PM PST 24 324623720 ps
T846 /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4293846253 Jan 17 01:03:08 PM PST 24 Jan 17 01:03:30 PM PST 24 31743383958 ps
T847 /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3181568597 Jan 17 01:03:38 PM PST 24 Jan 17 01:09:57 PM PST 24 330529454542 ps
T848 /workspace/coverage/default/33.adc_ctrl_filters_polled.2857690888 Jan 17 01:05:08 PM PST 24 Jan 17 01:06:39 PM PST 24 166283951387 ps
T849 /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1157433360 Jan 17 01:03:45 PM PST 24 Jan 17 01:16:59 PM PST 24 332678190463 ps
T315 /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1687588702 Jan 17 01:06:45 PM PST 24 Jan 17 01:10:13 PM PST 24 327065064808 ps
T850 /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1573012703 Jan 17 01:03:30 PM PST 24 Jan 17 01:13:32 PM PST 24 323003634684 ps
T851 /workspace/coverage/default/40.adc_ctrl_filters_both.3633742310 Jan 17 01:06:33 PM PST 24 Jan 17 01:08:07 PM PST 24 160218493079 ps
T852 /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2120694070 Jan 17 01:07:20 PM PST 24 Jan 17 01:24:28 PM PST 24 485301781171 ps
T853 /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1451617379 Jan 17 01:04:44 PM PST 24 Jan 17 01:09:14 PM PST 24 490939075403 ps
T854 /workspace/coverage/default/36.adc_ctrl_alert_test.3418935069 Jan 17 01:05:48 PM PST 24 Jan 17 01:05:50 PM PST 24 493773134 ps
T855 /workspace/coverage/default/15.adc_ctrl_alert_test.628254281 Jan 17 01:03:44 PM PST 24 Jan 17 01:03:46 PM PST 24 293126920 ps
T856 /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.964827955 Jan 17 01:07:29 PM PST 24 Jan 17 01:09:55 PM PST 24 78819143612 ps
T857 /workspace/coverage/default/5.adc_ctrl_poweron_counter.1393298970 Jan 17 01:03:00 PM PST 24 Jan 17 01:03:14 PM PST 24 4262050972 ps
T858 /workspace/coverage/default/40.adc_ctrl_smoke.4122898623 Jan 17 01:06:28 PM PST 24 Jan 17 01:06:33 PM PST 24 5731691552 ps
T859 /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.408769643 Jan 17 01:04:07 PM PST 24 Jan 17 01:05:32 PM PST 24 486429152338 ps
T860 /workspace/coverage/default/5.adc_ctrl_filters_both.2493293409 Jan 17 01:03:03 PM PST 24 Jan 17 01:08:02 PM PST 24 167285649397 ps
T861 /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2136658454 Jan 17 01:02:43 PM PST 24 Jan 17 01:04:26 PM PST 24 163004217746 ps
T862 /workspace/coverage/default/34.adc_ctrl_alert_test.2580753029 Jan 17 01:05:34 PM PST 24 Jan 17 01:05:36 PM PST 24 418403190 ps
T863 /workspace/coverage/default/43.adc_ctrl_smoke.1102337741 Jan 17 01:06:47 PM PST 24 Jan 17 01:06:50 PM PST 24 5781282927 ps
T282 /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1578537274 Jan 17 01:02:53 PM PST 24 Jan 17 01:06:11 PM PST 24 166775921881 ps
T864 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1230340842 Jan 17 12:30:22 PM PST 24 Jan 17 12:30:31 PM PST 24 2370308793 ps
T865 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.83309595 Jan 17 12:30:22 PM PST 24 Jan 17 12:30:28 PM PST 24 373732880 ps
T866 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2848580424 Jan 17 12:30:27 PM PST 24 Jan 17 12:30:32 PM PST 24 323245532 ps
T867 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1921359668 Jan 17 12:30:22 PM PST 24 Jan 17 12:30:34 PM PST 24 4269060863 ps
T868 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3260227974 Jan 17 12:30:37 PM PST 24 Jan 17 12:30:46 PM PST 24 4707542226 ps
T869 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2514523551 Jan 17 12:30:52 PM PST 24 Jan 17 12:30:55 PM PST 24 361713793 ps
T870 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3733328653 Jan 17 12:30:13 PM PST 24 Jan 17 12:30:19 PM PST 24 4260459137 ps
T871 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.401977689 Jan 17 12:30:24 PM PST 24 Jan 17 12:30:30 PM PST 24 583549173 ps
T872 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3678260309 Jan 17 12:30:32 PM PST 24 Jan 17 12:30:36 PM PST 24 497268864 ps
T873 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4127728475 Jan 17 12:30:24 PM PST 24 Jan 17 12:30:29 PM PST 24 331512279 ps
T874 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2791088836 Jan 17 12:30:23 PM PST 24 Jan 17 12:30:29 PM PST 24 442407465 ps
T875 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1429839512 Jan 17 12:30:40 PM PST 24 Jan 17 12:30:42 PM PST 24 383635277 ps
T876 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.489795414 Jan 17 12:30:21 PM PST 24 Jan 17 12:30:22 PM PST 24 541003860 ps
T877 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.284805868 Jan 17 12:30:26 PM PST 24 Jan 17 12:30:34 PM PST 24 4595582305 ps
T878 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.384110322 Jan 17 12:30:41 PM PST 24 Jan 17 12:30:44 PM PST 24 1413591132 ps
T879 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1674640344 Jan 17 12:30:33 PM PST 24 Jan 17 12:30:44 PM PST 24 1607906784 ps
T880 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2880387850 Jan 17 12:30:24 PM PST 24 Jan 17 12:30:38 PM PST 24 3805578790 ps
T881 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3052449049 Jan 17 12:30:31 PM PST 24 Jan 17 12:30:35 PM PST 24 307051538 ps
T882 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2958181957 Jan 17 12:30:30 PM PST 24 Jan 17 12:30:35 PM PST 24 388190853 ps
T883 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3053569150 Jan 17 12:30:22 PM PST 24 Jan 17 12:30:29 PM PST 24 851869367 ps
T884 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1617760391 Jan 17 12:30:10 PM PST 24 Jan 17 12:30:13 PM PST 24 1170058159 ps
T885 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4271354348 Jan 17 12:30:49 PM PST 24 Jan 17 12:30:53 PM PST 24 485122513 ps
T886 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3063531177 Jan 17 12:30:54 PM PST 24 Jan 17 12:30:56 PM PST 24 627393992 ps
T887 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4130589450 Jan 17 12:30:25 PM PST 24 Jan 17 12:30:33 PM PST 24 756460641 ps
T888 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.979241033 Jan 17 12:30:38 PM PST 24 Jan 17 12:30:42 PM PST 24 524474714 ps
T889 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1100598113 Jan 17 12:30:40 PM PST 24 Jan 17 12:30:42 PM PST 24 581935137 ps
T890 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2934678805 Jan 17 12:30:35 PM PST 24 Jan 17 12:30:53 PM PST 24 12839518383 ps
T891 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2650666489 Jan 17 12:30:32 PM PST 24 Jan 17 12:30:36 PM PST 24 425615500 ps
T892 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.189765569 Jan 17 12:30:28 PM PST 24 Jan 17 12:30:37 PM PST 24 2466494678 ps
T893 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1235138819 Jan 17 12:30:34 PM PST 24 Jan 17 12:30:38 PM PST 24 520593282 ps
T894 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1767882795 Jan 17 12:30:28 PM PST 24 Jan 17 12:30:33 PM PST 24 600514329 ps
T895 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.948939225 Jan 17 12:30:34 PM PST 24 Jan 17 12:30:38 PM PST 24 310667029 ps
T896 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1677441585 Jan 17 12:30:10 PM PST 24 Jan 17 12:30:14 PM PST 24 430918533 ps
T897 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.163264332 Jan 17 12:30:30 PM PST 24 Jan 17 12:30:35 PM PST 24 566644509 ps
T898 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2744700351 Jan 17 12:30:50 PM PST 24 Jan 17 12:30:53 PM PST 24 344012014 ps
T899 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2655370086 Jan 17 12:30:20 PM PST 24 Jan 17 12:30:22 PM PST 24 410695894 ps
T900 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3381806897 Jan 17 12:30:54 PM PST 24 Jan 17 12:30:57 PM PST 24 465407058 ps
T901 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4232514635 Jan 17 12:30:28 PM PST 24 Jan 17 12:30:32 PM PST 24 377066411 ps
T902 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4139689420 Jan 17 12:30:29 PM PST 24 Jan 17 12:30:39 PM PST 24 550290726 ps
T903 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3934871361 Jan 17 12:30:40 PM PST 24 Jan 17 12:30:43 PM PST 24 4154425603 ps
T904 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.718173940 Jan 17 12:30:56 PM PST 24 Jan 17 12:30:59 PM PST 24 524022559 ps
T905 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.308496105 Jan 17 12:30:08 PM PST 24 Jan 17 12:30:11 PM PST 24 583878126 ps
T906 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2106358340 Jan 17 12:30:47 PM PST 24 Jan 17 12:30:54 PM PST 24 4498558138 ps
T907 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1618589336 Jan 17 12:30:28 PM PST 24 Jan 17 12:30:34 PM PST 24 480989962 ps
T908 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2070957592 Jan 17 12:30:31 PM PST 24 Jan 17 12:30:35 PM PST 24 462300674 ps
T909 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2852837948 Jan 17 12:30:30 PM PST 24 Jan 17 12:30:34 PM PST 24 326906810 ps
T910 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.67804822 Jan 17 12:30:30 PM PST 24 Jan 17 12:30:39 PM PST 24 483479710 ps
T911 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3303216918 Jan 17 12:30:37 PM PST 24 Jan 17 12:30:53 PM PST 24 2637165055 ps
T912 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3511231788 Jan 17 12:30:22 PM PST 24 Jan 17 12:30:28 PM PST 24 284067402 ps
T913 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2320707970 Jan 17 12:30:31 PM PST 24 Jan 17 12:30:35 PM PST 24 600722110 ps
T914 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3462950198 Jan 17 12:30:41 PM PST 24 Jan 17 12:30:42 PM PST 24 461567753 ps

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3155292762
Short name T5
Test name
Test status
Simulation time 620206865 ps
CPU time 1.98 seconds
Started Jan 17 12:30:46 PM PST 24
Finished Jan 17 12:30:49 PM PST 24
Peak memory 200648 kb
Host smart-77dcd67e-bd4c-4152-8cce-a23b1a81a71a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155292762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3155292762
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1014713125
Short name T7
Test name
Test status
Simulation time 1039248534 ps
CPU time 2.9 seconds
Started Jan 17 12:30:10 PM PST 24
Finished Jan 17 12:30:14 PM PST 24
Peak memory 200624 kb
Host smart-9b1e8aee-8ae8-4b91-85a8-208696531c29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014713125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1014713125
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.4291656939
Short name T13
Test name
Test status
Simulation time 495458994741 ps
CPU time 315.27 seconds
Started Jan 17 01:05:04 PM PST 24
Finished Jan 17 01:10:21 PM PST 24
Peak memory 201096 kb
Host smart-b08a68f3-d230-4e2d-9497-baf0ca6d18e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291656939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.4291656939
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3065553105
Short name T209
Test name
Test status
Simulation time 502307317994 ps
CPU time 287.71 seconds
Started Jan 17 01:02:58 PM PST 24
Finished Jan 17 01:07:47 PM PST 24
Peak memory 200860 kb
Host smart-ffc3caef-0daf-4d5d-b1dc-8681a5ff831a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065553105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3065553105
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1837795578
Short name T12
Test name
Test status
Simulation time 438031390555 ps
CPU time 161.02 seconds
Started Jan 17 01:03:07 PM PST 24
Finished Jan 17 01:05:49 PM PST 24
Peak memory 201008 kb
Host smart-bf95f0c0-1934-483a-af25-7b64f9769ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837795578 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1837795578
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.322916660
Short name T228
Test name
Test status
Simulation time 659406685149 ps
CPU time 394.96 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:10:37 PM PST 24
Peak memory 200804 kb
Host smart-f792b677-7f21-4ae4-acec-7089116de857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322916660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
322916660
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2818784473
Short name T172
Test name
Test status
Simulation time 318596769 ps
CPU time 1 seconds
Started Jan 17 12:30:20 PM PST 24
Finished Jan 17 12:30:22 PM PST 24
Peak memory 200324 kb
Host smart-9bd99e70-a834-4727-9fac-5d057a5ad7a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818784473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2818784473
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.76220502
Short name T116
Test name
Test status
Simulation time 499418278311 ps
CPU time 1102.49 seconds
Started Jan 17 01:02:55 PM PST 24
Finished Jan 17 01:21:19 PM PST 24
Peak memory 200836 kb
Host smart-65c0d45e-32d5-46fc-aa6e-70bcb7e7d961
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76220502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating
.76220502
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.733109598
Short name T106
Test name
Test status
Simulation time 505682358564 ps
CPU time 581.27 seconds
Started Jan 17 01:03:19 PM PST 24
Finished Jan 17 01:13:02 PM PST 24
Peak memory 200916 kb
Host smart-552af9df-2562-4b60-905b-ba3665a65259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733109598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.733109598
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3834601504
Short name T44
Test name
Test status
Simulation time 647325340883 ps
CPU time 570.35 seconds
Started Jan 17 01:05:06 PM PST 24
Finished Jan 17 01:14:37 PM PST 24
Peak memory 209580 kb
Host smart-3e323da9-270d-42c8-808e-e598430b9320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834601504 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3834601504
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1102616222
Short name T105
Test name
Test status
Simulation time 491673025085 ps
CPU time 1163.22 seconds
Started Jan 17 01:07:43 PM PST 24
Finished Jan 17 01:27:09 PM PST 24
Peak memory 200764 kb
Host smart-3484f3ee-8f58-46ac-bcd6-c8b5315bb0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102616222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1102616222
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3859191971
Short name T255
Test name
Test status
Simulation time 336513483975 ps
CPU time 677.07 seconds
Started Jan 17 01:03:50 PM PST 24
Finished Jan 17 01:15:09 PM PST 24
Peak memory 200904 kb
Host smart-6cfc12ae-8949-40a8-8f77-3c6b1ed541e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859191971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3859191971
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2886299490
Short name T98
Test name
Test status
Simulation time 303230532864 ps
CPU time 260.47 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:08:06 PM PST 24
Peak memory 209788 kb
Host smart-cb35d353-7653-43af-a3d6-112afd48a1d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886299490 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2886299490
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3329475145
Short name T278
Test name
Test status
Simulation time 492665326521 ps
CPU time 893.26 seconds
Started Jan 17 01:07:19 PM PST 24
Finished Jan 17 01:22:14 PM PST 24
Peak memory 200752 kb
Host smart-33e9af97-be28-48f1-99a8-b43d9dfd76a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329475145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3329475145
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1674766500
Short name T1
Test name
Test status
Simulation time 8263846940 ps
CPU time 20.51 seconds
Started Jan 17 12:30:49 PM PST 24
Finished Jan 17 12:31:10 PM PST 24
Peak memory 200660 kb
Host smart-cc95c03c-0b17-4fd2-ac34-d7e054861009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674766500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1674766500
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.152008307
Short name T107
Test name
Test status
Simulation time 500980737595 ps
CPU time 210.18 seconds
Started Jan 17 01:07:31 PM PST 24
Finished Jan 17 01:11:02 PM PST 24
Peak memory 200744 kb
Host smart-90a308a2-8a6a-4e6f-860a-ac17bd6af5d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152008307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.152008307
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.47703990
Short name T217
Test name
Test status
Simulation time 501975293107 ps
CPU time 1126.72 seconds
Started Jan 17 01:07:43 PM PST 24
Finished Jan 17 01:26:32 PM PST 24
Peak memory 200872 kb
Host smart-2a4faba5-92f3-482d-a476-97fc5c4136fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47703990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.47703990
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.934644879
Short name T210
Test name
Test status
Simulation time 162832684071 ps
CPU time 201.72 seconds
Started Jan 17 01:07:46 PM PST 24
Finished Jan 17 01:11:10 PM PST 24
Peak memory 200848 kb
Host smart-58c0e9e0-9e4c-4133-9c23-c800e8370ad2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=934644879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.934644879
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1143058235
Short name T120
Test name
Test status
Simulation time 334142236405 ps
CPU time 52.32 seconds
Started Jan 17 01:04:36 PM PST 24
Finished Jan 17 01:05:30 PM PST 24
Peak memory 200972 kb
Host smart-03548267-fd7d-4a80-ab93-a5e408c3bc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143058235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1143058235
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4129798189
Short name T94
Test name
Test status
Simulation time 324650268438 ps
CPU time 199.21 seconds
Started Jan 17 01:04:23 PM PST 24
Finished Jan 17 01:07:42 PM PST 24
Peak memory 200952 kb
Host smart-98928b19-d9f5-44d9-98d5-b9e6ed587158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129798189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4129798189
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.336836072
Short name T198
Test name
Test status
Simulation time 496202521488 ps
CPU time 1226.21 seconds
Started Jan 17 01:04:28 PM PST 24
Finished Jan 17 01:24:55 PM PST 24
Peak memory 200896 kb
Host smart-3706ef28-b768-4a7d-aeb3-920021a60f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336836072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.336836072
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2979106182
Short name T17
Test name
Test status
Simulation time 495458390227 ps
CPU time 287.03 seconds
Started Jan 17 01:03:07 PM PST 24
Finished Jan 17 01:07:55 PM PST 24
Peak memory 200756 kb
Host smart-4e57a940-aee4-4e53-98d5-65095ea9d565
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979106182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2979106182
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2089556560
Short name T241
Test name
Test status
Simulation time 490724870450 ps
CPU time 1064.65 seconds
Started Jan 17 01:06:27 PM PST 24
Finished Jan 17 01:24:12 PM PST 24
Peak memory 200824 kb
Host smart-f7680b20-e039-4fd8-b2a4-e4a5fb7c16f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089556560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2089556560
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2475434300
Short name T49
Test name
Test status
Simulation time 8799457131 ps
CPU time 6.4 seconds
Started Jan 17 01:02:50 PM PST 24
Finished Jan 17 01:02:57 PM PST 24
Peak memory 217116 kb
Host smart-e79ff6cf-9fe3-46c0-aec0-dfebb6b9e306
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475434300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2475434300
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1458808228
Short name T130
Test name
Test status
Simulation time 490395588470 ps
CPU time 190.78 seconds
Started Jan 17 01:04:53 PM PST 24
Finished Jan 17 01:08:09 PM PST 24
Peak memory 200868 kb
Host smart-9cde24fc-c95d-4cb4-88f7-9e62fc17cd27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458808228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1458808228
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.174524339
Short name T114
Test name
Test status
Simulation time 503186613030 ps
CPU time 97.13 seconds
Started Jan 17 01:05:24 PM PST 24
Finished Jan 17 01:07:02 PM PST 24
Peak memory 200784 kb
Host smart-08e26c4a-d47d-4826-81d1-9a38078ae391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174524339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.174524339
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2214630966
Short name T27
Test name
Test status
Simulation time 719093031 ps
CPU time 3.31 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:28 PM PST 24
Peak memory 216956 kb
Host smart-90493c60-55ee-4056-8ee6-656f9e93f8d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214630966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2214630966
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2298886674
Short name T29
Test name
Test status
Simulation time 2376158114 ps
CPU time 5.32 seconds
Started Jan 17 12:30:41 PM PST 24
Finished Jan 17 12:30:47 PM PST 24
Peak memory 200480 kb
Host smart-3a3efccf-7604-4cf5-b9cc-45071e3c3c39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298886674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2298886674
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.95737517
Short name T183
Test name
Test status
Simulation time 241892058268 ps
CPU time 255.97 seconds
Started Jan 17 01:05:42 PM PST 24
Finished Jan 17 01:09:58 PM PST 24
Peak memory 201236 kb
Host smart-7bafe0b4-aebf-4550-8520-dedd1cb62c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95737517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.95737517
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3323359330
Short name T301
Test name
Test status
Simulation time 335025510221 ps
CPU time 250.97 seconds
Started Jan 17 01:06:41 PM PST 24
Finished Jan 17 01:10:54 PM PST 24
Peak memory 200784 kb
Host smart-4e972ce3-6fa7-4642-8f40-847bee0fbff1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323359330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3323359330
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.599600741
Short name T238
Test name
Test status
Simulation time 487093577193 ps
CPU time 1049.5 seconds
Started Jan 17 01:03:32 PM PST 24
Finished Jan 17 01:21:04 PM PST 24
Peak memory 200852 kb
Host smart-2f5063f2-4e5e-4cca-b611-a9ea404523dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599600741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
599600741
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3367502242
Short name T181
Test name
Test status
Simulation time 281588624388 ps
CPU time 392.31 seconds
Started Jan 17 01:02:47 PM PST 24
Finished Jan 17 01:09:21 PM PST 24
Peak memory 201376 kb
Host smart-656fec18-0aaa-4f82-9735-360f62a603b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367502242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3367502242
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3611625512
Short name T258
Test name
Test status
Simulation time 279682300794 ps
CPU time 376.7 seconds
Started Jan 17 01:03:37 PM PST 24
Finished Jan 17 01:09:55 PM PST 24
Peak memory 201384 kb
Host smart-9df351c7-3e16-4398-9536-4ab78db2b505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611625512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3611625512
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.735129677
Short name T204
Test name
Test status
Simulation time 486784021686 ps
CPU time 352.8 seconds
Started Jan 17 01:04:49 PM PST 24
Finished Jan 17 01:10:44 PM PST 24
Peak memory 200696 kb
Host smart-cfc8b27d-7348-4fa2-a4ef-9ed9c68d561b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735129677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.735129677
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4224579259
Short name T164
Test name
Test status
Simulation time 499063741326 ps
CPU time 263.99 seconds
Started Jan 17 01:05:06 PM PST 24
Finished Jan 17 01:09:31 PM PST 24
Peak memory 200884 kb
Host smart-df5e471d-7fcc-429c-8676-333532e4bade
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224579259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4224579259
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1654026378
Short name T221
Test name
Test status
Simulation time 492549451109 ps
CPU time 638.59 seconds
Started Jan 17 01:07:08 PM PST 24
Finished Jan 17 01:17:49 PM PST 24
Peak memory 200868 kb
Host smart-d473c72b-3955-4b9a-b1b8-fe696b612cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654026378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1654026378
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.15924365
Short name T233
Test name
Test status
Simulation time 449123419751 ps
CPU time 287.57 seconds
Started Jan 17 01:03:22 PM PST 24
Finished Jan 17 01:08:11 PM PST 24
Peak memory 210820 kb
Host smart-65b815a1-a38d-4fe4-a7b4-e049315e0708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15924365 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.15924365
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2928545054
Short name T15
Test name
Test status
Simulation time 162322624044 ps
CPU time 375.91 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:12:37 PM PST 24
Peak memory 200892 kb
Host smart-e52e80f7-2a28-4b5c-913d-9e86e872b734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928545054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2928545054
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4046392493
Short name T239
Test name
Test status
Simulation time 17377144946 ps
CPU time 41.41 seconds
Started Jan 17 01:04:49 PM PST 24
Finished Jan 17 01:05:31 PM PST 24
Peak memory 200948 kb
Host smart-e559c207-6d21-4ca3-9eac-d4a7db3314fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046392493 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4046392493
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3924232250
Short name T253
Test name
Test status
Simulation time 332376646647 ps
CPU time 205.91 seconds
Started Jan 17 01:02:45 PM PST 24
Finished Jan 17 01:06:13 PM PST 24
Peak memory 200868 kb
Host smart-fe3f0989-0ff3-4bf1-906f-7e11b63f8e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924232250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3924232250
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2661232351
Short name T143
Test name
Test status
Simulation time 288847233302 ps
CPU time 712.01 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:15:38 PM PST 24
Peak memory 201284 kb
Host smart-7f022533-ca16-4077-b099-dba7f3669765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661232351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2661232351
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.292882284
Short name T305
Test name
Test status
Simulation time 88867229994 ps
CPU time 54.34 seconds
Started Jan 17 01:04:12 PM PST 24
Finished Jan 17 01:05:06 PM PST 24
Peak memory 201008 kb
Host smart-92c013c4-3d4a-41a8-866b-988f5fd61f9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292882284 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.292882284
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2996903955
Short name T268
Test name
Test status
Simulation time 164641597420 ps
CPU time 368.26 seconds
Started Jan 17 01:03:55 PM PST 24
Finished Jan 17 01:10:10 PM PST 24
Peak memory 200892 kb
Host smart-df50e35f-998b-4c5b-9840-f16d7a903ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996903955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2996903955
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2081727934
Short name T285
Test name
Test status
Simulation time 158821327587 ps
CPU time 348.58 seconds
Started Jan 17 01:02:52 PM PST 24
Finished Jan 17 01:08:42 PM PST 24
Peak memory 200916 kb
Host smart-4eba5400-e48a-47ce-88c8-641d5173034f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081727934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2081727934
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2051904917
Short name T138
Test name
Test status
Simulation time 492411280692 ps
CPU time 296.96 seconds
Started Jan 17 01:04:50 PM PST 24
Finished Jan 17 01:09:48 PM PST 24
Peak memory 200824 kb
Host smart-146da1a6-9eea-4bd0-ba6e-2497c78e8fec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051904917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2051904917
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3587894998
Short name T149
Test name
Test status
Simulation time 484048319447 ps
CPU time 360.73 seconds
Started Jan 17 01:05:34 PM PST 24
Finished Jan 17 01:11:35 PM PST 24
Peak memory 201092 kb
Host smart-244a9163-5b41-4a60-9fb5-49c135f5d772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587894998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3587894998
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3144051302
Short name T251
Test name
Test status
Simulation time 497444809052 ps
CPU time 1193.31 seconds
Started Jan 17 01:02:53 PM PST 24
Finished Jan 17 01:22:47 PM PST 24
Peak memory 200848 kb
Host smart-91df3f22-3952-4495-9322-f0b802a08bbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144051302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3144051302
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2281661310
Short name T414
Test name
Test status
Simulation time 329014082141 ps
CPU time 785.43 seconds
Started Jan 17 01:03:36 PM PST 24
Finished Jan 17 01:16:42 PM PST 24
Peak memory 200932 kb
Host smart-12031ead-9513-499f-8116-7a059fabc5e9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281661310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2281661310
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1121238788
Short name T225
Test name
Test status
Simulation time 337158653620 ps
CPU time 55.84 seconds
Started Jan 17 01:04:43 PM PST 24
Finished Jan 17 01:05:40 PM PST 24
Peak memory 200976 kb
Host smart-8d629c68-a0c2-4f61-8784-1c1d31fadff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121238788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1121238788
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1859488792
Short name T137
Test name
Test status
Simulation time 486398528545 ps
CPU time 332.76 seconds
Started Jan 17 01:04:42 PM PST 24
Finished Jan 17 01:10:16 PM PST 24
Peak memory 200884 kb
Host smart-ebd9cf20-e0aa-4b0e-87be-1af52fe2aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859488792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1859488792
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3793411372
Short name T117
Test name
Test status
Simulation time 488292497381 ps
CPU time 535.46 seconds
Started Jan 17 01:03:01 PM PST 24
Finished Jan 17 01:11:59 PM PST 24
Peak memory 200872 kb
Host smart-2783228c-4c77-418b-9709-99c6c92e1700
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793411372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3793411372
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3118101584
Short name T174
Test name
Test status
Simulation time 462328207 ps
CPU time 0.86 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:29 PM PST 24
Peak memory 200124 kb
Host smart-a4bc707b-9d86-4b56-b027-f385bc4d8c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118101584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3118101584
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1749180912
Short name T266
Test name
Test status
Simulation time 326203927577 ps
CPU time 740.25 seconds
Started Jan 17 01:02:55 PM PST 24
Finished Jan 17 01:15:16 PM PST 24
Peak memory 200892 kb
Host smart-14e0fa05-4e44-488d-8ae0-ba6368eded49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749180912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1749180912
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2287733060
Short name T323
Test name
Test status
Simulation time 490078279504 ps
CPU time 1165.99 seconds
Started Jan 17 01:07:06 PM PST 24
Finished Jan 17 01:26:35 PM PST 24
Peak memory 201160 kb
Host smart-a35b7693-de94-4224-928b-a626d08a54a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287733060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2287733060
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1709764046
Short name T291
Test name
Test status
Simulation time 538437363462 ps
CPU time 632.83 seconds
Started Jan 17 01:07:22 PM PST 24
Finished Jan 17 01:17:56 PM PST 24
Peak memory 200788 kb
Host smart-cf2ac4f7-5503-4a71-8464-50a8caea18a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709764046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1709764046
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4131749423
Short name T254
Test name
Test status
Simulation time 330433335713 ps
CPU time 194.89 seconds
Started Jan 17 01:03:17 PM PST 24
Finished Jan 17 01:06:36 PM PST 24
Peak memory 200916 kb
Host smart-fd932b7d-39e0-455c-adff-f35b94e64984
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131749423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4131749423
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.916181199
Short name T222
Test name
Test status
Simulation time 490979045953 ps
CPU time 1094.51 seconds
Started Jan 17 01:03:10 PM PST 24
Finished Jan 17 01:21:27 PM PST 24
Peak memory 200928 kb
Host smart-d1227ff1-5459-4ba0-9dd9-55b682871a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916181199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.916181199
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.659685247
Short name T271
Test name
Test status
Simulation time 316592851874 ps
CPU time 95.79 seconds
Started Jan 17 01:03:40 PM PST 24
Finished Jan 17 01:05:17 PM PST 24
Peak memory 200876 kb
Host smart-06fae774-440a-4c2a-b8ab-4db8b4c52540
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659685247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.659685247
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2552765501
Short name T259
Test name
Test status
Simulation time 488570759642 ps
CPU time 253.72 seconds
Started Jan 17 01:04:41 PM PST 24
Finished Jan 17 01:08:55 PM PST 24
Peak memory 200864 kb
Host smart-6f3f942d-0d49-4db7-8f67-107259dc3b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552765501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2552765501
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1149664758
Short name T329
Test name
Test status
Simulation time 8741367481 ps
CPU time 17.72 seconds
Started Jan 17 12:30:33 PM PST 24
Finished Jan 17 12:30:53 PM PST 24
Peak memory 200724 kb
Host smart-84490669-dea7-4d93-8204-a05c724c20cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149664758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1149664758
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2180694115
Short name T423
Test name
Test status
Simulation time 492212825 ps
CPU time 1.66 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:03:23 PM PST 24
Peak memory 200556 kb
Host smart-bacd90af-4faa-4561-ad4b-17459ee5d08a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180694115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2180694115
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1182051305
Short name T178
Test name
Test status
Simulation time 126490220380 ps
CPU time 435.84 seconds
Started Jan 17 01:02:47 PM PST 24
Finished Jan 17 01:10:05 PM PST 24
Peak memory 201308 kb
Host smart-c3cb6f0a-4590-41a4-8ed2-d24edd530602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182051305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1182051305
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.777351492
Short name T309
Test name
Test status
Simulation time 495947020734 ps
CPU time 1163.17 seconds
Started Jan 17 01:03:21 PM PST 24
Finished Jan 17 01:22:45 PM PST 24
Peak memory 200940 kb
Host smart-39308ffb-e80f-43e6-8004-53b8cc8026cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777351492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.777351492
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2477215555
Short name T267
Test name
Test status
Simulation time 278158520540 ps
CPU time 435.04 seconds
Started Jan 17 01:04:05 PM PST 24
Finished Jan 17 01:11:20 PM PST 24
Peak memory 201312 kb
Host smart-982ac778-a099-4f04-bba7-1a650e8fd83d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477215555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2477215555
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4045931434
Short name T207
Test name
Test status
Simulation time 331732514042 ps
CPU time 777.25 seconds
Started Jan 17 01:03:01 PM PST 24
Finished Jan 17 01:16:01 PM PST 24
Peak memory 200980 kb
Host smart-d199f0f0-c18e-44f1-b9d3-66b6e8831e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045931434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4045931434
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3558190423
Short name T87
Test name
Test status
Simulation time 74844363403 ps
CPU time 46.68 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:03:37 PM PST 24
Peak memory 209252 kb
Host smart-8743326f-d577-4f74-a1d5-d302e816177f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558190423 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3558190423
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.4179714349
Short name T195
Test name
Test status
Simulation time 1728277434086 ps
CPU time 1344.68 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:26:11 PM PST 24
Peak memory 210724 kb
Host smart-2868dac1-947d-404e-b52d-22ff0c63ce9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179714349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.4179714349
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1191577876
Short name T284
Test name
Test status
Simulation time 500130736375 ps
CPU time 179.48 seconds
Started Jan 17 01:03:40 PM PST 24
Finished Jan 17 01:06:40 PM PST 24
Peak memory 200960 kb
Host smart-dc3e5999-f466-430f-bd03-cc964feb5543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191577876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1191577876
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2529708414
Short name T340
Test name
Test status
Simulation time 126652878027 ps
CPU time 673.64 seconds
Started Jan 17 01:04:18 PM PST 24
Finished Jan 17 01:15:32 PM PST 24
Peak memory 201320 kb
Host smart-3e1d12f1-cf4e-4dea-8c85-902cc337d63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529708414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2529708414
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2920393425
Short name T161
Test name
Test status
Simulation time 499804817490 ps
CPU time 271.79 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:08:49 PM PST 24
Peak memory 200804 kb
Host smart-592de19d-9ac7-442a-806a-5d4116a0dfb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920393425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2920393425
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4125366362
Short name T302
Test name
Test status
Simulation time 370489884306 ps
CPU time 145.17 seconds
Started Jan 17 01:05:15 PM PST 24
Finished Jan 17 01:07:41 PM PST 24
Peak memory 217296 kb
Host smart-6ef1d34f-2397-4bff-a4fc-a06c397265c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125366362 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4125366362
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1116045653
Short name T658
Test name
Test status
Simulation time 503307930162 ps
CPU time 346.49 seconds
Started Jan 17 01:05:25 PM PST 24
Finished Jan 17 01:11:12 PM PST 24
Peak memory 201252 kb
Host smart-5e43ac8d-0a71-4be6-962d-40436d1a4787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116045653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1116045653
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.955052888
Short name T230
Test name
Test status
Simulation time 325750104401 ps
CPU time 104.42 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:05:06 PM PST 24
Peak memory 200940 kb
Host smart-b8d04410-368e-4110-b977-95134e370b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955052888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.955052888
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3859883302
Short name T40
Test name
Test status
Simulation time 94425502923 ps
CPU time 476.22 seconds
Started Jan 17 01:03:50 PM PST 24
Finished Jan 17 01:11:48 PM PST 24
Peak memory 201292 kb
Host smart-6b6463c8-6fb1-4d33-92da-a8b95072bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859883302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3859883302
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1306391677
Short name T275
Test name
Test status
Simulation time 496446495593 ps
CPU time 292.15 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:07:56 PM PST 24
Peak memory 200840 kb
Host smart-7c8f0e3c-96bf-406a-ac8e-4ab18ed7212b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306391677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1306391677
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.932523140
Short name T218
Test name
Test status
Simulation time 168867084538 ps
CPU time 139.69 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:06:37 PM PST 24
Peak memory 200732 kb
Host smart-108231c5-db2d-49ca-b353-d366512a85ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932523140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.932523140
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3939816066
Short name T306
Test name
Test status
Simulation time 326914387775 ps
CPU time 756.16 seconds
Started Jan 17 01:04:22 PM PST 24
Finished Jan 17 01:16:59 PM PST 24
Peak memory 200940 kb
Host smart-903deff5-b8bd-4345-ba42-6cf5176a1de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939816066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3939816066
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.694804191
Short name T260
Test name
Test status
Simulation time 343234087328 ps
CPU time 557.53 seconds
Started Jan 17 01:05:17 PM PST 24
Finished Jan 17 01:14:35 PM PST 24
Peak memory 200840 kb
Host smart-1d110921-231d-4695-bc81-5c823c59d6b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694804191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.694804191
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.817279003
Short name T123
Test name
Test status
Simulation time 92033647929 ps
CPU time 229.21 seconds
Started Jan 17 01:05:44 PM PST 24
Finished Jan 17 01:09:34 PM PST 24
Peak memory 209564 kb
Host smart-d5fe2d55-e8d3-4042-9deb-e422d98f9560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817279003 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.817279003
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3063682982
Short name T342
Test name
Test status
Simulation time 287909821485 ps
CPU time 1047.85 seconds
Started Jan 17 01:06:21 PM PST 24
Finished Jan 17 01:23:50 PM PST 24
Peak memory 201360 kb
Host smart-6c1e764d-dc60-48c8-b5db-2f281308f2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063682982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3063682982
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.431328733
Short name T336
Test name
Test status
Simulation time 71424619225 ps
CPU time 234.9 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:10:16 PM PST 24
Peak memory 201344 kb
Host smart-ba0d8128-7a02-4250-9430-22f4b53f38a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431328733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.431328733
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1106502811
Short name T191
Test name
Test status
Simulation time 97342490744 ps
CPU time 152.88 seconds
Started Jan 17 01:06:18 PM PST 24
Finished Jan 17 01:08:54 PM PST 24
Peak memory 215384 kb
Host smart-eac5b32b-6556-47a7-b1e4-516de848b3e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106502811 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1106502811
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1173239246
Short name T62
Test name
Test status
Simulation time 163032421808 ps
CPU time 33.69 seconds
Started Jan 17 01:06:30 PM PST 24
Finished Jan 17 01:07:04 PM PST 24
Peak memory 200864 kb
Host smart-d123e83a-db31-4509-8b59-22af5747eebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173239246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1173239246
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3603089392
Short name T100
Test name
Test status
Simulation time 492496397236 ps
CPU time 558.13 seconds
Started Jan 17 01:06:36 PM PST 24
Finished Jan 17 01:16:00 PM PST 24
Peak memory 200872 kb
Host smart-33b770b8-128b-4d34-8279-68aefe5e74fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603089392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3603089392
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3652585894
Short name T190
Test name
Test status
Simulation time 134653799752 ps
CPU time 743.64 seconds
Started Jan 17 01:07:50 PM PST 24
Finished Jan 17 01:20:20 PM PST 24
Peak memory 201368 kb
Host smart-301cd3d6-9622-4733-8adb-b5c2720bc0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652585894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3652585894
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1576511812
Short name T201
Test name
Test status
Simulation time 330049611901 ps
CPU time 196.71 seconds
Started Jan 17 01:03:15 PM PST 24
Finished Jan 17 01:06:38 PM PST 24
Peak memory 200888 kb
Host smart-d8f30d06-805e-4998-977d-7c150b826cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576511812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1576511812
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3053569150
Short name T883
Test name
Test status
Simulation time 851869367 ps
CPU time 4.38 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:29 PM PST 24
Peak memory 200612 kb
Host smart-4f4ae023-92d2-4935-a7b8-9512b21bfbf4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053569150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3053569150
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2934678805
Short name T890
Test name
Test status
Simulation time 12839518383 ps
CPU time 16.33 seconds
Started Jan 17 12:30:35 PM PST 24
Finished Jan 17 12:30:53 PM PST 24
Peak memory 200724 kb
Host smart-13b03be5-e667-4a0e-995a-1e4ca46a5b15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934678805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2934678805
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1617760391
Short name T884
Test name
Test status
Simulation time 1170058159 ps
CPU time 2.06 seconds
Started Jan 17 12:30:10 PM PST 24
Finished Jan 17 12:30:13 PM PST 24
Peak memory 200392 kb
Host smart-d15f576c-29ac-444b-9859-19e189819833
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617760391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1617760391
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1314355541
Short name T355
Test name
Test status
Simulation time 507152933 ps
CPU time 1.94 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200436 kb
Host smart-458b0981-eca8-4e38-85f7-a177cfeddbaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314355541 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1314355541
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.308496105
Short name T905
Test name
Test status
Simulation time 583878126 ps
CPU time 1.12 seconds
Started Jan 17 12:30:08 PM PST 24
Finished Jan 17 12:30:11 PM PST 24
Peak memory 200424 kb
Host smart-d70efd50-3983-457b-b4dd-1b7c6fa8cdcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308496105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.308496105
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3790909768
Short name T6
Test name
Test status
Simulation time 448687528 ps
CPU time 0.69 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:29 PM PST 24
Peak memory 200120 kb
Host smart-f63ee89e-e1a1-47a4-857c-20254965eb2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790909768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3790909768
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.341999669
Short name T171
Test name
Test status
Simulation time 4635007059 ps
CPU time 9.18 seconds
Started Jan 17 12:30:11 PM PST 24
Finished Jan 17 12:30:21 PM PST 24
Peak memory 200652 kb
Host smart-1718e4fe-4517-43dc-b387-c0d20e8293ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341999669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.341999669
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1677441585
Short name T896
Test name
Test status
Simulation time 430918533 ps
CPU time 2.46 seconds
Started Jan 17 12:30:10 PM PST 24
Finished Jan 17 12:30:14 PM PST 24
Peak memory 200668 kb
Host smart-5f7d35fe-6803-4f10-924e-840fd642dd59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677441585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1677441585
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3446820876
Short name T65
Test name
Test status
Simulation time 8252128526 ps
CPU time 7.15 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:34 PM PST 24
Peak memory 200700 kb
Host smart-255c39eb-0cf1-4369-9984-40daf3fdb5be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446820876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3446820876
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.435852828
Short name T398
Test name
Test status
Simulation time 16045421601 ps
CPU time 20.7 seconds
Started Jan 17 12:30:16 PM PST 24
Finished Jan 17 12:30:39 PM PST 24
Peak memory 200712 kb
Host smart-1ceaf80c-1140-4d8c-9709-5914c6f40596
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435852828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.435852828
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3292681954
Short name T393
Test name
Test status
Simulation time 1382109290 ps
CPU time 0.91 seconds
Started Jan 17 12:30:30 PM PST 24
Finished Jan 17 12:30:34 PM PST 24
Peak memory 200404 kb
Host smart-18cb2596-7369-453b-988b-2a788eb4620e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292681954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3292681954
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.83309595
Short name T865
Test name
Test status
Simulation time 373732880 ps
CPU time 1.64 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:28 PM PST 24
Peak memory 200480 kb
Host smart-a3498bc0-5426-4d9e-a121-cb79b260294b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83309595 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.83309595
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.163264332
Short name T897
Test name
Test status
Simulation time 566644509 ps
CPU time 2.05 seconds
Started Jan 17 12:30:30 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200396 kb
Host smart-9f9145f9-e2ca-4a83-bb65-e7e2698dc708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163264332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.163264332
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.168700064
Short name T351
Test name
Test status
Simulation time 301675776 ps
CPU time 1.31 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200128 kb
Host smart-a5d992a3-18ff-4daf-92e9-bff1d5b8a000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168700064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.168700064
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.877207965
Short name T362
Test name
Test status
Simulation time 4370182697 ps
CPU time 3.61 seconds
Started Jan 17 12:30:25 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 200668 kb
Host smart-28f0890b-2893-4102-8f63-4bf822f56eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877207965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.877207965
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3670722400
Short name T69
Test name
Test status
Simulation time 590592576 ps
CPU time 1.35 seconds
Started Jan 17 12:30:19 PM PST 24
Finished Jan 17 12:30:21 PM PST 24
Peak memory 200664 kb
Host smart-1a71a998-3d87-4abe-8ae7-66d672bb8d21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670722400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3670722400
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.614621399
Short name T380
Test name
Test status
Simulation time 4191754097 ps
CPU time 11.52 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:38 PM PST 24
Peak memory 200724 kb
Host smart-dad92640-d577-494d-8781-6e2526dcf3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614621399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.614621399
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3043192246
Short name T346
Test name
Test status
Simulation time 428040348 ps
CPU time 1.83 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:36 PM PST 24
Peak memory 200512 kb
Host smart-e8f9ae61-a6b8-408d-a708-c4942b57c105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043192246 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3043192246
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2470339345
Short name T168
Test name
Test status
Simulation time 424117307 ps
CPU time 1.59 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200372 kb
Host smart-590246b4-63f9-47a8-88e2-a050f0dd1ae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470339345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2470339345
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4043208570
Short name T31
Test name
Test status
Simulation time 356541062 ps
CPU time 1.43 seconds
Started Jan 17 12:30:26 PM PST 24
Finished Jan 17 12:30:31 PM PST 24
Peak memory 200132 kb
Host smart-e2627019-b64e-4cb8-8828-7fa46134965c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043208570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4043208570
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3945996572
Short name T366
Test name
Test status
Simulation time 3982371322 ps
CPU time 15.46 seconds
Started Jan 17 12:30:31 PM PST 24
Finished Jan 17 12:30:49 PM PST 24
Peak memory 200692 kb
Host smart-79e11bf3-22f8-425a-92e4-1a75ef0a1306
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945996572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3945996572
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.346211124
Short name T169
Test name
Test status
Simulation time 2270707011 ps
CPU time 3.28 seconds
Started Jan 17 12:30:30 PM PST 24
Finished Jan 17 12:30:37 PM PST 24
Peak memory 200792 kb
Host smart-3c43726c-be72-480f-b1a9-86b80a8d5976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346211124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.346211124
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1674216818
Short name T354
Test name
Test status
Simulation time 4407363808 ps
CPU time 13.18 seconds
Started Jan 17 12:30:38 PM PST 24
Finished Jan 17 12:30:53 PM PST 24
Peak memory 200596 kb
Host smart-5e8b9f09-d07e-4582-9f96-e0727b7bd63d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674216818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1674216818
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1772852561
Short name T2
Test name
Test status
Simulation time 544200167 ps
CPU time 0.92 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:26 PM PST 24
Peak memory 200500 kb
Host smart-8ada8919-e405-42d6-85d8-8f3e2e58e33c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772852561 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1772852561
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1803758483
Short name T377
Test name
Test status
Simulation time 575355042 ps
CPU time 0.85 seconds
Started Jan 17 12:30:27 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 200460 kb
Host smart-42543879-dc21-49d5-a20d-58121014d119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803758483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1803758483
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.493168831
Short name T76
Test name
Test status
Simulation time 447023234 ps
CPU time 0.89 seconds
Started Jan 17 12:30:21 PM PST 24
Finished Jan 17 12:30:23 PM PST 24
Peak memory 200148 kb
Host smart-05fb14d9-e2e8-45de-991a-5d463a91a042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493168831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.493168831
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2172478711
Short name T372
Test name
Test status
Simulation time 4557665592 ps
CPU time 3.67 seconds
Started Jan 17 12:30:39 PM PST 24
Finished Jan 17 12:30:44 PM PST 24
Peak memory 200656 kb
Host smart-c7efccee-8d5a-425d-891a-36b02a4afc8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172478711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2172478711
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1618589336
Short name T907
Test name
Test status
Simulation time 480989962 ps
CPU time 3.33 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:34 PM PST 24
Peak memory 216972 kb
Host smart-31e6cc51-e350-4bf0-8cfe-c6624b7bdfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618589336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1618589336
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.284805868
Short name T877
Test name
Test status
Simulation time 4595582305 ps
CPU time 4.49 seconds
Started Jan 17 12:30:26 PM PST 24
Finished Jan 17 12:30:34 PM PST 24
Peak memory 200708 kb
Host smart-bde5a192-55fa-4581-baee-df462d08d270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284805868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.284805868
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4271354348
Short name T885
Test name
Test status
Simulation time 485122513 ps
CPU time 1.39 seconds
Started Jan 17 12:30:49 PM PST 24
Finished Jan 17 12:30:53 PM PST 24
Peak memory 200504 kb
Host smart-82d821c9-0a5d-4fe8-98db-02b268b17a86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271354348 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4271354348
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3958595893
Short name T73
Test name
Test status
Simulation time 451665570 ps
CPU time 1.84 seconds
Started Jan 17 12:30:50 PM PST 24
Finished Jan 17 12:30:54 PM PST 24
Peak memory 200420 kb
Host smart-3f75922a-5af3-4450-a543-3c68e84c2c61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958595893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3958595893
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1971570096
Short name T75
Test name
Test status
Simulation time 451168508 ps
CPU time 1.72 seconds
Started Jan 17 12:30:33 PM PST 24
Finished Jan 17 12:30:37 PM PST 24
Peak memory 200468 kb
Host smart-14927859-1cbe-4e03-b9d7-268a23e02e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971570096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1971570096
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.742348781
Short name T396
Test name
Test status
Simulation time 514507268 ps
CPU time 2.55 seconds
Started Jan 17 12:30:35 PM PST 24
Finished Jan 17 12:30:40 PM PST 24
Peak memory 209940 kb
Host smart-11eb8203-0c76-4570-8d41-95ccc32fa659
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742348781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.742348781
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3235750682
Short name T394
Test name
Test status
Simulation time 8889566621 ps
CPU time 11.05 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:39 PM PST 24
Peak memory 200592 kb
Host smart-98f65e8f-fc7a-410e-8b6e-ceca9eaa94ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235750682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3235750682
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2031659209
Short name T399
Test name
Test status
Simulation time 487980651 ps
CPU time 1.36 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:33 PM PST 24
Peak memory 200472 kb
Host smart-3f55fa61-e4cf-40a9-920e-2c6a9e644a7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031659209 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2031659209
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4232514635
Short name T901
Test name
Test status
Simulation time 377066411 ps
CPU time 0.89 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 200404 kb
Host smart-c267d142-16dd-44f7-ae17-94cba565a852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232514635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4232514635
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3052449049
Short name T881
Test name
Test status
Simulation time 307051538 ps
CPU time 0.79 seconds
Started Jan 17 12:30:31 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200324 kb
Host smart-fcb251cd-1215-4418-8398-a4561c91089a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052449049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3052449049
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3595052077
Short name T385
Test name
Test status
Simulation time 2400702627 ps
CPU time 3.82 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200500 kb
Host smart-f8f6dd30-7860-404c-9407-82de8ab82fc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595052077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3595052077
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2276345218
Short name T166
Test name
Test status
Simulation time 470135935 ps
CPU time 3.53 seconds
Started Jan 17 12:30:25 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 217060 kb
Host smart-da45f61b-86d1-4b9d-89ee-d09bd52dff2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276345218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2276345218
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.51198638
Short name T345
Test name
Test status
Simulation time 472739167 ps
CPU time 1.09 seconds
Started Jan 17 12:30:26 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200464 kb
Host smart-39431102-2c42-4047-b403-cfa13da057ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51198638 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.51198638
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2464799033
Short name T9
Test name
Test status
Simulation time 570156106 ps
CPU time 1.03 seconds
Started Jan 17 12:30:29 PM PST 24
Finished Jan 17 12:30:34 PM PST 24
Peak memory 200456 kb
Host smart-80ce65ce-ce5c-4a5d-a7cd-01d22b98fdc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464799033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2464799033
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2422479270
Short name T384
Test name
Test status
Simulation time 377420488 ps
CPU time 0.77 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 200124 kb
Host smart-ea149837-60af-42bd-ac5f-2de6ce69dcaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422479270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2422479270
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.539710954
Short name T8
Test name
Test status
Simulation time 3937309079 ps
CPU time 5.76 seconds
Started Jan 17 12:30:20 PM PST 24
Finished Jan 17 12:30:26 PM PST 24
Peak memory 200640 kb
Host smart-bca4e61c-b501-41a9-86b6-741975036d76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539710954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.539710954
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1767882795
Short name T894
Test name
Test status
Simulation time 600514329 ps
CPU time 1.53 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:33 PM PST 24
Peak memory 200980 kb
Host smart-44a6d11e-e94b-4321-bdda-35ecea662b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767882795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1767882795
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.63650823
Short name T330
Test name
Test status
Simulation time 8918549765 ps
CPU time 8.53 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:39 PM PST 24
Peak memory 200676 kb
Host smart-e846ae97-730c-417c-8d02-20ec7d1e97b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63650823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_int
g_err.63650823
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2320707970
Short name T913
Test name
Test status
Simulation time 600722110 ps
CPU time 1.59 seconds
Started Jan 17 12:30:31 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200508 kb
Host smart-b6b96cba-a049-408a-8859-841e4dd3ae98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320707970 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2320707970
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3372925697
Short name T34
Test name
Test status
Simulation time 418707383 ps
CPU time 1.59 seconds
Started Jan 17 12:30:26 PM PST 24
Finished Jan 17 12:30:31 PM PST 24
Peak memory 200396 kb
Host smart-4b2c30ff-96ae-44b9-a02a-475841920e5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372925697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3372925697
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1831409779
Short name T356
Test name
Test status
Simulation time 417132241 ps
CPU time 1.54 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:28 PM PST 24
Peak memory 200052 kb
Host smart-ea9bcfe9-370b-4a0f-9355-b916122c5d08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831409779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1831409779
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2932310152
Short name T378
Test name
Test status
Simulation time 3510240126 ps
CPU time 5.91 seconds
Started Jan 17 12:30:38 PM PST 24
Finished Jan 17 12:30:46 PM PST 24
Peak memory 200700 kb
Host smart-cc8f8a8b-a7bc-42f0-85a0-617619074570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932310152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2932310152
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.384110322
Short name T878
Test name
Test status
Simulation time 1413591132 ps
CPU time 2.72 seconds
Started Jan 17 12:30:41 PM PST 24
Finished Jan 17 12:30:44 PM PST 24
Peak memory 200716 kb
Host smart-8766077a-b5a2-4b83-81bf-7439e172d5ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384110322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.384110322
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3260227974
Short name T868
Test name
Test status
Simulation time 4707542226 ps
CPU time 2.32 seconds
Started Jan 17 12:30:37 PM PST 24
Finished Jan 17 12:30:46 PM PST 24
Peak memory 200724 kb
Host smart-2f84ab30-f29e-47b2-a559-08eb68c4a8e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260227974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3260227974
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.401977689
Short name T871
Test name
Test status
Simulation time 583549173 ps
CPU time 1.25 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200476 kb
Host smart-317f832c-f596-4ad4-8954-3fb007f68479
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401977689 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.401977689
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1545076362
Short name T382
Test name
Test status
Simulation time 403122046 ps
CPU time 1.66 seconds
Started Jan 17 12:30:26 PM PST 24
Finished Jan 17 12:30:31 PM PST 24
Peak memory 200408 kb
Host smart-d8ad0e59-3afb-45aa-8a8c-7c68ee44d359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545076362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1545076362
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3678260309
Short name T872
Test name
Test status
Simulation time 497268864 ps
CPU time 1.17 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:36 PM PST 24
Peak memory 200372 kb
Host smart-0038ece9-fb1c-4ee0-a33b-4d1e534708b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678260309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3678260309
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.918156628
Short name T381
Test name
Test status
Simulation time 4181326684 ps
CPU time 2.79 seconds
Started Jan 17 12:30:37 PM PST 24
Finished Jan 17 12:30:41 PM PST 24
Peak memory 200756 kb
Host smart-161f7571-2346-42c2-a6c9-12a64aedd994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918156628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.918156628
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2672798861
Short name T28
Test name
Test status
Simulation time 399311737 ps
CPU time 2.59 seconds
Started Jan 17 12:30:21 PM PST 24
Finished Jan 17 12:30:26 PM PST 24
Peak memory 216880 kb
Host smart-e3767e9f-7c01-4427-969f-c6400aaa2916
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672798861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2672798861
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1264758185
Short name T66
Test name
Test status
Simulation time 4947907147 ps
CPU time 12.61 seconds
Started Jan 17 12:30:36 PM PST 24
Finished Jan 17 12:30:50 PM PST 24
Peak memory 200660 kb
Host smart-3ec2f79d-8eba-468d-a6b1-ab5f55637f52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264758185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1264758185
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1235138819
Short name T893
Test name
Test status
Simulation time 520593282 ps
CPU time 1.29 seconds
Started Jan 17 12:30:34 PM PST 24
Finished Jan 17 12:30:38 PM PST 24
Peak memory 200440 kb
Host smart-63d3961a-0eb5-4df6-9bbf-c6250caf3497
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235138819 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1235138819
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3462950198
Short name T914
Test name
Test status
Simulation time 461567753 ps
CPU time 1.3 seconds
Started Jan 17 12:30:41 PM PST 24
Finished Jan 17 12:30:42 PM PST 24
Peak memory 200440 kb
Host smart-5fc82397-65a7-40af-a03d-18626a3dd203
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462950198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3462950198
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2791088836
Short name T874
Test name
Test status
Simulation time 442407465 ps
CPU time 1.16 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:29 PM PST 24
Peak memory 200380 kb
Host smart-8f8ed664-3f05-48ed-be02-36025bd4f209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791088836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2791088836
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1619744191
Short name T379
Test name
Test status
Simulation time 4631831132 ps
CPU time 11.51 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:38 PM PST 24
Peak memory 200692 kb
Host smart-c6d22994-a62f-431e-85a1-567d655ac3ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619744191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1619744191
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2413450226
Short name T64
Test name
Test status
Simulation time 692756329 ps
CPU time 1.85 seconds
Started Jan 17 12:30:34 PM PST 24
Finished Jan 17 12:30:39 PM PST 24
Peak memory 201064 kb
Host smart-bcf42f93-93fb-4b73-bf38-57b2ab402ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413450226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2413450226
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3850062549
Short name T4
Test name
Test status
Simulation time 4486021799 ps
CPU time 11.32 seconds
Started Jan 17 12:30:37 PM PST 24
Finished Jan 17 12:30:50 PM PST 24
Peak memory 200696 kb
Host smart-1daefa39-cdfe-437a-814d-20613e8146fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850062549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3850062549
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1425179165
Short name T350
Test name
Test status
Simulation time 344403464 ps
CPU time 1.53 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:36 PM PST 24
Peak memory 200484 kb
Host smart-39d61c43-761e-458e-b713-f8ce7ee9f47f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425179165 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1425179165
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1550416721
Short name T83
Test name
Test status
Simulation time 472355469 ps
CPU time 1.77 seconds
Started Jan 17 12:30:47 PM PST 24
Finished Jan 17 12:30:50 PM PST 24
Peak memory 200372 kb
Host smart-c2dff779-7268-4505-a03b-7bd91f3574e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550416721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1550416721
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4127728475
Short name T873
Test name
Test status
Simulation time 331512279 ps
CPU time 0.82 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:29 PM PST 24
Peak memory 200320 kb
Host smart-ed253832-4d93-4764-ae35-d0cc3be31f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127728475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4127728475
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2406885175
Short name T30
Test name
Test status
Simulation time 2600202924 ps
CPU time 2.42 seconds
Started Jan 17 12:30:51 PM PST 24
Finished Jan 17 12:30:55 PM PST 24
Peak memory 200860 kb
Host smart-cf53716b-d1b7-4f96-ba0f-91e6542f2b4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406885175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2406885175
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4130589450
Short name T887
Test name
Test status
Simulation time 756460641 ps
CPU time 3.48 seconds
Started Jan 17 12:30:25 PM PST 24
Finished Jan 17 12:30:33 PM PST 24
Peak memory 200756 kb
Host smart-1804d0cb-a6fa-4af1-b679-98f56fc79496
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130589450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4130589450
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1921359668
Short name T867
Test name
Test status
Simulation time 4269060863 ps
CPU time 9.2 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:34 PM PST 24
Peak memory 200620 kb
Host smart-ec7c67a2-63e1-48ce-b86a-904b99f0fa6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921359668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1921359668
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1100598113
Short name T889
Test name
Test status
Simulation time 581935137 ps
CPU time 1.7 seconds
Started Jan 17 12:30:40 PM PST 24
Finished Jan 17 12:30:42 PM PST 24
Peak memory 200484 kb
Host smart-014b483f-9994-4736-a84a-134d67e47af1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100598113 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1100598113
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3159435221
Short name T85
Test name
Test status
Simulation time 572750893 ps
CPU time 2.17 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:36 PM PST 24
Peak memory 200416 kb
Host smart-63a3c277-d360-4ffe-a410-f1d862f12362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159435221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3159435221
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2583776424
Short name T26
Test name
Test status
Simulation time 332465063 ps
CPU time 0.8 seconds
Started Jan 17 12:30:27 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200336 kb
Host smart-59c98e54-8e00-4717-9033-15f919f8f6e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583776424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2583776424
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.157947481
Short name T3
Test name
Test status
Simulation time 1890260642 ps
CPU time 2.36 seconds
Started Jan 17 12:30:29 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200440 kb
Host smart-cec0132f-4e68-48ec-b9d2-18ad16825526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157947481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.157947481
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4139689420
Short name T902
Test name
Test status
Simulation time 550290726 ps
CPU time 2.46 seconds
Started Jan 17 12:30:29 PM PST 24
Finished Jan 17 12:30:39 PM PST 24
Peak memory 200676 kb
Host smart-accf9078-fc74-4aad-86a0-66dbcc9bcdcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139689420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4139689420
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2880387850
Short name T880
Test name
Test status
Simulation time 3805578790 ps
CPU time 9.61 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:38 PM PST 24
Peak memory 200780 kb
Host smart-0a5d92f0-9193-480a-ae31-90ec60d4e2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880387850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2880387850
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3230897114
Short name T79
Test name
Test status
Simulation time 389636512 ps
CPU time 1.51 seconds
Started Jan 17 12:30:37 PM PST 24
Finished Jan 17 12:30:40 PM PST 24
Peak memory 200640 kb
Host smart-58d68d30-9c32-4c94-8de4-fad6ffdf01c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230897114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3230897114
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1083932519
Short name T82
Test name
Test status
Simulation time 18308796544 ps
CPU time 73.21 seconds
Started Jan 17 12:30:42 PM PST 24
Finished Jan 17 12:31:56 PM PST 24
Peak memory 200588 kb
Host smart-d879dfbb-8eaa-48af-953f-1932d4ef6dd0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083932519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1083932519
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2965981036
Short name T74
Test name
Test status
Simulation time 937162841 ps
CPU time 3.21 seconds
Started Jan 17 12:30:06 PM PST 24
Finished Jan 17 12:30:13 PM PST 24
Peak memory 200412 kb
Host smart-609b8b5f-d240-4044-a6ce-3603e7cbfcb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965981036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2965981036
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3175971900
Short name T388
Test name
Test status
Simulation time 384945345 ps
CPU time 1.79 seconds
Started Jan 17 12:30:09 PM PST 24
Finished Jan 17 12:30:12 PM PST 24
Peak memory 200384 kb
Host smart-19e9032f-ea6b-4449-8ec2-c1bdbfc76d28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175971900 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3175971900
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.489795414
Short name T876
Test name
Test status
Simulation time 541003860 ps
CPU time 1.03 seconds
Started Jan 17 12:30:21 PM PST 24
Finished Jan 17 12:30:22 PM PST 24
Peak memory 200416 kb
Host smart-d802e759-bfd4-4286-ba00-4fca47bc54e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489795414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.489795414
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3303216918
Short name T911
Test name
Test status
Simulation time 2637165055 ps
CPU time 13.76 seconds
Started Jan 17 12:30:37 PM PST 24
Finished Jan 17 12:30:53 PM PST 24
Peak memory 200428 kb
Host smart-fda4fbbd-6bc5-4ff2-b899-b50f18222947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303216918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3303216918
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3502734463
Short name T63
Test name
Test status
Simulation time 723225610 ps
CPU time 1.3 seconds
Started Jan 17 12:30:12 PM PST 24
Finished Jan 17 12:30:14 PM PST 24
Peak memory 201036 kb
Host smart-0f70dabe-e939-4584-b950-f69817ecf183
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502734463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3502734463
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2953631686
Short name T328
Test name
Test status
Simulation time 8263763448 ps
CPU time 20.99 seconds
Started Jan 17 12:30:20 PM PST 24
Finished Jan 17 12:30:42 PM PST 24
Peak memory 200720 kb
Host smart-d0c1f708-4d6a-4508-b846-0a2dc3f51f66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953631686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2953631686
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4263044103
Short name T368
Test name
Test status
Simulation time 508913423 ps
CPU time 1.25 seconds
Started Jan 17 12:31:01 PM PST 24
Finished Jan 17 12:31:04 PM PST 24
Peak memory 200112 kb
Host smart-84375007-c7dd-433b-8267-6fcb094a680a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263044103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4263044103
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2940384412
Short name T348
Test name
Test status
Simulation time 483084131 ps
CPU time 1.19 seconds
Started Jan 17 12:30:21 PM PST 24
Finished Jan 17 12:30:24 PM PST 24
Peak memory 200352 kb
Host smart-d783dedb-48d7-4bd9-bc68-28e4872b19dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940384412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2940384412
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3927060412
Short name T375
Test name
Test status
Simulation time 405779288 ps
CPU time 0.86 seconds
Started Jan 17 12:30:36 PM PST 24
Finished Jan 17 12:30:38 PM PST 24
Peak memory 200384 kb
Host smart-bbbb52b0-7045-4324-b531-5a79714942ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927060412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3927060412
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.4014412897
Short name T395
Test name
Test status
Simulation time 279920199 ps
CPU time 1.3 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:36 PM PST 24
Peak memory 200336 kb
Host smart-3e518588-ece2-4d36-a913-0cb4e5926e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014412897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.4014412897
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.629071084
Short name T363
Test name
Test status
Simulation time 387910445 ps
CPU time 1.02 seconds
Started Jan 17 12:30:41 PM PST 24
Finished Jan 17 12:30:43 PM PST 24
Peak memory 200068 kb
Host smart-6852a08d-8ec7-4301-a54d-28caf6082a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629071084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.629071084
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1278223700
Short name T389
Test name
Test status
Simulation time 540578247 ps
CPU time 0.71 seconds
Started Jan 17 12:30:27 PM PST 24
Finished Jan 17 12:30:31 PM PST 24
Peak memory 200360 kb
Host smart-54a613ef-93a0-456a-af80-7916028ea3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278223700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1278223700
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2744700351
Short name T898
Test name
Test status
Simulation time 344012014 ps
CPU time 1.03 seconds
Started Jan 17 12:30:50 PM PST 24
Finished Jan 17 12:30:53 PM PST 24
Peak memory 200076 kb
Host smart-fcf22084-3f55-48f4-ac0b-2547d9f70994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744700351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2744700351
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.718173940
Short name T904
Test name
Test status
Simulation time 524022559 ps
CPU time 1.71 seconds
Started Jan 17 12:30:56 PM PST 24
Finished Jan 17 12:30:59 PM PST 24
Peak memory 200208 kb
Host smart-bdd23080-4c78-476a-b8ac-71ff95881983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718173940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.718173940
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4238764778
Short name T357
Test name
Test status
Simulation time 440914868 ps
CPU time 1.66 seconds
Started Jan 17 12:30:25 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200336 kb
Host smart-9f70bbc7-a1d6-4188-a236-109ba0379e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238764778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.4238764778
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2942121952
Short name T387
Test name
Test status
Simulation time 485373689 ps
CPU time 0.89 seconds
Started Jan 17 12:30:58 PM PST 24
Finished Jan 17 12:31:00 PM PST 24
Peak memory 200136 kb
Host smart-11cb199f-3e82-4614-87f6-e123b97461c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942121952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2942121952
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3839939529
Short name T33
Test name
Test status
Simulation time 811086360 ps
CPU time 3.17 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 200580 kb
Host smart-2ba11618-830f-4e23-94d3-57ef4a30866d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839939529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3839939529
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1023174388
Short name T80
Test name
Test status
Simulation time 21404767368 ps
CPU time 12.58 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:39 PM PST 24
Peak memory 200652 kb
Host smart-d9fc0aa1-7cfd-480f-b126-6f6eac2cea59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023174388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1023174388
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1684616708
Short name T72
Test name
Test status
Simulation time 707889281 ps
CPU time 1.06 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200340 kb
Host smart-138c4995-8a62-4b9d-b768-b42e5a2efd7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684616708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1684616708
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2650666489
Short name T891
Test name
Test status
Simulation time 425615500 ps
CPU time 1.24 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:36 PM PST 24
Peak memory 200416 kb
Host smart-e0c176bc-37eb-4a8d-b668-94471a45dd86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650666489 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2650666489
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1870057765
Short name T78
Test name
Test status
Simulation time 461711113 ps
CPU time 1.07 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:29 PM PST 24
Peak memory 200432 kb
Host smart-4a20f0be-0da6-49be-a31c-1832bf02b9f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870057765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1870057765
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2851427654
Short name T370
Test name
Test status
Simulation time 493899831 ps
CPU time 0.93 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200096 kb
Host smart-be99ef50-1e2a-40d8-ba69-1b7cfcba9f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851427654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2851427654
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2582297979
Short name T84
Test name
Test status
Simulation time 4222111175 ps
CPU time 10.24 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:45 PM PST 24
Peak memory 200608 kb
Host smart-e85d5c2d-034c-4c7f-977e-0c186472c78a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582297979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2582297979
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2373814431
Short name T10
Test name
Test status
Simulation time 4316569234 ps
CPU time 6.42 seconds
Started Jan 17 12:30:37 PM PST 24
Finished Jan 17 12:30:45 PM PST 24
Peak memory 200712 kb
Host smart-c31195ad-7dde-4d99-9a43-1a99437a4140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373814431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2373814431
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3107942376
Short name T391
Test name
Test status
Simulation time 383606263 ps
CPU time 0.86 seconds
Started Jan 17 12:30:27 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 200144 kb
Host smart-ebc4a976-f459-40d3-9666-cf15cfc0576b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107942376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3107942376
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.67804822
Short name T910
Test name
Test status
Simulation time 483479710 ps
CPU time 1.13 seconds
Started Jan 17 12:30:30 PM PST 24
Finished Jan 17 12:30:39 PM PST 24
Peak memory 200308 kb
Host smart-1758e47a-e99d-41b2-a8ec-8fb385147d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67804822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.67804822
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2070957592
Short name T908
Test name
Test status
Simulation time 462300674 ps
CPU time 1.65 seconds
Started Jan 17 12:30:31 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200348 kb
Host smart-c491e259-2e22-4bdc-a36a-a05326509595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070957592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2070957592
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2958181957
Short name T882
Test name
Test status
Simulation time 388190853 ps
CPU time 1.59 seconds
Started Jan 17 12:30:30 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200128 kb
Host smart-f637a2c3-0d55-4736-b6ab-c932058f3c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958181957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2958181957
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2514523551
Short name T869
Test name
Test status
Simulation time 361713793 ps
CPU time 1.44 seconds
Started Jan 17 12:30:52 PM PST 24
Finished Jan 17 12:30:55 PM PST 24
Peak memory 200124 kb
Host smart-7999d88c-76fd-4e3f-bc4a-9623cfba09e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514523551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2514523551
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.979241033
Short name T888
Test name
Test status
Simulation time 524474714 ps
CPU time 1.94 seconds
Started Jan 17 12:30:38 PM PST 24
Finished Jan 17 12:30:42 PM PST 24
Peak memory 200120 kb
Host smart-b1aca062-383a-47f7-a10f-d785b9458598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979241033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.979241033
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3063531177
Short name T886
Test name
Test status
Simulation time 627393992 ps
CPU time 0.8 seconds
Started Jan 17 12:30:54 PM PST 24
Finished Jan 17 12:30:56 PM PST 24
Peak memory 200200 kb
Host smart-029151ff-38b1-4828-acf4-d7f9ab5d2a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063531177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3063531177
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1894526815
Short name T353
Test name
Test status
Simulation time 412655065 ps
CPU time 1.51 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200140 kb
Host smart-fc75610d-812c-4c78-b773-380710e9fd90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894526815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1894526815
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3381806897
Short name T900
Test name
Test status
Simulation time 465407058 ps
CPU time 0.89 seconds
Started Jan 17 12:30:54 PM PST 24
Finished Jan 17 12:30:57 PM PST 24
Peak memory 200176 kb
Host smart-d07cd108-7211-4881-bbdb-158f5551190e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381806897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3381806897
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3407968900
Short name T81
Test name
Test status
Simulation time 742253305 ps
CPU time 1.89 seconds
Started Jan 17 12:30:31 PM PST 24
Finished Jan 17 12:30:36 PM PST 24
Peak memory 200612 kb
Host smart-c749f7e1-82ca-4c57-a15e-9be77b7a54ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407968900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3407968900
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1674640344
Short name T879
Test name
Test status
Simulation time 1607906784 ps
CPU time 9.37 seconds
Started Jan 17 12:30:33 PM PST 24
Finished Jan 17 12:30:44 PM PST 24
Peak memory 200660 kb
Host smart-6663bde2-6185-4997-b9ff-7a2d8be9df1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674640344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1674640344
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2001970334
Short name T71
Test name
Test status
Simulation time 1402019704 ps
CPU time 4.21 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200448 kb
Host smart-94352345-b479-4968-a546-caa30e295d64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001970334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2001970334
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2418427756
Short name T165
Test name
Test status
Simulation time 493745184 ps
CPU time 1.33 seconds
Started Jan 17 12:30:24 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200504 kb
Host smart-c28893e6-309e-467c-9b3d-28d2605bbfe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418427756 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2418427756
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1763677096
Short name T167
Test name
Test status
Simulation time 453160572 ps
CPU time 1.18 seconds
Started Jan 17 12:30:19 PM PST 24
Finished Jan 17 12:30:21 PM PST 24
Peak memory 200412 kb
Host smart-868b9e69-1737-4a3e-a836-04eec349e403
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763677096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1763677096
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2976200219
Short name T364
Test name
Test status
Simulation time 489624367 ps
CPU time 0.89 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:28 PM PST 24
Peak memory 200156 kb
Host smart-c215da5a-98cf-4afd-a919-b0bb17dc337b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976200219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2976200219
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2898366195
Short name T373
Test name
Test status
Simulation time 2158537229 ps
CPU time 4.74 seconds
Started Jan 17 12:30:19 PM PST 24
Finished Jan 17 12:30:25 PM PST 24
Peak memory 200492 kb
Host smart-4fe103e2-a733-4a29-b242-d8fb003f76d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898366195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2898366195
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3889799656
Short name T67
Test name
Test status
Simulation time 533171454 ps
CPU time 1.33 seconds
Started Jan 17 12:30:27 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 200468 kb
Host smart-7fbb1513-fa22-4c14-92f1-dabce13b774b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889799656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3889799656
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1370017142
Short name T371
Test name
Test status
Simulation time 5182397120 ps
CPU time 3.09 seconds
Started Jan 17 12:30:37 PM PST 24
Finished Jan 17 12:30:42 PM PST 24
Peak memory 200560 kb
Host smart-1d4b6d61-6e9b-4f0d-a253-1889a2dffa3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370017142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1370017142
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1064939064
Short name T383
Test name
Test status
Simulation time 458826266 ps
CPU time 1.14 seconds
Started Jan 17 12:30:51 PM PST 24
Finished Jan 17 12:30:54 PM PST 24
Peak memory 200084 kb
Host smart-b815f6d6-ccb3-422d-98fa-b4238bf0b360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064939064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1064939064
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.470319554
Short name T173
Test name
Test status
Simulation time 478738976 ps
CPU time 1.15 seconds
Started Jan 17 12:30:51 PM PST 24
Finished Jan 17 12:30:54 PM PST 24
Peak memory 200092 kb
Host smart-a45aa9c3-96de-4447-bfbc-8e2f5016b98f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470319554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.470319554
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1615319779
Short name T365
Test name
Test status
Simulation time 401085387 ps
CPU time 0.85 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200288 kb
Host smart-5cdf1646-59a4-4a72-89e7-3a0ab05e8f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615319779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1615319779
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2515911183
Short name T344
Test name
Test status
Simulation time 430933942 ps
CPU time 0.88 seconds
Started Jan 17 12:30:37 PM PST 24
Finished Jan 17 12:30:39 PM PST 24
Peak memory 200092 kb
Host smart-45faa800-12dc-4dd4-ae7c-ca095cdf433a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515911183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2515911183
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2848580424
Short name T866
Test name
Test status
Simulation time 323245532 ps
CPU time 0.98 seconds
Started Jan 17 12:30:27 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 200152 kb
Host smart-966711ac-15dd-4697-8b96-70f04b31a69d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848580424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2848580424
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3375801903
Short name T352
Test name
Test status
Simulation time 530934890 ps
CPU time 1.86 seconds
Started Jan 17 12:30:49 PM PST 24
Finished Jan 17 12:30:54 PM PST 24
Peak memory 200316 kb
Host smart-86e95c42-699b-42fc-baab-05d374f305f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375801903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3375801903
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.948939225
Short name T895
Test name
Test status
Simulation time 310667029 ps
CPU time 1.34 seconds
Started Jan 17 12:30:34 PM PST 24
Finished Jan 17 12:30:38 PM PST 24
Peak memory 200100 kb
Host smart-f3481bd3-b09a-4d08-8fbb-bfac2dfd9ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948939225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.948939225
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1604880848
Short name T361
Test name
Test status
Simulation time 484411755 ps
CPU time 0.91 seconds
Started Jan 17 12:30:27 PM PST 24
Finished Jan 17 12:30:31 PM PST 24
Peak memory 200344 kb
Host smart-cc3794b2-0767-4808-82c5-7b5801c80691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604880848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1604880848
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2190722604
Short name T390
Test name
Test status
Simulation time 396608562 ps
CPU time 0.88 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:36 PM PST 24
Peak memory 200136 kb
Host smart-bda0f05c-aa1e-4324-96b5-f87e8ee43208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190722604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2190722604
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2852837948
Short name T909
Test name
Test status
Simulation time 326906810 ps
CPU time 0.81 seconds
Started Jan 17 12:30:30 PM PST 24
Finished Jan 17 12:30:34 PM PST 24
Peak memory 200340 kb
Host smart-001a3ddf-71ee-4db7-ab1a-56fda0af5ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852837948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2852837948
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.614632935
Short name T32
Test name
Test status
Simulation time 354418058 ps
CPU time 0.96 seconds
Started Jan 17 12:30:25 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 200496 kb
Host smart-281206a8-5203-4bc6-b71a-51a1234041bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614632935 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.614632935
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3135695126
Short name T77
Test name
Test status
Simulation time 415881258 ps
CPU time 1.11 seconds
Started Jan 17 12:30:32 PM PST 24
Finished Jan 17 12:30:36 PM PST 24
Peak memory 200376 kb
Host smart-9bf2dec5-3828-4fe2-bc85-8282e0df2349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135695126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3135695126
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2125618149
Short name T349
Test name
Test status
Simulation time 385888723 ps
CPU time 1.43 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:28 PM PST 24
Peak memory 200116 kb
Host smart-bda5806c-9dee-4c59-869c-b34956a282bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125618149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2125618149
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2106358340
Short name T906
Test name
Test status
Simulation time 4498558138 ps
CPU time 6.08 seconds
Started Jan 17 12:30:47 PM PST 24
Finished Jan 17 12:30:54 PM PST 24
Peak memory 200652 kb
Host smart-6892849d-c487-4682-890b-8b999bdbbefe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106358340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2106358340
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3947393492
Short name T25
Test name
Test status
Simulation time 566310599 ps
CPU time 2.99 seconds
Started Jan 17 12:30:23 PM PST 24
Finished Jan 17 12:30:30 PM PST 24
Peak memory 208956 kb
Host smart-d53eb9c0-467b-4de3-9593-a0a48aa57d32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947393492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3947393492
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3733328653
Short name T870
Test name
Test status
Simulation time 4260459137 ps
CPU time 4.18 seconds
Started Jan 17 12:30:13 PM PST 24
Finished Jan 17 12:30:19 PM PST 24
Peak memory 200680 kb
Host smart-e1085109-dc07-4e39-923b-1717b4b0cbae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733328653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3733328653
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2655370086
Short name T899
Test name
Test status
Simulation time 410695894 ps
CPU time 1.7 seconds
Started Jan 17 12:30:20 PM PST 24
Finished Jan 17 12:30:22 PM PST 24
Peak memory 200396 kb
Host smart-e54d493c-3188-4a13-9fa8-69d8cca68b28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655370086 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2655370086
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4266426392
Short name T358
Test name
Test status
Simulation time 409899833 ps
CPU time 1.46 seconds
Started Jan 17 12:30:39 PM PST 24
Finished Jan 17 12:30:41 PM PST 24
Peak memory 200400 kb
Host smart-d8b72852-63ad-4d5f-9569-1820e3926168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266426392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.4266426392
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3511231788
Short name T912
Test name
Test status
Simulation time 284067402 ps
CPU time 1.23 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:28 PM PST 24
Peak memory 200060 kb
Host smart-75ef84a1-e431-47b1-af0a-c41320d1a22c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511231788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3511231788
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1230340842
Short name T864
Test name
Test status
Simulation time 2370308793 ps
CPU time 6.29 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:31 PM PST 24
Peak memory 200436 kb
Host smart-c555bde9-f32a-4f93-bb52-9538d92d6ee4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230340842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1230340842
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1173961885
Short name T68
Test name
Test status
Simulation time 653424380 ps
CPU time 1.65 seconds
Started Jan 17 12:30:26 PM PST 24
Finished Jan 17 12:30:31 PM PST 24
Peak memory 200728 kb
Host smart-f9dcd187-ac02-4119-87f0-c0548c928076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173961885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1173961885
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.427693293
Short name T331
Test name
Test status
Simulation time 9348303425 ps
CPU time 17.5 seconds
Started Jan 17 12:30:47 PM PST 24
Finished Jan 17 12:31:06 PM PST 24
Peak memory 200572 kb
Host smart-5db2bca1-0ac1-487c-b844-3dedd76683ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427693293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.427693293
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4098374144
Short name T367
Test name
Test status
Simulation time 367548862 ps
CPU time 1.21 seconds
Started Jan 17 12:30:49 PM PST 24
Finished Jan 17 12:30:51 PM PST 24
Peak memory 200460 kb
Host smart-736197ad-bd12-40a5-9cc2-e643902112c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098374144 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4098374144
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2924594471
Short name T397
Test name
Test status
Simulation time 480527050 ps
CPU time 1.76 seconds
Started Jan 17 12:30:35 PM PST 24
Finished Jan 17 12:30:39 PM PST 24
Peak memory 200368 kb
Host smart-af1ca8e0-258e-4cde-8c52-f7a2e448721e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924594471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2924594471
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.444109154
Short name T360
Test name
Test status
Simulation time 489643954 ps
CPU time 1.65 seconds
Started Jan 17 12:30:30 PM PST 24
Finished Jan 17 12:30:35 PM PST 24
Peak memory 200148 kb
Host smart-e1aa0fab-f402-491e-b65f-1ddd22f30a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444109154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.444109154
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1861524184
Short name T392
Test name
Test status
Simulation time 2124493655 ps
CPU time 5.59 seconds
Started Jan 17 12:30:21 PM PST 24
Finished Jan 17 12:30:27 PM PST 24
Peak memory 200428 kb
Host smart-900c6d7c-b8e5-4c29-96d8-86645376a7a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861524184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1861524184
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4218696868
Short name T359
Test name
Test status
Simulation time 670822348 ps
CPU time 2.3 seconds
Started Jan 17 12:30:13 PM PST 24
Finished Jan 17 12:30:17 PM PST 24
Peak memory 200636 kb
Host smart-328c6eaf-c5b0-4f54-ab1e-d7fe79023014
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218696868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4218696868
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.518642632
Short name T70
Test name
Test status
Simulation time 8367006056 ps
CPU time 7.06 seconds
Started Jan 17 12:30:37 PM PST 24
Finished Jan 17 12:30:46 PM PST 24
Peak memory 200612 kb
Host smart-ac23fb50-1fb9-4e87-908c-164b6bb14b14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518642632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.518642632
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2098079595
Short name T347
Test name
Test status
Simulation time 483931823 ps
CPU time 1.85 seconds
Started Jan 17 12:30:20 PM PST 24
Finished Jan 17 12:30:23 PM PST 24
Peak memory 200500 kb
Host smart-c9b591ca-9c86-487f-8bfd-0cf96f6c8394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098079595 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2098079595
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1429839512
Short name T875
Test name
Test status
Simulation time 383635277 ps
CPU time 1.55 seconds
Started Jan 17 12:30:40 PM PST 24
Finished Jan 17 12:30:42 PM PST 24
Peak memory 200372 kb
Host smart-e9e3b118-75ed-4808-9e3c-cb41f248699f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429839512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1429839512
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.18361996
Short name T369
Test name
Test status
Simulation time 398069628 ps
CPU time 1.55 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:33 PM PST 24
Peak memory 200144 kb
Host smart-b3e611d2-6567-4b38-9e77-62c363982981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18361996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.18361996
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.189765569
Short name T892
Test name
Test status
Simulation time 2466494678 ps
CPU time 6.33 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:37 PM PST 24
Peak memory 200524 kb
Host smart-17e733c1-8f8b-455e-91fc-1bfdecdf400e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189765569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.189765569
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3691181318
Short name T170
Test name
Test status
Simulation time 888612817 ps
CPU time 2.68 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:34 PM PST 24
Peak memory 208848 kb
Host smart-9d08b8fd-40cd-44a2-9675-9c6a2d6c7921
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691181318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3691181318
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3317729420
Short name T376
Test name
Test status
Simulation time 508902734 ps
CPU time 1.36 seconds
Started Jan 17 12:30:22 PM PST 24
Finished Jan 17 12:30:28 PM PST 24
Peak memory 200512 kb
Host smart-9aac33a9-33c7-4fb7-b2a7-21124844b113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317729420 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3317729420
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4000967881
Short name T11
Test name
Test status
Simulation time 342552406 ps
CPU time 1.15 seconds
Started Jan 17 12:30:28 PM PST 24
Finished Jan 17 12:30:32 PM PST 24
Peak memory 200444 kb
Host smart-184d59f0-b453-475d-8913-56ff20cc6c0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000967881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4000967881
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1777535669
Short name T386
Test name
Test status
Simulation time 380531350 ps
CPU time 1.52 seconds
Started Jan 17 12:30:21 PM PST 24
Finished Jan 17 12:30:24 PM PST 24
Peak memory 200128 kb
Host smart-e5350817-fe7f-4688-a937-5ea8f6589699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777535669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1777535669
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3934871361
Short name T903
Test name
Test status
Simulation time 4154425603 ps
CPU time 2 seconds
Started Jan 17 12:30:40 PM PST 24
Finished Jan 17 12:30:43 PM PST 24
Peak memory 200640 kb
Host smart-0529f10a-ff28-4ecd-adf2-4b36a741a6e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934871361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3934871361
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.182413234
Short name T374
Test name
Test status
Simulation time 4701872727 ps
CPU time 3.02 seconds
Started Jan 17 12:30:30 PM PST 24
Finished Jan 17 12:30:37 PM PST 24
Peak memory 200708 kb
Host smart-25ea938b-a1b8-4aea-83c8-0d231a02cfbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182413234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.182413234
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2927791614
Short name T481
Test name
Test status
Simulation time 555948537 ps
CPU time 0.85 seconds
Started Jan 17 01:02:48 PM PST 24
Finished Jan 17 01:02:50 PM PST 24
Peak memory 200656 kb
Host smart-aacb4542-a053-47e2-8c56-ef2c1ee33bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927791614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2927791614
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3767716531
Short name T542
Test name
Test status
Simulation time 329615258204 ps
CPU time 767.53 seconds
Started Jan 17 01:02:55 PM PST 24
Finished Jan 17 01:15:43 PM PST 24
Peak memory 201076 kb
Host smart-583a31e3-4ba7-453c-903e-538f11929f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767716531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3767716531
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1775822625
Short name T461
Test name
Test status
Simulation time 321803218905 ps
CPU time 755.4 seconds
Started Jan 17 01:02:57 PM PST 24
Finished Jan 17 01:15:35 PM PST 24
Peak memory 200932 kb
Host smart-c9b320ff-8941-4b2c-a57a-bda016486f6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775822625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1775822625
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3109362745
Short name T702
Test name
Test status
Simulation time 328292060575 ps
CPU time 158.16 seconds
Started Jan 17 01:02:58 PM PST 24
Finished Jan 17 01:05:38 PM PST 24
Peak memory 200892 kb
Host smart-f6172189-da54-4515-8bef-f3127ef856f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109362745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3109362745
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3855113447
Short name T779
Test name
Test status
Simulation time 166861859802 ps
CPU time 358.61 seconds
Started Jan 17 01:02:47 PM PST 24
Finished Jan 17 01:08:46 PM PST 24
Peak memory 200796 kb
Host smart-91d1e3b9-fdf6-40be-99d5-777e2326bf1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855113447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3855113447
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1529564383
Short name T321
Test name
Test status
Simulation time 499389588708 ps
CPU time 558.31 seconds
Started Jan 17 01:02:47 PM PST 24
Finished Jan 17 01:12:07 PM PST 24
Peak memory 200876 kb
Host smart-692942a4-9df0-40aa-83e8-c5a7f3dc509f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529564383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1529564383
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3995767880
Short name T535
Test name
Test status
Simulation time 168191313633 ps
CPU time 45.43 seconds
Started Jan 17 01:02:57 PM PST 24
Finished Jan 17 01:03:43 PM PST 24
Peak memory 200868 kb
Host smart-3142f2a0-97a4-4642-a526-3c4eb272931d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995767880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3995767880
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2471728585
Short name T563
Test name
Test status
Simulation time 42639005562 ps
CPU time 51.31 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:03:42 PM PST 24
Peak memory 200672 kb
Host smart-ec938e26-21d4-4831-8a85-e77d5ba40bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471728585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2471728585
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.462507638
Short name T431
Test name
Test status
Simulation time 3576856785 ps
CPU time 2.84 seconds
Started Jan 17 01:02:48 PM PST 24
Finished Jan 17 01:02:52 PM PST 24
Peak memory 200740 kb
Host smart-33c46e50-b496-40eb-b245-8a8a6e2db007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462507638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.462507638
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3900087779
Short name T415
Test name
Test status
Simulation time 5743207727 ps
CPU time 14.34 seconds
Started Jan 17 01:02:50 PM PST 24
Finished Jan 17 01:03:05 PM PST 24
Peak memory 200720 kb
Host smart-7b822f57-9670-4625-aeaa-2a11873e436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900087779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3900087779
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3760346767
Short name T43
Test name
Test status
Simulation time 117292402157 ps
CPU time 72.5 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:04:02 PM PST 24
Peak memory 200932 kb
Host smart-1291eae2-f861-4bd2-bae0-54d0621f9b09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760346767 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3760346767
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1298509517
Short name T748
Test name
Test status
Simulation time 495951039 ps
CPU time 0.95 seconds
Started Jan 17 01:02:53 PM PST 24
Finished Jan 17 01:02:54 PM PST 24
Peak memory 200656 kb
Host smart-3bc3cde8-bdb7-4d26-8d6b-40d365acf589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298509517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1298509517
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1934239457
Short name T247
Test name
Test status
Simulation time 497841668988 ps
CPU time 270.5 seconds
Started Jan 17 01:02:50 PM PST 24
Finished Jan 17 01:07:21 PM PST 24
Peak memory 200952 kb
Host smart-49334e76-7b9e-4bfd-880b-b301949f389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934239457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1934239457
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2136658454
Short name T861
Test name
Test status
Simulation time 163004217746 ps
CPU time 98.37 seconds
Started Jan 17 01:02:43 PM PST 24
Finished Jan 17 01:04:26 PM PST 24
Peak memory 200808 kb
Host smart-dd6b3e2b-115d-4706-bd32-9c982c65c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136658454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2136658454
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2354375881
Short name T502
Test name
Test status
Simulation time 490045724502 ps
CPU time 72.87 seconds
Started Jan 17 01:02:47 PM PST 24
Finished Jan 17 01:04:01 PM PST 24
Peak memory 200864 kb
Host smart-9e2d12e1-a178-44e2-9bb0-87b3cd6295be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354375881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2354375881
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2192885000
Short name T640
Test name
Test status
Simulation time 162987341815 ps
CPU time 89.52 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:04:20 PM PST 24
Peak memory 200936 kb
Host smart-90acd161-a337-412a-80e5-af67018cd813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192885000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2192885000
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3497592466
Short name T744
Test name
Test status
Simulation time 339490197934 ps
CPU time 207.38 seconds
Started Jan 17 01:02:58 PM PST 24
Finished Jan 17 01:06:26 PM PST 24
Peak memory 200868 kb
Host smart-afe5e12b-f0ee-4bc3-947a-e52f7b33ee0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497592466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3497592466
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1001657026
Short name T684
Test name
Test status
Simulation time 164742092949 ps
CPU time 98.1 seconds
Started Jan 17 01:02:50 PM PST 24
Finished Jan 17 01:04:29 PM PST 24
Peak memory 200856 kb
Host smart-1faca035-8524-40a1-ba11-fc8bcd5ba85f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001657026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1001657026
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2700296170
Short name T644
Test name
Test status
Simulation time 139341125361 ps
CPU time 545.02 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:12:08 PM PST 24
Peak memory 201244 kb
Host smart-bc67bd65-1f50-4369-907f-7e39534d3b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700296170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2700296170
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.491589421
Short name T487
Test name
Test status
Simulation time 27586704751 ps
CPU time 64.37 seconds
Started Jan 17 01:02:56 PM PST 24
Finished Jan 17 01:04:01 PM PST 24
Peak memory 200684 kb
Host smart-2eb62179-03c9-4a6b-a098-11b10dce52ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491589421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.491589421
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2238926414
Short name T432
Test name
Test status
Simulation time 3763967808 ps
CPU time 2.97 seconds
Started Jan 17 01:02:50 PM PST 24
Finished Jan 17 01:02:54 PM PST 24
Peak memory 200712 kb
Host smart-8ac8bc57-f10c-4b62-a971-a8aa4e28839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238926414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2238926414
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3582365509
Short name T52
Test name
Test status
Simulation time 4160993490 ps
CPU time 2.72 seconds
Started Jan 17 01:02:55 PM PST 24
Finished Jan 17 01:02:59 PM PST 24
Peak memory 216048 kb
Host smart-21137b2b-a366-4fba-982e-aa684758890f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582365509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3582365509
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1347145895
Short name T503
Test name
Test status
Simulation time 5757475485 ps
CPU time 4.39 seconds
Started Jan 17 01:02:56 PM PST 24
Finished Jan 17 01:03:01 PM PST 24
Peak memory 200724 kb
Host smart-778db8cd-710a-41ac-85f2-9c7cdbd4d57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347145895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1347145895
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2522260851
Short name T825
Test name
Test status
Simulation time 504004554660 ps
CPU time 119.61 seconds
Started Jan 17 01:02:54 PM PST 24
Finished Jan 17 01:04:54 PM PST 24
Peak memory 200892 kb
Host smart-8c3598b4-099f-4e4b-9eb3-a1125c1cbb8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522260851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2522260851
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.163053043
Short name T326
Test name
Test status
Simulation time 497461669867 ps
CPU time 1180.9 seconds
Started Jan 17 01:03:19 PM PST 24
Finished Jan 17 01:23:02 PM PST 24
Peak memory 200872 kb
Host smart-6b4a67da-5e49-4122-93f0-1b51da0e5e82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163053043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.163053043
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3565522648
Short name T812
Test name
Test status
Simulation time 325011192556 ps
CPU time 370.91 seconds
Started Jan 17 01:03:17 PM PST 24
Finished Jan 17 01:09:32 PM PST 24
Peak memory 200908 kb
Host smart-dc879ed7-10d6-454e-865c-63c244278759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565522648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3565522648
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2040795905
Short name T483
Test name
Test status
Simulation time 495131677656 ps
CPU time 216.16 seconds
Started Jan 17 01:03:17 PM PST 24
Finished Jan 17 01:06:57 PM PST 24
Peak memory 200848 kb
Host smart-5065d244-edd5-4ab6-8a71-8283a61a2722
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040795905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2040795905
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3144508913
Short name T606
Test name
Test status
Simulation time 325020528556 ps
CPU time 153.71 seconds
Started Jan 17 01:03:19 PM PST 24
Finished Jan 17 01:05:55 PM PST 24
Peak memory 200956 kb
Host smart-552705d9-20ef-4c9b-b6f5-02946db0e68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144508913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3144508913
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.151687471
Short name T402
Test name
Test status
Simulation time 163751710260 ps
CPU time 186.57 seconds
Started Jan 17 01:03:25 PM PST 24
Finished Jan 17 01:06:33 PM PST 24
Peak memory 200832 kb
Host smart-2816cc7d-5d09-4b46-a12e-36c683bd9f6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=151687471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.151687471
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.371255967
Short name T750
Test name
Test status
Simulation time 506548130063 ps
CPU time 329.32 seconds
Started Jan 17 01:03:18 PM PST 24
Finished Jan 17 01:08:50 PM PST 24
Peak memory 201164 kb
Host smart-233fac5b-d021-4d77-b06e-2835eb4b5607
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371255967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.371255967
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1963874305
Short name T790
Test name
Test status
Simulation time 335604128188 ps
CPU time 210.99 seconds
Started Jan 17 01:03:18 PM PST 24
Finished Jan 17 01:06:52 PM PST 24
Peak memory 200820 kb
Host smart-aa81cdff-e67a-465e-a9fd-4cca283c9877
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963874305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1963874305
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.4165869140
Short name T333
Test name
Test status
Simulation time 66333424612 ps
CPU time 219.62 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:07:01 PM PST 24
Peak memory 201428 kb
Host smart-4c7fbaca-011f-437f-a7bf-4c066502ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165869140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.4165869140
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2787223935
Short name T570
Test name
Test status
Simulation time 47015778535 ps
CPU time 60.77 seconds
Started Jan 17 01:03:24 PM PST 24
Finished Jan 17 01:04:26 PM PST 24
Peak memory 200712 kb
Host smart-0146fec7-9ad4-4c3b-a997-d567fdf0a039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787223935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2787223935
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.240424300
Short name T413
Test name
Test status
Simulation time 5412167319 ps
CPU time 2.1 seconds
Started Jan 17 01:03:25 PM PST 24
Finished Jan 17 01:03:27 PM PST 24
Peak memory 200732 kb
Host smart-30877ed5-6524-4adb-be58-1a51030c2605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240424300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.240424300
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2792869104
Short name T582
Test name
Test status
Simulation time 5969801913 ps
CPU time 13.83 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:03:35 PM PST 24
Peak memory 200684 kb
Host smart-c3c9e609-5d33-40ba-90c5-0dab45a0d8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792869104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2792869104
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.125108960
Short name T35
Test name
Test status
Simulation time 172339676028 ps
CPU time 259.25 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:07:40 PM PST 24
Peak memory 200864 kb
Host smart-d89aac21-3733-40c1-b8f5-a89f6a11c12a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125108960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
125108960
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3781788771
Short name T752
Test name
Test status
Simulation time 203988318569 ps
CPU time 197.31 seconds
Started Jan 17 01:03:17 PM PST 24
Finished Jan 17 01:06:38 PM PST 24
Peak memory 201436 kb
Host smart-bb8d6593-b2f9-48d3-ade7-cfeae890f11e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781788771 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3781788771
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.596394556
Short name T463
Test name
Test status
Simulation time 315011974 ps
CPU time 0.78 seconds
Started Jan 17 01:03:19 PM PST 24
Finished Jan 17 01:03:22 PM PST 24
Peak memory 200592 kb
Host smart-311bd32b-8c14-4f51-970e-541e46feaef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596394556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.596394556
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1030425894
Short name T139
Test name
Test status
Simulation time 329085890057 ps
CPU time 157.95 seconds
Started Jan 17 01:03:17 PM PST 24
Finished Jan 17 01:05:59 PM PST 24
Peak memory 200880 kb
Host smart-9d48b6ca-28ce-4dde-a8ff-a8f8ac7186e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030425894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1030425894
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.211312299
Short name T224
Test name
Test status
Simulation time 496485731290 ps
CPU time 1072.37 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:21:14 PM PST 24
Peak memory 200928 kb
Host smart-c1cb0ae1-3ada-414b-80a5-adb10b721f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211312299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.211312299
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2850360019
Short name T426
Test name
Test status
Simulation time 165341650999 ps
CPU time 400.46 seconds
Started Jan 17 01:03:24 PM PST 24
Finished Jan 17 01:10:05 PM PST 24
Peak memory 200744 kb
Host smart-f369de4a-ba93-41a7-9fac-b5e886f6069a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850360019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2850360019
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2820210633
Short name T96
Test name
Test status
Simulation time 491056796971 ps
CPU time 267.82 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:07:49 PM PST 24
Peak memory 200816 kb
Host smart-63526d7d-7897-4563-9268-011d49fd741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820210633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2820210633
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.545708842
Short name T474
Test name
Test status
Simulation time 484956733655 ps
CPU time 1134.72 seconds
Started Jan 17 01:03:19 PM PST 24
Finished Jan 17 01:22:16 PM PST 24
Peak memory 200876 kb
Host smart-026f401e-3986-4fa6-833a-ca767addb8fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=545708842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.545708842
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3277738907
Short name T257
Test name
Test status
Simulation time 502842795416 ps
CPU time 312.63 seconds
Started Jan 17 01:03:17 PM PST 24
Finished Jan 17 01:08:34 PM PST 24
Peak memory 200944 kb
Host smart-75406b36-c713-4db6-bede-964dc68f98ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277738907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3277738907
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1757087551
Short name T822
Test name
Test status
Simulation time 333902760954 ps
CPU time 179.25 seconds
Started Jan 17 01:03:24 PM PST 24
Finished Jan 17 01:06:24 PM PST 24
Peak memory 200868 kb
Host smart-43616de4-6952-4f4d-a78a-56c83227f4e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757087551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1757087551
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2382765608
Short name T720
Test name
Test status
Simulation time 67759740536 ps
CPU time 342.84 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:09:04 PM PST 24
Peak memory 201284 kb
Host smart-5599ef65-f997-4617-9490-9c6fd1dea827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382765608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2382765608
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3679156341
Short name T574
Test name
Test status
Simulation time 25068322766 ps
CPU time 13.76 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:03:35 PM PST 24
Peak memory 200724 kb
Host smart-00b5ca80-0820-42e2-ad22-bf7f91594678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679156341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3679156341
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.182782939
Short name T694
Test name
Test status
Simulation time 5354756312 ps
CPU time 8.37 seconds
Started Jan 17 01:03:24 PM PST 24
Finished Jan 17 01:03:33 PM PST 24
Peak memory 200748 kb
Host smart-6bfa1ae2-1413-4d89-8388-60c44638cab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182782939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.182782939
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3367648321
Short name T545
Test name
Test status
Simulation time 5758024532 ps
CPU time 3.22 seconds
Started Jan 17 01:03:19 PM PST 24
Finished Jan 17 01:03:24 PM PST 24
Peak memory 200700 kb
Host smart-c90e4d2a-2a4d-414e-821b-7f8dc746bd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367648321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3367648321
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4071094839
Short name T24
Test name
Test status
Simulation time 330934458785 ps
CPU time 162.43 seconds
Started Jan 17 01:03:21 PM PST 24
Finished Jan 17 01:06:04 PM PST 24
Peak memory 200972 kb
Host smart-03759a8e-92ef-4c9b-b36a-6fac84dcfec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071094839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4071094839
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2710293260
Short name T666
Test name
Test status
Simulation time 482007497 ps
CPU time 0.85 seconds
Started Jan 17 01:03:34 PM PST 24
Finished Jan 17 01:03:36 PM PST 24
Peak memory 200664 kb
Host smart-f6a59a7d-3738-4040-b1c8-842f0f287164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710293260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2710293260
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.863565411
Short name T134
Test name
Test status
Simulation time 166979644402 ps
CPU time 97.64 seconds
Started Jan 17 01:03:18 PM PST 24
Finished Jan 17 01:04:59 PM PST 24
Peak memory 200820 kb
Host smart-28b17979-891f-4d8b-b8ab-132664631dcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863565411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.863565411
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1265898161
Short name T92
Test name
Test status
Simulation time 166390052530 ps
CPU time 41.51 seconds
Started Jan 17 01:03:25 PM PST 24
Finished Jan 17 01:04:08 PM PST 24
Peak memory 200924 kb
Host smart-411d0236-6212-4b90-8afd-9a85738bc545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265898161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1265898161
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2880562200
Short name T250
Test name
Test status
Simulation time 494569212156 ps
CPU time 569.54 seconds
Started Jan 17 01:03:24 PM PST 24
Finished Jan 17 01:12:54 PM PST 24
Peak memory 200972 kb
Host smart-1590677b-45ee-4acf-911c-9cf0008395b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880562200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2880562200
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1676223291
Short name T547
Test name
Test status
Simulation time 324950403105 ps
CPU time 209.19 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:06:50 PM PST 24
Peak memory 200876 kb
Host smart-63fae66a-d7e8-4f7a-be4a-b1fd60614b12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676223291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1676223291
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2157526807
Short name T56
Test name
Test status
Simulation time 492979224939 ps
CPU time 1069.65 seconds
Started Jan 17 01:03:24 PM PST 24
Finished Jan 17 01:21:14 PM PST 24
Peak memory 200960 kb
Host smart-d2a0ef22-6c93-4ad0-96bf-25db0e86a90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157526807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2157526807
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3824864770
Short name T751
Test name
Test status
Simulation time 164239220824 ps
CPU time 363.49 seconds
Started Jan 17 01:03:23 PM PST 24
Finished Jan 17 01:09:27 PM PST 24
Peak memory 200868 kb
Host smart-fd0a0399-1baf-4c47-89f2-e98ab60cf609
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824864770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3824864770
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2981939492
Short name T499
Test name
Test status
Simulation time 330828936895 ps
CPU time 364.44 seconds
Started Jan 17 01:03:25 PM PST 24
Finished Jan 17 01:09:31 PM PST 24
Peak memory 200844 kb
Host smart-6beaf96c-8dd4-4b41-a85e-c5905791e42d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981939492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2981939492
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1680404310
Short name T670
Test name
Test status
Simulation time 88916596048 ps
CPU time 270.86 seconds
Started Jan 17 01:03:31 PM PST 24
Finished Jan 17 01:08:04 PM PST 24
Peak memory 201272 kb
Host smart-baaf4cd9-4ed8-4073-8c71-2dfee52a9cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680404310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1680404310
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.19929149
Short name T444
Test name
Test status
Simulation time 44640837325 ps
CPU time 26.59 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:03:48 PM PST 24
Peak memory 200660 kb
Host smart-a265f520-9758-4115-bf5b-2e5762c612d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19929149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.19929149
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3828300111
Short name T661
Test name
Test status
Simulation time 2967806981 ps
CPU time 4.03 seconds
Started Jan 17 01:03:26 PM PST 24
Finished Jan 17 01:03:31 PM PST 24
Peak memory 200728 kb
Host smart-f2d4f6c0-1003-47e3-a79a-2a59bb64896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828300111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3828300111
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4149881726
Short name T90
Test name
Test status
Simulation time 6061065254 ps
CPU time 3.88 seconds
Started Jan 17 01:03:20 PM PST 24
Finished Jan 17 01:03:25 PM PST 24
Peak memory 200732 kb
Host smart-0ea9c780-a874-4b96-94e3-3e288d1cdcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149881726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4149881726
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.4075846708
Short name T121
Test name
Test status
Simulation time 182463743126 ps
CPU time 253.64 seconds
Started Jan 17 01:03:41 PM PST 24
Finished Jan 17 01:07:55 PM PST 24
Peak memory 209700 kb
Host smart-f3119dc5-c1da-4db3-8fee-147fc50d7434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075846708 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.4075846708
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1637214830
Short name T520
Test name
Test status
Simulation time 290627511 ps
CPU time 1.32 seconds
Started Jan 17 01:03:48 PM PST 24
Finished Jan 17 01:03:50 PM PST 24
Peak memory 200644 kb
Host smart-2e74cb3f-5b86-4e9e-9a1f-2b9a45512044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637214830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1637214830
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3334589253
Short name T226
Test name
Test status
Simulation time 174525179456 ps
CPU time 24.99 seconds
Started Jan 17 01:03:31 PM PST 24
Finished Jan 17 01:03:59 PM PST 24
Peak memory 200968 kb
Host smart-889d55b6-eb9b-4d67-9b01-c1159097f862
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334589253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3334589253
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3062771635
Short name T256
Test name
Test status
Simulation time 325923197341 ps
CPU time 216.63 seconds
Started Jan 17 01:03:40 PM PST 24
Finished Jan 17 01:07:17 PM PST 24
Peak memory 200984 kb
Host smart-dc407824-bb12-4442-b0ef-4f64977ce41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062771635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3062771635
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3170046064
Short name T219
Test name
Test status
Simulation time 498821043937 ps
CPU time 446.12 seconds
Started Jan 17 01:03:33 PM PST 24
Finished Jan 17 01:11:01 PM PST 24
Peak memory 200872 kb
Host smart-542d939b-58da-4707-9f9c-39d6a5e541c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170046064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3170046064
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1573012703
Short name T850
Test name
Test status
Simulation time 323003634684 ps
CPU time 601.27 seconds
Started Jan 17 01:03:30 PM PST 24
Finished Jan 17 01:13:32 PM PST 24
Peak memory 200868 kb
Host smart-a4436a84-28bb-4c20-b531-e008f417d943
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573012703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1573012703
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2493894506
Short name T707
Test name
Test status
Simulation time 327481702076 ps
CPU time 756.85 seconds
Started Jan 17 01:03:36 PM PST 24
Finished Jan 17 01:16:14 PM PST 24
Peak memory 200900 kb
Host smart-95d105ea-457b-4107-baa7-760a37af9416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493894506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2493894506
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3257103134
Short name T565
Test name
Test status
Simulation time 498887383588 ps
CPU time 1176.87 seconds
Started Jan 17 01:03:31 PM PST 24
Finished Jan 17 01:23:10 PM PST 24
Peak memory 200760 kb
Host smart-24c2e83a-2400-4968-b306-c501185c280f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257103134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3257103134
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.340349339
Short name T794
Test name
Test status
Simulation time 167652271119 ps
CPU time 127.45 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:05:53 PM PST 24
Peak memory 200804 kb
Host smart-6a6fdaf2-e801-4d64-b220-aa29ebce81c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340349339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.340349339
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4001044272
Short name T620
Test name
Test status
Simulation time 116304547445 ps
CPU time 647.07 seconds
Started Jan 17 01:03:37 PM PST 24
Finished Jan 17 01:14:25 PM PST 24
Peak memory 201268 kb
Host smart-a4b41cff-f2b9-430a-aefb-337141d95998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001044272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4001044272
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3306076136
Short name T716
Test name
Test status
Simulation time 40544431801 ps
CPU time 10.41 seconds
Started Jan 17 01:03:33 PM PST 24
Finished Jan 17 01:03:46 PM PST 24
Peak memory 200732 kb
Host smart-cdff7bb9-b89a-408f-aa90-3feefd84609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306076136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3306076136
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1432413757
Short name T791
Test name
Test status
Simulation time 4808209230 ps
CPU time 6.43 seconds
Started Jan 17 01:03:51 PM PST 24
Finished Jan 17 01:03:58 PM PST 24
Peak memory 200728 kb
Host smart-071ca51c-98d4-46d4-af60-08b55173e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432413757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1432413757
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3784045233
Short name T780
Test name
Test status
Simulation time 5843550197 ps
CPU time 2.53 seconds
Started Jan 17 01:03:40 PM PST 24
Finished Jan 17 01:03:44 PM PST 24
Peak memory 200948 kb
Host smart-89f20b68-2911-4a12-99a2-bfe91cd1c1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784045233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3784045233
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2480237082
Short name T320
Test name
Test status
Simulation time 57099508275 ps
CPU time 143.16 seconds
Started Jan 17 01:03:44 PM PST 24
Finished Jan 17 01:06:08 PM PST 24
Peak memory 209656 kb
Host smart-ee4dd756-f5a0-47f4-8d72-d72ec39ef825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480237082 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2480237082
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2025066362
Short name T686
Test name
Test status
Simulation time 541102383 ps
CPU time 1.21 seconds
Started Jan 17 01:03:54 PM PST 24
Finished Jan 17 01:03:56 PM PST 24
Peak memory 200664 kb
Host smart-eeb5f41e-814c-4fa0-a1d9-eb3e87ec9758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025066362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2025066362
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1816611818
Short name T272
Test name
Test status
Simulation time 165068183277 ps
CPU time 95.89 seconds
Started Jan 17 01:03:55 PM PST 24
Finished Jan 17 01:05:38 PM PST 24
Peak memory 200808 kb
Host smart-aec8b7bd-c43f-4d5c-a89e-b8a79b02c88f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816611818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1816611818
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2039029270
Short name T667
Test name
Test status
Simulation time 487200933159 ps
CPU time 1160.87 seconds
Started Jan 17 01:03:31 PM PST 24
Finished Jan 17 01:22:56 PM PST 24
Peak memory 200880 kb
Host smart-87795eb6-7e05-40a3-bce9-13e0f66671d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039029270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2039029270
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3796798254
Short name T118
Test name
Test status
Simulation time 332462290319 ps
CPU time 351.69 seconds
Started Jan 17 01:03:59 PM PST 24
Finished Jan 17 01:09:54 PM PST 24
Peak memory 200912 kb
Host smart-54b50514-16d8-4151-8041-ee7b4959420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796798254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3796798254
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3869240679
Short name T146
Test name
Test status
Simulation time 503226545989 ps
CPU time 297.98 seconds
Started Jan 17 01:03:40 PM PST 24
Finished Jan 17 01:08:39 PM PST 24
Peak memory 200856 kb
Host smart-125e64e7-7bcc-4512-9581-cf2c4f68170b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869240679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3869240679
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2630265320
Short name T103
Test name
Test status
Simulation time 496073966540 ps
CPU time 1222.77 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:24:09 PM PST 24
Peak memory 200880 kb
Host smart-83d578a7-02f3-4a61-8c8a-904088eebea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630265320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2630265320
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3613195247
Short name T697
Test name
Test status
Simulation time 493496164130 ps
CPU time 626.9 seconds
Started Jan 17 01:03:35 PM PST 24
Finished Jan 17 01:14:02 PM PST 24
Peak memory 201076 kb
Host smart-04e46c9f-1036-4360-a643-61d3234a4641
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613195247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3613195247
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1926188938
Short name T144
Test name
Test status
Simulation time 167118427502 ps
CPU time 100.12 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:05:26 PM PST 24
Peak memory 200940 kb
Host smart-d5e4f506-451e-4f71-a177-590d23b84c41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926188938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1926188938
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1339562091
Short name T719
Test name
Test status
Simulation time 166370436353 ps
CPU time 305.94 seconds
Started Jan 17 01:03:42 PM PST 24
Finished Jan 17 01:08:49 PM PST 24
Peak memory 200868 kb
Host smart-aad51f88-62bd-400b-b706-51f1880065b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339562091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1339562091
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1884528664
Short name T140
Test name
Test status
Simulation time 43417444742 ps
CPU time 32.69 seconds
Started Jan 17 01:03:59 PM PST 24
Finished Jan 17 01:04:35 PM PST 24
Peak memory 200728 kb
Host smart-95426e07-6d8d-4d3a-826c-dc76e7e69f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884528664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1884528664
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.187196198
Short name T89
Test name
Test status
Simulation time 4525254232 ps
CPU time 3.44 seconds
Started Jan 17 01:03:55 PM PST 24
Finished Jan 17 01:04:05 PM PST 24
Peak memory 200716 kb
Host smart-3db51bf5-2e65-45d2-823d-ce85e0bd8def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187196198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.187196198
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3253649788
Short name T662
Test name
Test status
Simulation time 6028158920 ps
CPU time 8.15 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:03:53 PM PST 24
Peak memory 200712 kb
Host smart-e71f37bc-e3fb-43ab-8c6b-b80e8a4e0160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253649788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3253649788
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3025520797
Short name T53
Test name
Test status
Simulation time 370703569427 ps
CPU time 906.05 seconds
Started Jan 17 01:04:00 PM PST 24
Finished Jan 17 01:19:08 PM PST 24
Peak memory 200972 kb
Host smart-17e5f9ec-ba19-4e3a-ab7e-2801c5288144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025520797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3025520797
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1940340514
Short name T245
Test name
Test status
Simulation time 16161459667 ps
CPU time 37.91 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:04:40 PM PST 24
Peak memory 200944 kb
Host smart-7778367a-563a-4490-a19d-563e32de9737
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940340514 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1940340514
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.628254281
Short name T855
Test name
Test status
Simulation time 293126920 ps
CPU time 1.31 seconds
Started Jan 17 01:03:44 PM PST 24
Finished Jan 17 01:03:46 PM PST 24
Peak memory 200604 kb
Host smart-7f167186-ddfd-4769-b764-936f3c966334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628254281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.628254281
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2675364853
Short name T550
Test name
Test status
Simulation time 485030593572 ps
CPU time 303.73 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:09:14 PM PST 24
Peak memory 200744 kb
Host smart-ff4ad729-975a-4997-bb8b-eea46ae2df44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675364853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2675364853
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3989740828
Short name T131
Test name
Test status
Simulation time 496480964607 ps
CPU time 276.63 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:08:45 PM PST 24
Peak memory 200980 kb
Host smart-2f5a6e88-59aa-48f1-a2de-f25896a17b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989740828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3989740828
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1949531719
Short name T262
Test name
Test status
Simulation time 168032064899 ps
CPU time 409.11 seconds
Started Jan 17 01:04:06 PM PST 24
Finished Jan 17 01:10:57 PM PST 24
Peak memory 200872 kb
Host smart-c2cd1700-f90f-438b-8a03-0b096d91180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949531719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1949531719
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3061109443
Short name T211
Test name
Test status
Simulation time 332098506519 ps
CPU time 625.77 seconds
Started Jan 17 01:04:08 PM PST 24
Finished Jan 17 01:14:36 PM PST 24
Peak memory 200832 kb
Host smart-d6b51b92-5b54-49be-bdbc-d7214a8f69de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061109443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3061109443
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2900302914
Short name T122
Test name
Test status
Simulation time 494341025720 ps
CPU time 165.11 seconds
Started Jan 17 01:03:47 PM PST 24
Finished Jan 17 01:06:32 PM PST 24
Peak memory 200820 kb
Host smart-63757c3b-cc75-4be5-aa3c-274d58da5a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900302914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2900302914
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.709730910
Short name T465
Test name
Test status
Simulation time 163040834188 ps
CPU time 87.9 seconds
Started Jan 17 01:03:46 PM PST 24
Finished Jan 17 01:05:14 PM PST 24
Peak memory 200872 kb
Host smart-1e896389-9ca5-47cd-92f1-95489f0531f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=709730910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.709730910
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1800266551
Short name T673
Test name
Test status
Simulation time 390941241289 ps
CPU time 454.94 seconds
Started Jan 17 01:03:57 PM PST 24
Finished Jan 17 01:11:37 PM PST 24
Peak memory 200880 kb
Host smart-7c497cbc-8bc2-42e4-a588-5ba425dfc8ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800266551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1800266551
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3732303859
Short name T769
Test name
Test status
Simulation time 502966139978 ps
CPU time 299.85 seconds
Started Jan 17 01:04:06 PM PST 24
Finished Jan 17 01:09:08 PM PST 24
Peak memory 200872 kb
Host smart-56b30f13-da6d-463b-a4e4-01dcabf3d384
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732303859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3732303859
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3083563639
Short name T196
Test name
Test status
Simulation time 108900386900 ps
CPU time 449.56 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:11:38 PM PST 24
Peak memory 201376 kb
Host smart-4fa4f662-3812-42de-bd25-6daecb86ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083563639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3083563639
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1986650428
Short name T676
Test name
Test status
Simulation time 27256081358 ps
CPU time 5.6 seconds
Started Jan 17 01:04:11 PM PST 24
Finished Jan 17 01:04:17 PM PST 24
Peak memory 200724 kb
Host smart-afa63862-b200-4473-a9e5-d4500f7c93f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986650428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1986650428
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3697517359
Short name T830
Test name
Test status
Simulation time 3617048690 ps
CPU time 9.4 seconds
Started Jan 17 01:04:08 PM PST 24
Finished Jan 17 01:04:20 PM PST 24
Peak memory 200732 kb
Host smart-fc21d914-b65f-4171-80c8-60afb9009d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697517359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3697517359
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2009487030
Short name T478
Test name
Test status
Simulation time 5998474383 ps
CPU time 4.08 seconds
Started Jan 17 01:04:04 PM PST 24
Finished Jan 17 01:04:09 PM PST 24
Peak memory 200724 kb
Host smart-1744418d-6f17-4f13-a287-d19aceb3cbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009487030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2009487030
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1665252256
Short name T486
Test name
Test status
Simulation time 436914681 ps
CPU time 0.9 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:03:47 PM PST 24
Peak memory 199960 kb
Host smart-cf2a732a-0b0e-46cd-b6d0-fb2b4f341a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665252256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1665252256
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3239308638
Short name T244
Test name
Test status
Simulation time 331821077185 ps
CPU time 60.96 seconds
Started Jan 17 01:03:35 PM PST 24
Finished Jan 17 01:04:37 PM PST 24
Peak memory 200868 kb
Host smart-9ca31b95-379a-4246-b004-c1ac4487b168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239308638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3239308638
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2491725252
Short name T270
Test name
Test status
Simulation time 165151165811 ps
CPU time 368.89 seconds
Started Jan 17 01:03:41 PM PST 24
Finished Jan 17 01:09:51 PM PST 24
Peak memory 200880 kb
Host smart-92c17086-4f8e-4184-9bb9-60bf8f6724f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491725252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2491725252
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3181568597
Short name T847
Test name
Test status
Simulation time 330529454542 ps
CPU time 379.18 seconds
Started Jan 17 01:03:38 PM PST 24
Finished Jan 17 01:09:57 PM PST 24
Peak memory 200928 kb
Host smart-16ba13a5-8787-418b-91c2-8fb8e7d5b6ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181568597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3181568597
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.443757980
Short name T789
Test name
Test status
Simulation time 162760330321 ps
CPU time 364.69 seconds
Started Jan 17 01:03:44 PM PST 24
Finished Jan 17 01:09:49 PM PST 24
Peak memory 200888 kb
Host smart-662d6b2d-4bc9-4f44-9813-1cb9a69a3c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443757980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.443757980
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1074350808
Short name T440
Test name
Test status
Simulation time 312162990299 ps
CPU time 314.16 seconds
Started Jan 17 01:03:40 PM PST 24
Finished Jan 17 01:08:55 PM PST 24
Peak memory 200848 kb
Host smart-a1f8846b-403c-4908-9c75-9fe4790f7bc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074350808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1074350808
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.340488154
Short name T290
Test name
Test status
Simulation time 484849820412 ps
CPU time 267.7 seconds
Started Jan 17 01:03:51 PM PST 24
Finished Jan 17 01:08:21 PM PST 24
Peak memory 200824 kb
Host smart-18e2a23a-52c5-4dfd-93c5-dbc5e198b7ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340488154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.340488154
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.4234997133
Short name T659
Test name
Test status
Simulation time 495126214401 ps
CPU time 1094.2 seconds
Started Jan 17 01:03:38 PM PST 24
Finished Jan 17 01:21:53 PM PST 24
Peak memory 200824 kb
Host smart-391f079a-f0ed-4c59-9236-e66568c7056b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234997133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.4234997133
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.587274401
Short name T187
Test name
Test status
Simulation time 109789858360 ps
CPU time 423.55 seconds
Started Jan 17 01:03:41 PM PST 24
Finished Jan 17 01:10:45 PM PST 24
Peak memory 201292 kb
Host smart-bcf0ca08-bc68-4114-952c-ccde1c0cad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587274401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.587274401
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2421738991
Short name T564
Test name
Test status
Simulation time 32415150553 ps
CPU time 77.78 seconds
Started Jan 17 01:03:37 PM PST 24
Finished Jan 17 01:04:55 PM PST 24
Peak memory 200708 kb
Host smart-accafa2c-e658-4d0f-9cce-9b5e2fd03b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421738991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2421738991
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2834550578
Short name T457
Test name
Test status
Simulation time 3870895979 ps
CPU time 2.8 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:03:49 PM PST 24
Peak memory 200732 kb
Host smart-7d5fe280-ac5c-4ef8-838e-6bd5e80755bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834550578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2834550578
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2453975151
Short name T608
Test name
Test status
Simulation time 5933940122 ps
CPU time 14.82 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:04:00 PM PST 24
Peak memory 200692 kb
Host smart-3d6bdd20-4f12-4fe5-bf44-ebdc18838a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453975151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2453975151
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2982151216
Short name T843
Test name
Test status
Simulation time 460682781 ps
CPU time 1.14 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:04:03 PM PST 24
Peak memory 200636 kb
Host smart-e90e5871-5b6e-4eee-8863-1c48a46a6d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982151216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2982151216
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2308982427
Short name T774
Test name
Test status
Simulation time 336386729263 ps
CPU time 757.82 seconds
Started Jan 17 01:03:48 PM PST 24
Finished Jan 17 01:16:27 PM PST 24
Peak memory 200896 kb
Host smart-42175c9f-5277-4cf1-8f20-61d0bd5e6814
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308982427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2308982427
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.960017296
Short name T150
Test name
Test status
Simulation time 327539788905 ps
CPU time 705.25 seconds
Started Jan 17 01:03:42 PM PST 24
Finished Jan 17 01:15:28 PM PST 24
Peak memory 200960 kb
Host smart-a846d04a-c2ec-4697-bb9b-0bb00aeab049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960017296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.960017296
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1537439162
Short name T685
Test name
Test status
Simulation time 480591211371 ps
CPU time 477.54 seconds
Started Jan 17 01:03:36 PM PST 24
Finished Jan 17 01:11:34 PM PST 24
Peak memory 200884 kb
Host smart-18681846-9a22-491e-9e6e-606a6dadc1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537439162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1537439162
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.633422990
Short name T692
Test name
Test status
Simulation time 323315831581 ps
CPU time 195.92 seconds
Started Jan 17 01:03:47 PM PST 24
Finished Jan 17 01:07:04 PM PST 24
Peak memory 200820 kb
Host smart-8dc7d00c-9d96-4291-8bf8-9b8251af2dbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=633422990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.633422990
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.959853552
Short name T500
Test name
Test status
Simulation time 486433223927 ps
CPU time 302.77 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:08:49 PM PST 24
Peak memory 200876 kb
Host smart-19cb1038-7bba-47ec-ac74-fac7cb4b5a44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=959853552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.959853552
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1157433360
Short name T849
Test name
Test status
Simulation time 332678190463 ps
CPU time 793.22 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:16:59 PM PST 24
Peak memory 200940 kb
Host smart-ec1bf1ce-42f0-4cfd-8eb2-3a23cda12375
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157433360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1157433360
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.707319205
Short name T838
Test name
Test status
Simulation time 492127509515 ps
CPU time 1110.24 seconds
Started Jan 17 01:03:46 PM PST 24
Finished Jan 17 01:22:17 PM PST 24
Peak memory 200940 kb
Host smart-4f93ed10-6b83-4743-a4bb-109dbf2ad5e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707319205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.707319205
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.572664107
Short name T569
Test name
Test status
Simulation time 98474139356 ps
CPU time 446.88 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:11:13 PM PST 24
Peak memory 201264 kb
Host smart-662bdfc6-aed8-49d6-9b88-436c10c3c569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572664107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.572664107
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1200281280
Short name T469
Test name
Test status
Simulation time 35955119892 ps
CPU time 19.21 seconds
Started Jan 17 01:03:43 PM PST 24
Finished Jan 17 01:04:03 PM PST 24
Peak memory 200748 kb
Host smart-fe2a25c8-a640-4d4e-b547-ae23e44b0e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200281280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1200281280
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1388036179
Short name T516
Test name
Test status
Simulation time 3734444169 ps
CPU time 10.48 seconds
Started Jan 17 01:03:58 PM PST 24
Finished Jan 17 01:04:12 PM PST 24
Peak memory 200728 kb
Host smart-5c1f38d6-7a04-411c-b7df-9ef7a6c6fca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388036179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1388036179
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3376364319
Short name T493
Test name
Test status
Simulation time 5551815522 ps
CPU time 13.96 seconds
Started Jan 17 01:03:48 PM PST 24
Finished Jan 17 01:04:03 PM PST 24
Peak memory 200684 kb
Host smart-efa583ca-3615-483f-bdd9-5c98874e1477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376364319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3376364319
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1630558219
Short name T279
Test name
Test status
Simulation time 91096793100 ps
CPU time 123.06 seconds
Started Jan 17 01:03:58 PM PST 24
Finished Jan 17 01:06:05 PM PST 24
Peak memory 209500 kb
Host smart-426888a3-41b4-4eb5-8642-ab26e61a44fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630558219 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1630558219
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1978999428
Short name T596
Test name
Test status
Simulation time 354445576 ps
CPU time 1.36 seconds
Started Jan 17 01:03:58 PM PST 24
Finished Jan 17 01:04:03 PM PST 24
Peak memory 200660 kb
Host smart-3dc56ff3-24d8-4625-beae-b1d5e1e6a980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978999428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1978999428
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2924236186
Short name T37
Test name
Test status
Simulation time 163719810907 ps
CPU time 15.82 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:04:18 PM PST 24
Peak memory 200864 kb
Host smart-0a3dd33f-dca1-449a-aeff-a25676d9fe45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924236186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2924236186
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.30060872
Short name T206
Test name
Test status
Simulation time 335631869703 ps
CPU time 218.6 seconds
Started Jan 17 01:03:57 PM PST 24
Finished Jan 17 01:07:40 PM PST 24
Peak memory 200896 kb
Host smart-c957d601-02ef-4a83-b119-3ad0a1aaabd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30060872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.30060872
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4290274001
Short name T742
Test name
Test status
Simulation time 162188500603 ps
CPU time 174.02 seconds
Started Jan 17 01:04:04 PM PST 24
Finished Jan 17 01:06:59 PM PST 24
Peak memory 200936 kb
Host smart-b1bda91f-2076-47a7-a8e9-3e9678d950c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290274001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.4290274001
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.408769643
Short name T859
Test name
Test status
Simulation time 486429152338 ps
CPU time 81.57 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:05:32 PM PST 24
Peak memory 200792 kb
Host smart-f6e73fa8-0667-4e25-86ae-134d60c2e479
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=408769643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.408769643
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1279794439
Short name T109
Test name
Test status
Simulation time 163928142040 ps
CPU time 394.56 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:10:21 PM PST 24
Peak memory 200792 kb
Host smart-884a9b10-f4fd-4fba-beb1-74a84f34597f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279794439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1279794439
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1784120373
Short name T460
Test name
Test status
Simulation time 495533568438 ps
CPU time 1181.91 seconds
Started Jan 17 01:03:46 PM PST 24
Finished Jan 17 01:23:28 PM PST 24
Peak memory 200808 kb
Host smart-c9220eb8-d1a4-408a-8947-bb3e0e8714df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784120373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1784120373
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.417702116
Short name T119
Test name
Test status
Simulation time 488534168086 ps
CPU time 156.4 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:06:38 PM PST 24
Peak memory 200820 kb
Host smart-8a887519-1df0-43a4-a2c5-e380b70cf4d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417702116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.417702116
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3602186704
Short name T511
Test name
Test status
Simulation time 497974368086 ps
CPU time 301.77 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:09:04 PM PST 24
Peak memory 200876 kb
Host smart-8c8fcf3e-4f6e-4c27-886f-25820468457f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602186704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3602186704
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3726225441
Short name T607
Test name
Test status
Simulation time 64028425558 ps
CPU time 337.64 seconds
Started Jan 17 01:03:53 PM PST 24
Finished Jan 17 01:09:32 PM PST 24
Peak memory 201296 kb
Host smart-2f489925-49b4-4733-a4d2-b5fbecf279ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726225441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3726225441
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3164941721
Short name T42
Test name
Test status
Simulation time 38062117296 ps
CPU time 49.15 seconds
Started Jan 17 01:03:51 PM PST 24
Finished Jan 17 01:04:42 PM PST 24
Peak memory 200664 kb
Host smart-c1beabd7-fc07-4b4e-810a-973794d704e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164941721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3164941721
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.120224521
Short name T561
Test name
Test status
Simulation time 4840465209 ps
CPU time 12.79 seconds
Started Jan 17 01:03:50 PM PST 24
Finished Jan 17 01:04:05 PM PST 24
Peak memory 200704 kb
Host smart-457d6ef2-0223-4be0-8824-928f544ef8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120224521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.120224521
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4138532293
Short name T757
Test name
Test status
Simulation time 5682917819 ps
CPU time 3.97 seconds
Started Jan 17 01:03:58 PM PST 24
Finished Jan 17 01:04:06 PM PST 24
Peak memory 200780 kb
Host smart-1a43724d-d07e-48ba-8f1c-38cbfeb6b93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138532293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4138532293
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1788637635
Short name T192
Test name
Test status
Simulation time 476914390383 ps
CPU time 875.03 seconds
Started Jan 17 01:03:43 PM PST 24
Finished Jan 17 01:18:19 PM PST 24
Peak memory 210100 kb
Host smart-f33a7d77-7bfa-476d-97c2-4e2db5a5b105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788637635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1788637635
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1946717723
Short name T182
Test name
Test status
Simulation time 177105698264 ps
CPU time 196.08 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:07:18 PM PST 24
Peak memory 214680 kb
Host smart-33d9b832-bac0-429a-b2f7-48bcbde2d9d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946717723 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1946717723
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1345306694
Short name T688
Test name
Test status
Simulation time 388655049 ps
CPU time 1.05 seconds
Started Jan 17 01:03:47 PM PST 24
Finished Jan 17 01:03:48 PM PST 24
Peak memory 200620 kb
Host smart-f663a634-733b-43a8-9886-73289a203089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345306694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1345306694
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.272673458
Short name T296
Test name
Test status
Simulation time 160893355258 ps
CPU time 202.16 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:07:07 PM PST 24
Peak memory 200856 kb
Host smart-16e37406-4509-4d45-92b2-9301c3235994
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272673458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.272673458
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.840981476
Short name T152
Test name
Test status
Simulation time 498829704577 ps
CPU time 313.76 seconds
Started Jan 17 01:03:44 PM PST 24
Finished Jan 17 01:08:58 PM PST 24
Peak memory 200944 kb
Host smart-60141d2b-47ba-4a89-9566-ca65f68fb794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840981476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.840981476
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3417449773
Short name T491
Test name
Test status
Simulation time 163695337384 ps
CPU time 101.55 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:05:43 PM PST 24
Peak memory 200820 kb
Host smart-8ee4a5dd-5dc3-48ae-a587-528af4e30a05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417449773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3417449773
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.4021889096
Short name T311
Test name
Test status
Simulation time 330938322022 ps
CPU time 252.78 seconds
Started Jan 17 01:03:44 PM PST 24
Finished Jan 17 01:07:58 PM PST 24
Peak memory 200928 kb
Host smart-b6762cc2-e9b3-4108-8d69-fcca604ed1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021889096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.4021889096
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1317025327
Short name T54
Test name
Test status
Simulation time 329626309306 ps
CPU time 208.59 seconds
Started Jan 17 01:03:49 PM PST 24
Finished Jan 17 01:07:19 PM PST 24
Peak memory 200820 kb
Host smart-1524ee03-d01a-40ab-a9a5-14714ebdba03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317025327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1317025327
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.77501469
Short name T128
Test name
Test status
Simulation time 330031969933 ps
CPU time 174.56 seconds
Started Jan 17 01:03:58 PM PST 24
Finished Jan 17 01:06:56 PM PST 24
Peak memory 200876 kb
Host smart-940ba67d-fa0d-4f0b-80e6-fed1d90a9829
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77501469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_w
akeup.77501469
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3913660768
Short name T738
Test name
Test status
Simulation time 498115588058 ps
CPU time 205.75 seconds
Started Jan 17 01:03:55 PM PST 24
Finished Jan 17 01:07:28 PM PST 24
Peak memory 200872 kb
Host smart-8583b8f8-dfd7-4d9b-8451-2a4ca2f335dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913660768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3913660768
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3087902573
Short name T691
Test name
Test status
Simulation time 125484283964 ps
CPU time 673.11 seconds
Started Jan 17 01:03:52 PM PST 24
Finished Jan 17 01:15:07 PM PST 24
Peak memory 201420 kb
Host smart-1770d1cd-d957-417a-b1fe-e4bee3ead170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087902573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3087902573
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.181927561
Short name T473
Test name
Test status
Simulation time 30478213718 ps
CPU time 18.21 seconds
Started Jan 17 01:03:43 PM PST 24
Finished Jan 17 01:04:02 PM PST 24
Peak memory 200672 kb
Host smart-69276aae-240c-412a-ab35-1f248d8a4d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181927561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.181927561
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.4053888394
Short name T605
Test name
Test status
Simulation time 4153240802 ps
CPU time 9.62 seconds
Started Jan 17 01:03:50 PM PST 24
Finished Jan 17 01:04:01 PM PST 24
Peak memory 200728 kb
Host smart-5ad6852e-ace1-4e23-a0de-6d771ca44e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053888394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4053888394
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.179643426
Short name T714
Test name
Test status
Simulation time 5634490798 ps
CPU time 1.64 seconds
Started Jan 17 01:03:45 PM PST 24
Finished Jan 17 01:03:48 PM PST 24
Peak memory 200600 kb
Host smart-59d77980-c953-41cc-aa02-c5de9748cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179643426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.179643426
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1947620085
Short name T142
Test name
Test status
Simulation time 169293802844 ps
CPU time 98.7 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:05:41 PM PST 24
Peak memory 200816 kb
Host smart-d96a79f2-32a2-43a7-8147-b2e4ded11d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947620085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1947620085
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.645317550
Short name T795
Test name
Test status
Simulation time 22014793809 ps
CPU time 51.74 seconds
Started Jan 17 01:03:51 PM PST 24
Finished Jan 17 01:04:45 PM PST 24
Peak memory 200736 kb
Host smart-4b712713-6810-4357-a9d0-4705a3c1920b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645317550 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.645317550
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2275576321
Short name T464
Test name
Test status
Simulation time 428708990 ps
CPU time 1.67 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:03:06 PM PST 24
Peak memory 200672 kb
Host smart-3e5c2ce4-71ac-457d-8d53-0020fb072bdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275576321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2275576321
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1021461736
Short name T299
Test name
Test status
Simulation time 330063194901 ps
CPU time 208.85 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:06:32 PM PST 24
Peak memory 200924 kb
Host smart-21e50f9d-29c1-430a-8b02-d3cc1de2d3bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021461736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1021461736
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.940570177
Short name T265
Test name
Test status
Simulation time 334809196334 ps
CPU time 797.06 seconds
Started Jan 17 01:02:59 PM PST 24
Finished Jan 17 01:16:20 PM PST 24
Peak memory 200944 kb
Host smart-6d4e4e35-7044-48dc-8447-4fd48d8e2ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940570177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.940570177
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3616590921
Short name T559
Test name
Test status
Simulation time 171074927313 ps
CPU time 225.19 seconds
Started Jan 17 01:02:56 PM PST 24
Finished Jan 17 01:06:42 PM PST 24
Peak memory 200812 kb
Host smart-7f6612be-42be-44ec-85c7-0300ce86026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616590921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3616590921
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3051371867
Short name T449
Test name
Test status
Simulation time 332814279889 ps
CPU time 742.28 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:15:26 PM PST 24
Peak memory 200872 kb
Host smart-4097b0b0-f19b-4448-9730-a0aeb32b6403
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051371867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3051371867
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3109241848
Short name T759
Test name
Test status
Simulation time 158878744013 ps
CPU time 175 seconds
Started Jan 17 01:02:51 PM PST 24
Finished Jan 17 01:05:47 PM PST 24
Peak memory 200896 kb
Host smart-3744dd7c-eb7d-4337-a82c-b8eaf21ee2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109241848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3109241848
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1814949408
Short name T557
Test name
Test status
Simulation time 329780154380 ps
CPU time 405.62 seconds
Started Jan 17 01:02:52 PM PST 24
Finished Jan 17 01:09:38 PM PST 24
Peak memory 200832 kb
Host smart-8ae3030c-08f4-4d24-b4c5-6e701826a105
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814949408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1814949408
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1638110982
Short name T466
Test name
Test status
Simulation time 161974916053 ps
CPU time 345.3 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:08:48 PM PST 24
Peak memory 200856 kb
Host smart-c148c46e-36fd-4354-a5ec-35f6bddf43af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638110982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1638110982
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2437265605
Short name T334
Test name
Test status
Simulation time 109206215933 ps
CPU time 615.24 seconds
Started Jan 17 01:02:54 PM PST 24
Finished Jan 17 01:13:10 PM PST 24
Peak memory 201308 kb
Host smart-ab2a5d04-cf9c-4e85-a5db-ba5822de93dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437265605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2437265605
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2188417322
Short name T615
Test name
Test status
Simulation time 21834168407 ps
CPU time 13.03 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:03:18 PM PST 24
Peak memory 200692 kb
Host smart-030dd6ee-cbc9-4983-a69c-cbda4352cb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188417322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2188417322
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.427143203
Short name T771
Test name
Test status
Simulation time 4254492227 ps
CPU time 10.37 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:03:15 PM PST 24
Peak memory 200740 kb
Host smart-1187dd84-ec65-46c3-8c0b-a18d3edbd5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427143203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.427143203
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3474253146
Short name T48
Test name
Test status
Simulation time 4176183149 ps
CPU time 3.18 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:03:08 PM PST 24
Peak memory 216192 kb
Host smart-f33d1086-84d2-4883-b81c-f525e97e2d49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474253146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3474253146
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2478465038
Short name T424
Test name
Test status
Simulation time 5891645821 ps
CPU time 7.77 seconds
Started Jan 17 01:02:53 PM PST 24
Finished Jan 17 01:03:02 PM PST 24
Peak memory 200736 kb
Host smart-de483687-68dc-448b-87a3-7a5f7e2b4b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478465038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2478465038
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.89519064
Short name T657
Test name
Test status
Simulation time 215958487820 ps
CPU time 130.92 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:05:15 PM PST 24
Peak memory 200800 kb
Host smart-20619618-644b-46e3-a51e-75c760489ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89519064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.89519064
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2989233298
Short name T19
Test name
Test status
Simulation time 14644670893 ps
CPU time 33 seconds
Started Jan 17 01:03:05 PM PST 24
Finished Jan 17 01:03:38 PM PST 24
Peak memory 200944 kb
Host smart-f385318d-5dda-46cb-8488-85487b671a63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989233298 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2989233298
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.47544957
Short name T612
Test name
Test status
Simulation time 402441544 ps
CPU time 0.78 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:04:11 PM PST 24
Peak memory 200572 kb
Host smart-b4918043-6321-4b10-a24f-4626cf533d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47544957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.47544957
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2317092699
Short name T530
Test name
Test status
Simulation time 159922910508 ps
CPU time 195.53 seconds
Started Jan 17 01:03:58 PM PST 24
Finished Jan 17 01:07:17 PM PST 24
Peak memory 200828 kb
Host smart-160fabe0-5440-4fca-8b8e-0d40941e78d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317092699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2317092699
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2290345011
Short name T826
Test name
Test status
Simulation time 320467357026 ps
CPU time 274.38 seconds
Started Jan 17 01:04:11 PM PST 24
Finished Jan 17 01:08:46 PM PST 24
Peak memory 200876 kb
Host smart-b79ed4ab-f834-4b17-b67b-f01c7a2e66b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290345011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2290345011
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3398060464
Short name T519
Test name
Test status
Simulation time 162467668921 ps
CPU time 360.56 seconds
Started Jan 17 01:04:06 PM PST 24
Finished Jan 17 01:10:09 PM PST 24
Peak memory 200976 kb
Host smart-526f533b-9978-41c1-bdfd-b516ba6469ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398060464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3398060464
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1174681959
Short name T61
Test name
Test status
Simulation time 326908962870 ps
CPU time 365.89 seconds
Started Jan 17 01:04:04 PM PST 24
Finished Jan 17 01:10:10 PM PST 24
Peak memory 200792 kb
Host smart-a34d2953-2ebf-45a2-88c2-80bcf03a1ce8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174681959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1174681959
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.985099877
Short name T525
Test name
Test status
Simulation time 165020056604 ps
CPU time 52.34 seconds
Started Jan 17 01:04:05 PM PST 24
Finished Jan 17 01:04:59 PM PST 24
Peak memory 200892 kb
Host smart-47072abd-9ee6-4e76-bb1d-fe94fdeb1d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985099877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.985099877
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2468678615
Short name T616
Test name
Test status
Simulation time 162787227063 ps
CPU time 27.54 seconds
Started Jan 17 01:03:55 PM PST 24
Finished Jan 17 01:04:29 PM PST 24
Peak memory 200864 kb
Host smart-ecf8692f-82c4-49f3-87ff-f70bdf5fc597
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468678615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2468678615
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2289634439
Short name T135
Test name
Test status
Simulation time 325048510010 ps
CPU time 193.03 seconds
Started Jan 17 01:04:06 PM PST 24
Finished Jan 17 01:07:21 PM PST 24
Peak memory 200572 kb
Host smart-e86bfdf2-7368-4f07-9284-2c4c70cccd0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289634439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2289634439
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.744398502
Short name T159
Test name
Test status
Simulation time 327193334365 ps
CPU time 271.84 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:08:34 PM PST 24
Peak memory 200792 kb
Host smart-df335d4a-61d4-4eab-a95c-03787695d157
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744398502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.744398502
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3248006699
Short name T617
Test name
Test status
Simulation time 106261954332 ps
CPU time 408.73 seconds
Started Jan 17 01:04:05 PM PST 24
Finished Jan 17 01:10:54 PM PST 24
Peak memory 201320 kb
Host smart-4c5475c7-1457-4352-8069-63062d7227ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248006699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3248006699
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1740064232
Short name T429
Test name
Test status
Simulation time 28538366510 ps
CPU time 63.73 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:05:06 PM PST 24
Peak memory 200724 kb
Host smart-a0ba86c6-5d2e-45e1-9bf2-a9c05a5a15ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740064232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1740064232
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.109615790
Short name T576
Test name
Test status
Simulation time 4308848127 ps
CPU time 2.28 seconds
Started Jan 17 01:04:01 PM PST 24
Finished Jan 17 01:04:04 PM PST 24
Peak memory 200704 kb
Host smart-1c8f5b34-3fd1-480b-bcce-8ed4ef448aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109615790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.109615790
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.6419921
Short name T443
Test name
Test status
Simulation time 5903397693 ps
CPU time 14.46 seconds
Started Jan 17 01:03:56 PM PST 24
Finished Jan 17 01:04:16 PM PST 24
Peak memory 200688 kb
Host smart-067b2e01-66e6-41b0-8019-42bb8bd37c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6419921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.6419921
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3421676798
Short name T700
Test name
Test status
Simulation time 313558354818 ps
CPU time 207.84 seconds
Started Jan 17 01:04:06 PM PST 24
Finished Jan 17 01:07:35 PM PST 24
Peak memory 209580 kb
Host smart-ef2b9449-dcc4-474c-820b-6a1d211600f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421676798 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3421676798
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4117071548
Short name T46
Test name
Test status
Simulation time 466570756 ps
CPU time 1.02 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:04:11 PM PST 24
Peak memory 200632 kb
Host smart-713abef8-0d5c-4d29-a93c-c36522367785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117071548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4117071548
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3892369248
Short name T252
Test name
Test status
Simulation time 500465522730 ps
CPU time 214.99 seconds
Started Jan 17 01:03:57 PM PST 24
Finished Jan 17 01:07:37 PM PST 24
Peak memory 200892 kb
Host smart-c9806c79-732b-4373-9c46-5d57494e01e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892369248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3892369248
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1845290429
Short name T587
Test name
Test status
Simulation time 161428242777 ps
CPU time 370.2 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:10:20 PM PST 24
Peak memory 200860 kb
Host smart-608299c0-83c5-4498-8b8c-fc410901d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845290429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1845290429
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.382514505
Short name T524
Test name
Test status
Simulation time 160144164535 ps
CPU time 103.26 seconds
Started Jan 17 01:04:01 PM PST 24
Finished Jan 17 01:05:45 PM PST 24
Peak memory 200804 kb
Host smart-887a875a-e308-4797-a28f-65c6fd2b245b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=382514505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.382514505
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1292650587
Short name T696
Test name
Test status
Simulation time 167888865638 ps
CPU time 41.71 seconds
Started Jan 17 01:04:04 PM PST 24
Finished Jan 17 01:04:47 PM PST 24
Peak memory 200848 kb
Host smart-429598ea-86c9-4bae-a66c-051a3aaffb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292650587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1292650587
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3310052900
Short name T125
Test name
Test status
Simulation time 166868063458 ps
CPU time 42.45 seconds
Started Jan 17 01:04:03 PM PST 24
Finished Jan 17 01:04:47 PM PST 24
Peak memory 200864 kb
Host smart-514d36dc-2068-4479-9f1c-29105ddd8dcc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310052900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3310052900
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.506330649
Short name T104
Test name
Test status
Simulation time 491874509618 ps
CPU time 583.76 seconds
Started Jan 17 01:04:04 PM PST 24
Finished Jan 17 01:13:49 PM PST 24
Peak memory 200876 kb
Host smart-42fda0d3-3664-40ae-bcee-fbe8d64fcd07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506330649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.506330649
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.126079275
Short name T558
Test name
Test status
Simulation time 162744733014 ps
CPU time 178.96 seconds
Started Jan 17 01:03:53 PM PST 24
Finished Jan 17 01:06:53 PM PST 24
Peak memory 200868 kb
Host smart-e0928e3c-f439-4fdf-bb7a-84d21504c841
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126079275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.126079275
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3597792309
Short name T447
Test name
Test status
Simulation time 67797894313 ps
CPU time 239.23 seconds
Started Jan 17 01:04:05 PM PST 24
Finished Jan 17 01:08:06 PM PST 24
Peak memory 201380 kb
Host smart-0be035f6-1e01-4049-8120-9b9a3c34c606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597792309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3597792309
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1898073794
Short name T468
Test name
Test status
Simulation time 24884915885 ps
CPU time 57.97 seconds
Started Jan 17 01:04:12 PM PST 24
Finished Jan 17 01:05:10 PM PST 24
Peak memory 199648 kb
Host smart-d2aebc5b-91af-400c-af8e-7842d334ce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898073794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1898073794
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.387404212
Short name T538
Test name
Test status
Simulation time 4583061702 ps
CPU time 11.74 seconds
Started Jan 17 01:03:58 PM PST 24
Finished Jan 17 01:04:14 PM PST 24
Peak memory 200748 kb
Host smart-7ce32e52-6ecd-43d1-92bd-0ca3029003ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387404212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.387404212
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3919094651
Short name T756
Test name
Test status
Simulation time 5765102386 ps
CPU time 4.23 seconds
Started Jan 17 01:04:06 PM PST 24
Finished Jan 17 01:04:12 PM PST 24
Peak memory 200652 kb
Host smart-1349cc47-a688-4cf2-a094-4dd336b3682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919094651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3919094651
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.880520135
Short name T735
Test name
Test status
Simulation time 169629010426 ps
CPU time 99.59 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:05:50 PM PST 24
Peak memory 200948 kb
Host smart-f5b07a19-79ca-43ac-b06e-151ffd9857e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880520135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
880520135
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2115509433
Short name T652
Test name
Test status
Simulation time 196939660271 ps
CPU time 406.39 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:10:57 PM PST 24
Peak memory 209524 kb
Host smart-90e597e3-541a-4b6f-84be-a588515cdf8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115509433 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2115509433
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1010641542
Short name T782
Test name
Test status
Simulation time 500223797 ps
CPU time 0.88 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:04:18 PM PST 24
Peak memory 200660 kb
Host smart-8fa13585-330f-4b0c-a548-d66aca2303ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010641542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1010641542
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4280394937
Short name T698
Test name
Test status
Simulation time 170740548218 ps
CPU time 357.58 seconds
Started Jan 17 01:04:03 PM PST 24
Finished Jan 17 01:10:02 PM PST 24
Peak memory 200904 kb
Host smart-bc588bb7-6c7d-4ca6-a3de-ce279a115393
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280394937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4280394937
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.209205007
Short name T808
Test name
Test status
Simulation time 328461783364 ps
CPU time 403.85 seconds
Started Jan 17 01:04:06 PM PST 24
Finished Jan 17 01:10:52 PM PST 24
Peak memory 200808 kb
Host smart-2c6badf3-86c7-4d3b-88c5-2afdf63a3825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209205007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.209205007
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1548661358
Short name T732
Test name
Test status
Simulation time 496481279615 ps
CPU time 127.12 seconds
Started Jan 17 01:04:06 PM PST 24
Finished Jan 17 01:06:15 PM PST 24
Peak memory 200936 kb
Host smart-f2b044fc-197c-4dd9-b3ca-b484e63ec666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548661358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1548661358
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3964421663
Short name T611
Test name
Test status
Simulation time 170640637805 ps
CPU time 399.13 seconds
Started Jan 17 01:04:04 PM PST 24
Finished Jan 17 01:10:44 PM PST 24
Peak memory 200820 kb
Host smart-6627fa6a-cc00-4890-947a-2a7a1e2207ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964421663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3964421663
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2307659552
Short name T281
Test name
Test status
Simulation time 327883869764 ps
CPU time 176.14 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:07:05 PM PST 24
Peak memory 200824 kb
Host smart-c2d99eca-382b-49b8-9836-bf4418d4f262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307659552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2307659552
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1657247946
Short name T586
Test name
Test status
Simulation time 331905815438 ps
CPU time 184.89 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:07:13 PM PST 24
Peak memory 200868 kb
Host smart-eda18097-1221-4568-91bf-c6d694052418
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657247946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1657247946
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.71856394
Short name T202
Test name
Test status
Simulation time 174134365419 ps
CPU time 222.04 seconds
Started Jan 17 01:04:02 PM PST 24
Finished Jan 17 01:07:45 PM PST 24
Peak memory 200864 kb
Host smart-9914fe10-f123-4908-94ed-4e95a2150e20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71856394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_w
akeup.71856394
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3810377277
Short name T124
Test name
Test status
Simulation time 336711739781 ps
CPU time 71.1 seconds
Started Jan 17 01:04:04 PM PST 24
Finished Jan 17 01:05:16 PM PST 24
Peak memory 200820 kb
Host smart-e680e64a-9c39-4313-96cf-6b5d597198fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810377277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3810377277
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.219911057
Short name T141
Test name
Test status
Simulation time 122158903349 ps
CPU time 509.71 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:12:40 PM PST 24
Peak memory 201288 kb
Host smart-00afa9af-14d1-4f6d-8d8c-98a87756780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219911057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.219911057
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3960214899
Short name T679
Test name
Test status
Simulation time 28631252552 ps
CPU time 16.35 seconds
Started Jan 17 01:04:07 PM PST 24
Finished Jan 17 01:04:27 PM PST 24
Peak memory 200640 kb
Host smart-7959b252-3595-4185-8eec-cd09915411fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960214899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3960214899
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.383442627
Short name T438
Test name
Test status
Simulation time 4106819255 ps
CPU time 9.89 seconds
Started Jan 17 01:04:08 PM PST 24
Finished Jan 17 01:04:20 PM PST 24
Peak memory 200732 kb
Host smart-97575560-43bf-47b0-a267-1863863a71ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383442627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.383442627
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.4023713158
Short name T783
Test name
Test status
Simulation time 5720417970 ps
CPU time 4.44 seconds
Started Jan 17 01:04:11 PM PST 24
Finished Jan 17 01:04:16 PM PST 24
Peak memory 200676 kb
Host smart-b72f4863-cd64-4558-a9ee-575785a550cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023713158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.4023713158
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.144818917
Short name T263
Test name
Test status
Simulation time 29061878242 ps
CPU time 84.39 seconds
Started Jan 17 01:04:12 PM PST 24
Finished Jan 17 01:05:36 PM PST 24
Peak memory 216800 kb
Host smart-696502c8-d935-4b87-8692-4d4f35bc4c0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144818917 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.144818917
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.771187939
Short name T462
Test name
Test status
Simulation time 563658616 ps
CPU time 0.75 seconds
Started Jan 17 01:04:24 PM PST 24
Finished Jan 17 01:04:26 PM PST 24
Peak memory 200700 kb
Host smart-a467be30-1b49-495d-95ee-d38cd8630ebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771187939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.771187939
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1259572989
Short name T736
Test name
Test status
Simulation time 498063471668 ps
CPU time 561.9 seconds
Started Jan 17 01:04:19 PM PST 24
Finished Jan 17 01:13:41 PM PST 24
Peak memory 200996 kb
Host smart-74c6d0f1-1f4b-48a1-abe0-1c0835b267a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259572989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1259572989
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1905034532
Short name T215
Test name
Test status
Simulation time 327077727504 ps
CPU time 724.66 seconds
Started Jan 17 01:04:21 PM PST 24
Finished Jan 17 01:16:26 PM PST 24
Peak memory 200916 kb
Host smart-30d3d2d3-3a2d-4177-8262-0b816f999585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905034532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1905034532
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2128950664
Short name T803
Test name
Test status
Simulation time 164415163288 ps
CPU time 180.76 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:07:19 PM PST 24
Peak memory 200868 kb
Host smart-170c858e-a725-4c0f-bee7-fa54b723117c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128950664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2128950664
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1630839622
Short name T729
Test name
Test status
Simulation time 491949297863 ps
CPU time 1168.72 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:23:46 PM PST 24
Peak memory 200876 kb
Host smart-267b6021-c08c-405e-bcfb-f68b0b016842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630839622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1630839622
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2326980565
Short name T153
Test name
Test status
Simulation time 334483903910 ps
CPU time 809.77 seconds
Started Jan 17 01:04:16 PM PST 24
Finished Jan 17 01:17:46 PM PST 24
Peak memory 200868 kb
Host smart-e5008d56-f141-46a5-9794-d41ce34579e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326980565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2326980565
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2279780703
Short name T248
Test name
Test status
Simulation time 348789899714 ps
CPU time 212.94 seconds
Started Jan 17 01:04:22 PM PST 24
Finished Jan 17 01:07:56 PM PST 24
Peak memory 200876 kb
Host smart-887166ca-3adb-4b7d-8cf9-4c2710e4c2db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279780703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2279780703
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3248092699
Short name T743
Test name
Test status
Simulation time 166927070322 ps
CPU time 72.82 seconds
Started Jan 17 01:04:15 PM PST 24
Finished Jan 17 01:05:28 PM PST 24
Peak memory 200872 kb
Host smart-20fe08d7-eab5-427d-b83c-09e89047ff68
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248092699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3248092699
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3782473796
Short name T551
Test name
Test status
Simulation time 81318336140 ps
CPU time 265.96 seconds
Started Jan 17 01:04:18 PM PST 24
Finished Jan 17 01:08:44 PM PST 24
Peak memory 201376 kb
Host smart-0ee1592b-a700-4e2b-89b3-098c02ddf3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782473796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3782473796
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.637419310
Short name T819
Test name
Test status
Simulation time 38209651897 ps
CPU time 24.52 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:04:43 PM PST 24
Peak memory 200728 kb
Host smart-91ea4b09-e73a-41a1-8158-341d4071b08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637419310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.637419310
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1928539830
Short name T701
Test name
Test status
Simulation time 3566026812 ps
CPU time 8.77 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:04:26 PM PST 24
Peak memory 200748 kb
Host smart-83e70333-d53f-487d-aace-d2b6f27b19fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928539830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1928539830
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.371963186
Short name T498
Test name
Test status
Simulation time 5869392198 ps
CPU time 8.01 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:04:26 PM PST 24
Peak memory 200724 kb
Host smart-98f3f404-c0a7-4f6a-8fec-4816a78aa7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371963186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.371963186
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1272599957
Short name T214
Test name
Test status
Simulation time 46609475785 ps
CPU time 115.13 seconds
Started Jan 17 01:04:21 PM PST 24
Finished Jan 17 01:06:17 PM PST 24
Peak memory 209680 kb
Host smart-9be7a7a9-8fa8-47f1-b52a-59817c0b0e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272599957 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1272599957
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1150290044
Short name T467
Test name
Test status
Simulation time 436596132 ps
CPU time 0.9 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:04:18 PM PST 24
Peak memory 200528 kb
Host smart-780f4cea-fe82-4c6a-a605-db73172efb85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150290044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1150290044
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3383077438
Short name T599
Test name
Test status
Simulation time 165308192505 ps
CPU time 91.09 seconds
Started Jan 17 01:04:21 PM PST 24
Finished Jan 17 01:05:52 PM PST 24
Peak memory 200908 kb
Host smart-b051a9fa-5cb1-47cc-a296-1d86fd3d8582
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383077438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3383077438
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3044551893
Short name T102
Test name
Test status
Simulation time 327851787158 ps
CPU time 376.72 seconds
Started Jan 17 01:04:19 PM PST 24
Finished Jan 17 01:10:36 PM PST 24
Peak memory 200936 kb
Host smart-d85e1e23-3b36-49eb-b39e-18e20ff91fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044551893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3044551893
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.499971738
Short name T655
Test name
Test status
Simulation time 335833473450 ps
CPU time 399.65 seconds
Started Jan 17 01:04:20 PM PST 24
Finished Jan 17 01:11:00 PM PST 24
Peak memory 200916 kb
Host smart-c88901b7-e95e-4dd8-be70-1009923824b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=499971738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.499971738
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1351551741
Short name T132
Test name
Test status
Simulation time 489274140292 ps
CPU time 144.23 seconds
Started Jan 17 01:04:23 PM PST 24
Finished Jan 17 01:06:48 PM PST 24
Peak memory 201020 kb
Host smart-4c735445-4c63-4caa-8006-5ee81131c895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351551741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1351551741
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2284944910
Short name T154
Test name
Test status
Simulation time 497932067799 ps
CPU time 294.12 seconds
Started Jan 17 01:04:18 PM PST 24
Finished Jan 17 01:09:13 PM PST 24
Peak memory 200860 kb
Host smart-9bc3561b-fc19-4fa2-b77d-78e787d93710
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284944910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2284944910
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.106574146
Short name T627
Test name
Test status
Simulation time 165553186755 ps
CPU time 47.23 seconds
Started Jan 17 01:04:23 PM PST 24
Finished Jan 17 01:05:10 PM PST 24
Peak memory 200880 kb
Host smart-48dc2871-4ca3-4c52-ab78-3cb91818fde3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106574146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.106574146
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2909312766
Short name T418
Test name
Test status
Simulation time 325153453830 ps
CPU time 770.67 seconds
Started Jan 17 01:04:23 PM PST 24
Finished Jan 17 01:17:14 PM PST 24
Peak memory 200972 kb
Host smart-a9d73a20-27d7-45b3-b42c-8148cc41b24c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909312766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2909312766
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3963379127
Short name T802
Test name
Test status
Simulation time 38729946153 ps
CPU time 85.42 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:05:43 PM PST 24
Peak memory 200728 kb
Host smart-5dbd563a-7f3d-493c-a8fc-b74b786430aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963379127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3963379127
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.337011864
Short name T456
Test name
Test status
Simulation time 4558265988 ps
CPU time 2.85 seconds
Started Jan 17 01:04:15 PM PST 24
Finished Jan 17 01:04:19 PM PST 24
Peak memory 200752 kb
Host smart-0a76fe6d-02d5-440a-9e74-04646b5e7265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337011864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.337011864
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2659281687
Short name T532
Test name
Test status
Simulation time 5734638363 ps
CPU time 4.67 seconds
Started Jan 17 01:04:16 PM PST 24
Finished Jan 17 01:04:21 PM PST 24
Peak memory 200660 kb
Host smart-ba00a92d-10e8-417f-bed6-c80e5a3c1099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659281687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2659281687
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2227514533
Short name T546
Test name
Test status
Simulation time 455405642030 ps
CPU time 550.62 seconds
Started Jan 17 01:04:20 PM PST 24
Finished Jan 17 01:13:31 PM PST 24
Peak memory 201236 kb
Host smart-d94feffc-5020-419f-a7dc-f364801acf20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227514533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2227514533
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.501359301
Short name T690
Test name
Test status
Simulation time 188573114277 ps
CPU time 104.25 seconds
Started Jan 17 01:04:25 PM PST 24
Finished Jan 17 01:06:12 PM PST 24
Peak memory 209268 kb
Host smart-4bcc41e9-3937-4436-8d9d-b6f20fce3a65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501359301 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.501359301
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.372018304
Short name T577
Test name
Test status
Simulation time 322262444 ps
CPU time 0.96 seconds
Started Jan 17 01:04:28 PM PST 24
Finished Jan 17 01:04:30 PM PST 24
Peak memory 200892 kb
Host smart-b1a55a1f-ed3f-411e-a76b-92a2cd79b062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372018304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.372018304
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1244964669
Short name T36
Test name
Test status
Simulation time 325023429555 ps
CPU time 274.2 seconds
Started Jan 17 01:04:16 PM PST 24
Finished Jan 17 01:08:50 PM PST 24
Peak memory 200928 kb
Host smart-3f0a8575-a987-44b7-84b5-6f4f73af782a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244964669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1244964669
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3350221821
Short name T273
Test name
Test status
Simulation time 164848414943 ps
CPU time 98.75 seconds
Started Jan 17 01:04:16 PM PST 24
Finished Jan 17 01:05:55 PM PST 24
Peak memory 200860 kb
Host smart-1e8bb800-48ed-465a-8300-777bd00ed35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350221821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3350221821
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1685942119
Short name T689
Test name
Test status
Simulation time 329327557481 ps
CPU time 766.64 seconds
Started Jan 17 01:04:22 PM PST 24
Finished Jan 17 01:17:09 PM PST 24
Peak memory 200864 kb
Host smart-83ca3feb-b80b-458b-8679-4d851177b358
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685942119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1685942119
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.842749133
Short name T618
Test name
Test status
Simulation time 324206431193 ps
CPU time 182.89 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:07:21 PM PST 24
Peak memory 200828 kb
Host smart-6e5b642c-adb9-4ca9-8c57-77ce11be7245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842749133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.842749133
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.415885109
Short name T581
Test name
Test status
Simulation time 497861068745 ps
CPU time 1218.08 seconds
Started Jan 17 01:04:15 PM PST 24
Finished Jan 17 01:24:34 PM PST 24
Peak memory 200876 kb
Host smart-7dd9aaa7-1774-493d-9178-f79a744b045e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=415885109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.415885109
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2285339741
Short name T417
Test name
Test status
Simulation time 165215481944 ps
CPU time 386.87 seconds
Started Jan 17 01:04:20 PM PST 24
Finished Jan 17 01:10:48 PM PST 24
Peak memory 200912 kb
Host smart-51ac2aca-c4bc-4c77-8244-0ef371aca029
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285339741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2285339741
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1865862028
Short name T184
Test name
Test status
Simulation time 123044106724 ps
CPU time 654.46 seconds
Started Jan 17 01:04:18 PM PST 24
Finished Jan 17 01:15:13 PM PST 24
Peak memory 201320 kb
Host smart-f38b92ed-c276-4b5e-afc9-c0261f1c2e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865862028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1865862028
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2116368763
Short name T41
Test name
Test status
Simulation time 39411693749 ps
CPU time 13.95 seconds
Started Jan 17 01:04:16 PM PST 24
Finished Jan 17 01:04:31 PM PST 24
Peak memory 200688 kb
Host smart-e2ede15f-78ce-4579-a6f3-c661222f31ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116368763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2116368763
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.984549362
Short name T703
Test name
Test status
Simulation time 5259345394 ps
CPU time 2.99 seconds
Started Jan 17 01:04:18 PM PST 24
Finished Jan 17 01:04:21 PM PST 24
Peak memory 200704 kb
Host smart-5b31dfb6-1116-4043-af2e-c7783e1e9153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984549362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.984549362
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2825646881
Short name T610
Test name
Test status
Simulation time 6103763499 ps
CPU time 4.36 seconds
Started Jan 17 01:04:16 PM PST 24
Finished Jan 17 01:04:21 PM PST 24
Peak memory 200708 kb
Host smart-b7fd69e6-7477-4137-8fa3-67dbe70faecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825646881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2825646881
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1345064029
Short name T763
Test name
Test status
Simulation time 95929305159 ps
CPU time 354.75 seconds
Started Jan 17 01:04:26 PM PST 24
Finished Jan 17 01:10:23 PM PST 24
Peak memory 201332 kb
Host smart-676e688e-1339-4b74-a011-9f8ada6cdc59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345064029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1345064029
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3325511513
Short name T567
Test name
Test status
Simulation time 136224391353 ps
CPU time 80.5 seconds
Started Jan 17 01:04:17 PM PST 24
Finished Jan 17 01:05:38 PM PST 24
Peak memory 209604 kb
Host smart-b59438b4-90de-4c82-aa45-061bbdcd8321
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325511513 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3325511513
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3750718423
Short name T484
Test name
Test status
Simulation time 333630040 ps
CPU time 0.8 seconds
Started Jan 17 01:04:33 PM PST 24
Finished Jan 17 01:04:37 PM PST 24
Peak memory 200668 kb
Host smart-bacc369b-9a5e-439d-a3a8-39d64191db06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750718423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3750718423
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.4211384012
Short name T626
Test name
Test status
Simulation time 350768460620 ps
CPU time 379.56 seconds
Started Jan 17 01:04:25 PM PST 24
Finished Jan 17 01:10:47 PM PST 24
Peak memory 200812 kb
Host smart-7ab811f1-404b-4218-ac1c-1c38a8859023
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211384012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.4211384012
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1701688509
Short name T295
Test name
Test status
Simulation time 492545854276 ps
CPU time 1156.09 seconds
Started Jan 17 01:04:26 PM PST 24
Finished Jan 17 01:23:45 PM PST 24
Peak memory 200988 kb
Host smart-5f67ad40-bd4e-4c51-9ddc-306e896e7dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701688509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1701688509
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.132472002
Short name T155
Test name
Test status
Simulation time 164421711964 ps
CPU time 97.71 seconds
Started Jan 17 01:04:32 PM PST 24
Finished Jan 17 01:06:13 PM PST 24
Peak memory 200884 kb
Host smart-70e2ddec-5909-41e1-8d97-b117d79e0bf9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=132472002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.132472002
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3819233353
Short name T831
Test name
Test status
Simulation time 493481840179 ps
CPU time 116.81 seconds
Started Jan 17 01:04:28 PM PST 24
Finished Jan 17 01:06:26 PM PST 24
Peak memory 200956 kb
Host smart-6b8ce72e-49d1-453c-bf79-3434a4770bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819233353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3819233353
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3727743959
Short name T660
Test name
Test status
Simulation time 494867008484 ps
CPU time 1074.05 seconds
Started Jan 17 01:04:28 PM PST 24
Finished Jan 17 01:22:23 PM PST 24
Peak memory 200920 kb
Host smart-8a5076d6-8e2e-4757-8ee6-0456a151a91e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727743959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3727743959
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2925680654
Short name T289
Test name
Test status
Simulation time 169176328490 ps
CPU time 367.7 seconds
Started Jan 17 01:04:29 PM PST 24
Finished Jan 17 01:10:43 PM PST 24
Peak memory 200948 kb
Host smart-51e5a93a-2059-432b-9503-1e3c2bdb638b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925680654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2925680654
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.4278471627
Short name T510
Test name
Test status
Simulation time 317364554647 ps
CPU time 116.76 seconds
Started Jan 17 01:04:31 PM PST 24
Finished Jan 17 01:06:33 PM PST 24
Peak memory 200804 kb
Host smart-b564a8a8-2072-435d-bda4-4fa522273d84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278471627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.4278471627
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3807498785
Short name T722
Test name
Test status
Simulation time 80140689109 ps
CPU time 288.25 seconds
Started Jan 17 01:04:32 PM PST 24
Finished Jan 17 01:09:24 PM PST 24
Peak memory 201388 kb
Host smart-499984ff-0701-4c2a-a4c8-788f35a8031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807498785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3807498785
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.520656751
Short name T540
Test name
Test status
Simulation time 46275225943 ps
CPU time 54.45 seconds
Started Jan 17 01:04:27 PM PST 24
Finished Jan 17 01:05:23 PM PST 24
Peak memory 200732 kb
Host smart-a9d43d92-5e6f-49cb-be3c-7be0f8545abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520656751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.520656751
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1145102034
Short name T583
Test name
Test status
Simulation time 2828083135 ps
CPU time 6.72 seconds
Started Jan 17 01:04:26 PM PST 24
Finished Jan 17 01:04:35 PM PST 24
Peak memory 200724 kb
Host smart-18b60585-d85a-4e1f-b9b4-3d1e7620855d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145102034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1145102034
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3389822125
Short name T595
Test name
Test status
Simulation time 6134679745 ps
CPU time 7.54 seconds
Started Jan 17 01:04:27 PM PST 24
Finished Jan 17 01:04:36 PM PST 24
Peak memory 200608 kb
Host smart-9202ce0c-e6a6-4ea1-bcff-273465423e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389822125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3389822125
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2878516446
Short name T678
Test name
Test status
Simulation time 358309672787 ps
CPU time 841.24 seconds
Started Jan 17 01:04:29 PM PST 24
Finished Jan 17 01:18:31 PM PST 24
Peak memory 200868 kb
Host smart-9e61acb1-f455-4ab8-a968-dfcf205b8dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878516446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2878516446
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.649904388
Short name T693
Test name
Test status
Simulation time 46430520094 ps
CPU time 144.58 seconds
Started Jan 17 01:04:30 PM PST 24
Finished Jan 17 01:07:00 PM PST 24
Peak memory 217680 kb
Host smart-458b8b55-3caf-4874-85f0-f72544e29593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649904388 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.649904388
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3350910795
Short name T642
Test name
Test status
Simulation time 444782172 ps
CPU time 1.65 seconds
Started Jan 17 01:04:35 PM PST 24
Finished Jan 17 01:04:38 PM PST 24
Peak memory 200604 kb
Host smart-5f2df4de-374c-4aa6-846b-0e0ff9642fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350910795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3350910795
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2871477509
Short name T325
Test name
Test status
Simulation time 329430608397 ps
CPU time 192.35 seconds
Started Jan 17 01:04:43 PM PST 24
Finished Jan 17 01:07:56 PM PST 24
Peak memory 201168 kb
Host smart-ea1e0063-1275-4a37-b0b1-f840154d0697
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871477509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2871477509
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3736322960
Short name T488
Test name
Test status
Simulation time 160361116086 ps
CPU time 370.03 seconds
Started Jan 17 01:04:39 PM PST 24
Finished Jan 17 01:10:50 PM PST 24
Peak memory 200876 kb
Host smart-5a0e8df9-44d1-4ec1-b48f-c49e5abdcc66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736322960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3736322960
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3041017469
Short name T548
Test name
Test status
Simulation time 491304319256 ps
CPU time 303.18 seconds
Started Jan 17 01:04:35 PM PST 24
Finished Jan 17 01:09:39 PM PST 24
Peak memory 200876 kb
Host smart-20234089-f369-4a48-9321-5a12d2c79345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041017469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3041017469
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3674837315
Short name T725
Test name
Test status
Simulation time 490139515949 ps
CPU time 283.21 seconds
Started Jan 17 01:04:41 PM PST 24
Finished Jan 17 01:09:24 PM PST 24
Peak memory 200784 kb
Host smart-7a0e45ac-38cf-475b-8bc6-fc7e450f944c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674837315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3674837315
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1335855958
Short name T129
Test name
Test status
Simulation time 488454310939 ps
CPU time 308.97 seconds
Started Jan 17 01:04:34 PM PST 24
Finished Jan 17 01:09:45 PM PST 24
Peak memory 200888 kb
Host smart-b29b0843-6aad-4b35-b5d9-5e7e88d1a8b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335855958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1335855958
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.404998942
Short name T648
Test name
Test status
Simulation time 504577789029 ps
CPU time 169.3 seconds
Started Jan 17 01:04:35 PM PST 24
Finished Jan 17 01:07:26 PM PST 24
Peak memory 200736 kb
Host smart-c658f892-fdb7-4809-87ec-60b0297d868f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404998942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.404998942
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1884770067
Short name T193
Test name
Test status
Simulation time 90746514224 ps
CPU time 471.17 seconds
Started Jan 17 01:04:35 PM PST 24
Finished Jan 17 01:12:27 PM PST 24
Peak memory 201320 kb
Host smart-94b26212-139c-4348-9050-7b1dd16be512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884770067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1884770067
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3354988233
Short name T448
Test name
Test status
Simulation time 30311595767 ps
CPU time 73.11 seconds
Started Jan 17 01:04:49 PM PST 24
Finished Jan 17 01:06:04 PM PST 24
Peak memory 200560 kb
Host smart-8775232e-9496-447d-b840-45d7ec47f938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354988233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3354988233
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3988778727
Short name T793
Test name
Test status
Simulation time 3022313619 ps
CPU time 1.5 seconds
Started Jan 17 01:04:34 PM PST 24
Finished Jan 17 01:04:37 PM PST 24
Peak memory 200708 kb
Host smart-c2cc2c34-03fc-4e7d-8922-8bb61d8e7934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988778727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3988778727
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.934846078
Short name T671
Test name
Test status
Simulation time 5720133617 ps
CPU time 14.73 seconds
Started Jan 17 01:04:27 PM PST 24
Finished Jan 17 01:04:44 PM PST 24
Peak memory 200936 kb
Host smart-e89d140f-8bcc-4ae6-b3bd-4f36af6239ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934846078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.934846078
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2201787457
Short name T280
Test name
Test status
Simulation time 70543226825 ps
CPU time 119.82 seconds
Started Jan 17 01:04:41 PM PST 24
Finished Jan 17 01:06:42 PM PST 24
Peak memory 217696 kb
Host smart-b1df7163-b196-437f-a8d8-2bf42516f06e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201787457 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2201787457
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.293442678
Short name T588
Test name
Test status
Simulation time 488396832 ps
CPU time 1.75 seconds
Started Jan 17 01:04:44 PM PST 24
Finished Jan 17 01:04:46 PM PST 24
Peak memory 200652 kb
Host smart-0b9c9339-43ab-46b6-bfb7-5f2ad4db7d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293442678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.293442678
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1484404279
Short name T269
Test name
Test status
Simulation time 170517814749 ps
CPU time 107.47 seconds
Started Jan 17 01:04:41 PM PST 24
Finished Jan 17 01:06:29 PM PST 24
Peak memory 200924 kb
Host smart-6698da74-5838-447f-80bb-a0181ea9eb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484404279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1484404279
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1544558326
Short name T317
Test name
Test status
Simulation time 494858884749 ps
CPU time 547.35 seconds
Started Jan 17 01:04:41 PM PST 24
Finished Jan 17 01:13:49 PM PST 24
Peak memory 200932 kb
Host smart-59d2115c-a65b-4859-bca1-b6250c2d2518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544558326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1544558326
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3295247811
Short name T654
Test name
Test status
Simulation time 325376735137 ps
CPU time 196.12 seconds
Started Jan 17 01:04:40 PM PST 24
Finished Jan 17 01:07:56 PM PST 24
Peak memory 200868 kb
Host smart-8277afdb-9abd-48b3-ab69-9f67a3ac75ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295247811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3295247811
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1628858186
Short name T288
Test name
Test status
Simulation time 338645534370 ps
CPU time 186.78 seconds
Started Jan 17 01:04:33 PM PST 24
Finished Jan 17 01:07:43 PM PST 24
Peak memory 200792 kb
Host smart-002b579c-19fa-4187-92f7-b2b85be3a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628858186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1628858186
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1798446817
Short name T730
Test name
Test status
Simulation time 491606632960 ps
CPU time 595.84 seconds
Started Jan 17 01:04:36 PM PST 24
Finished Jan 17 01:14:32 PM PST 24
Peak memory 200924 kb
Host smart-384ba667-b210-4c15-8f03-fe9d3df2672d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798446817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1798446817
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.418588297
Short name T731
Test name
Test status
Simulation time 330533601996 ps
CPU time 223.32 seconds
Started Jan 17 01:04:41 PM PST 24
Finished Jan 17 01:08:25 PM PST 24
Peak memory 200868 kb
Host smart-97234d21-b679-4480-8fdb-4aea873b9428
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418588297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.418588297
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.748424916
Short name T806
Test name
Test status
Simulation time 332062309035 ps
CPU time 710.15 seconds
Started Jan 17 01:04:43 PM PST 24
Finished Jan 17 01:16:34 PM PST 24
Peak memory 200824 kb
Host smart-509c0ce8-e58e-4011-a4cb-342703989483
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748424916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.748424916
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2391691739
Short name T337
Test name
Test status
Simulation time 120376354237 ps
CPU time 663.51 seconds
Started Jan 17 01:04:40 PM PST 24
Finished Jan 17 01:15:44 PM PST 24
Peak memory 201308 kb
Host smart-82c97636-5d75-4649-aa30-8a5bbf7f669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391691739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2391691739
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1878070727
Short name T712
Test name
Test status
Simulation time 38684169268 ps
CPU time 91.58 seconds
Started Jan 17 01:04:42 PM PST 24
Finished Jan 17 01:06:14 PM PST 24
Peak memory 200676 kb
Host smart-a5d20948-1088-4e18-8d2a-3112fb7bba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878070727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1878070727
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1959648009
Short name T649
Test name
Test status
Simulation time 5171485205 ps
CPU time 6.67 seconds
Started Jan 17 01:04:47 PM PST 24
Finished Jan 17 01:04:54 PM PST 24
Peak memory 200688 kb
Host smart-1dbdc6e3-83b7-471b-bb71-d6fa1a6f8078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959648009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1959648009
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.747377723
Short name T497
Test name
Test status
Simulation time 5685640400 ps
CPU time 7.29 seconds
Started Jan 17 01:04:36 PM PST 24
Finished Jan 17 01:04:44 PM PST 24
Peak memory 200708 kb
Host smart-2a96bbc9-45de-43ba-bc7d-4661dbc19d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747377723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.747377723
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1512671298
Short name T327
Test name
Test status
Simulation time 458500122592 ps
CPU time 1482.35 seconds
Started Jan 17 01:04:47 PM PST 24
Finished Jan 17 01:29:30 PM PST 24
Peak memory 201160 kb
Host smart-401befcb-d127-4608-8c09-fb7aae1486f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512671298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1512671298
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1663526123
Short name T492
Test name
Test status
Simulation time 61947582752 ps
CPU time 57.93 seconds
Started Jan 17 01:04:41 PM PST 24
Finished Jan 17 01:05:40 PM PST 24
Peak memory 209576 kb
Host smart-8b4c4572-d815-4815-bb9a-c4f7c8fea6a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663526123 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1663526123
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.916904768
Short name T645
Test name
Test status
Simulation time 492233250 ps
CPU time 1.14 seconds
Started Jan 17 01:04:55 PM PST 24
Finished Jan 17 01:05:00 PM PST 24
Peak memory 200064 kb
Host smart-c3a89b8c-fb44-454a-abab-2d2fe61bbf06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916904768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.916904768
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.198501070
Short name T261
Test name
Test status
Simulation time 163743503649 ps
CPU time 209.18 seconds
Started Jan 17 01:04:53 PM PST 24
Finished Jan 17 01:08:28 PM PST 24
Peak memory 200904 kb
Host smart-26dbe5d0-7e9b-4fa7-a04b-0aa9a25428f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198501070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.198501070
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1502548767
Short name T425
Test name
Test status
Simulation time 334909386038 ps
CPU time 806.25 seconds
Started Jan 17 01:04:50 PM PST 24
Finished Jan 17 01:18:17 PM PST 24
Peak memory 200880 kb
Host smart-3cf3f89f-ba2b-4b5c-b9ec-3b6bac7cd3ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502548767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1502548767
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.9675174
Short name T513
Test name
Test status
Simulation time 482998072183 ps
CPU time 465.16 seconds
Started Jan 17 01:04:49 PM PST 24
Finished Jan 17 01:12:36 PM PST 24
Peak memory 200752 kb
Host smart-317bd684-bae4-44b4-ba18-b996adb2f1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9675174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.9675174
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1451617379
Short name T853
Test name
Test status
Simulation time 490939075403 ps
CPU time 269.81 seconds
Started Jan 17 01:04:44 PM PST 24
Finished Jan 17 01:09:14 PM PST 24
Peak memory 200840 kb
Host smart-629bfe77-55c5-4d72-9048-0cfec303cf66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451617379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1451617379
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1258698831
Short name T199
Test name
Test status
Simulation time 327579617500 ps
CPU time 370.3 seconds
Started Jan 17 01:04:51 PM PST 24
Finished Jan 17 01:11:02 PM PST 24
Peak memory 200900 kb
Host smart-fdae5e67-de0d-4d19-a27d-548ef8d4b3d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258698831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1258698831
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2702767961
Short name T111
Test name
Test status
Simulation time 331565404706 ps
CPU time 130.55 seconds
Started Jan 17 01:04:53 PM PST 24
Finished Jan 17 01:07:09 PM PST 24
Peak memory 200848 kb
Host smart-ef94e6b6-038b-4ce4-96e6-f45fa0b1677a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702767961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2702767961
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1072480947
Short name T176
Test name
Test status
Simulation time 107326148376 ps
CPU time 542.11 seconds
Started Jan 17 01:04:52 PM PST 24
Finished Jan 17 01:14:01 PM PST 24
Peak memory 201284 kb
Host smart-4aa57c2f-326b-4750-88e9-35e0824528d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072480947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1072480947
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.973191823
Short name T824
Test name
Test status
Simulation time 28370325841 ps
CPU time 15.28 seconds
Started Jan 17 01:04:51 PM PST 24
Finished Jan 17 01:05:07 PM PST 24
Peak memory 200708 kb
Host smart-637442a1-f069-4b99-afc1-845c193791e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973191823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.973191823
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3684024830
Short name T723
Test name
Test status
Simulation time 3060281409 ps
CPU time 7.28 seconds
Started Jan 17 01:04:49 PM PST 24
Finished Jan 17 01:04:57 PM PST 24
Peak memory 200720 kb
Host smart-47a1d95b-e381-4b42-8310-75338de31af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684024830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3684024830
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2229412082
Short name T430
Test name
Test status
Simulation time 5779105963 ps
CPU time 3.6 seconds
Started Jan 17 01:04:43 PM PST 24
Finished Jan 17 01:04:47 PM PST 24
Peak memory 200636 kb
Host smart-74d29628-4f8c-4ef5-b6c2-543d9a01117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229412082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2229412082
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3735368141
Short name T108
Test name
Test status
Simulation time 541432057100 ps
CPU time 299.86 seconds
Started Jan 17 01:04:50 PM PST 24
Finished Jan 17 01:09:51 PM PST 24
Peak memory 200912 kb
Host smart-f310acfa-8c1b-41d6-9467-016beb7c571b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735368141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3735368141
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.883996922
Short name T672
Test name
Test status
Simulation time 467449214 ps
CPU time 0.73 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:03:04 PM PST 24
Peak memory 200604 kb
Host smart-4051ef23-bedc-4acf-9656-3dc15e95530c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883996922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.883996922
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1578537274
Short name T282
Test name
Test status
Simulation time 166775921881 ps
CPU time 196.66 seconds
Started Jan 17 01:02:53 PM PST 24
Finished Jan 17 01:06:11 PM PST 24
Peak memory 200916 kb
Host smart-1c2ea30a-8418-44c8-b7d1-300df6ba498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578537274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1578537274
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1700282183
Short name T505
Test name
Test status
Simulation time 163431530468 ps
CPU time 34.11 seconds
Started Jan 17 01:02:53 PM PST 24
Finished Jan 17 01:03:28 PM PST 24
Peak memory 200868 kb
Host smart-ebf5ce9c-72b5-41fa-8e1e-1d6d6124c89b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700282183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1700282183
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.496264771
Short name T623
Test name
Test status
Simulation time 165020351834 ps
CPU time 374.61 seconds
Started Jan 17 01:03:01 PM PST 24
Finished Jan 17 01:09:19 PM PST 24
Peak memory 200992 kb
Host smart-62092cdd-5705-4de7-b635-24e58cd072dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496264771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.496264771
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1633452054
Short name T534
Test name
Test status
Simulation time 491020178215 ps
CPU time 541.84 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:12:06 PM PST 24
Peak memory 200748 kb
Host smart-580ee674-6961-4d44-9742-1a79ed6604ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633452054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1633452054
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2106714806
Short name T496
Test name
Test status
Simulation time 161715982061 ps
CPU time 157.41 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:05:41 PM PST 24
Peak memory 200908 kb
Host smart-7e1d04e1-d33f-49bb-9270-ea661c32438c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106714806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2106714806
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1353529303
Short name T677
Test name
Test status
Simulation time 486018007624 ps
CPU time 274.67 seconds
Started Jan 17 01:02:54 PM PST 24
Finished Jan 17 01:07:29 PM PST 24
Peak memory 200876 kb
Host smart-9e444199-ed85-4814-b291-842051499921
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353529303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1353529303
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1556918418
Short name T188
Test name
Test status
Simulation time 72984651786 ps
CPU time 272.94 seconds
Started Jan 17 01:02:54 PM PST 24
Finished Jan 17 01:07:28 PM PST 24
Peak memory 201300 kb
Host smart-882bcf23-523c-4314-91a0-0211c0925e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556918418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1556918418
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.514655334
Short name T401
Test name
Test status
Simulation time 36664185873 ps
CPU time 23.09 seconds
Started Jan 17 01:02:56 PM PST 24
Finished Jan 17 01:03:20 PM PST 24
Peak memory 200688 kb
Host smart-d7c1b138-5bae-4b23-9115-44dbdc12b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514655334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.514655334
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3649181565
Short name T681
Test name
Test status
Simulation time 3642273898 ps
CPU time 2.95 seconds
Started Jan 17 01:02:55 PM PST 24
Finished Jan 17 01:02:59 PM PST 24
Peak memory 200692 kb
Host smart-4af4940a-b747-4b61-bcaf-122dbec45844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649181565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3649181565
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2252293901
Short name T51
Test name
Test status
Simulation time 8131725151 ps
CPU time 20.35 seconds
Started Jan 17 01:02:52 PM PST 24
Finished Jan 17 01:03:13 PM PST 24
Peak memory 217252 kb
Host smart-24fed24a-d189-4fb8-8da3-b7bde05866ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252293901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2252293901
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1847638339
Short name T88
Test name
Test status
Simulation time 5559599452 ps
CPU time 14.82 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:03:19 PM PST 24
Peak memory 200528 kb
Host smart-94a59561-2086-4780-9d1d-259a7c9f20f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847638339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1847638339
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.569098869
Short name T776
Test name
Test status
Simulation time 117131540170 ps
CPU time 126.52 seconds
Started Jan 17 01:02:58 PM PST 24
Finished Jan 17 01:05:05 PM PST 24
Peak memory 209576 kb
Host smart-5865cfb8-d7d8-412b-9950-c090df38c4ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569098869 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.569098869
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3774138123
Short name T818
Test name
Test status
Simulation time 312146141 ps
CPU time 1.33 seconds
Started Jan 17 01:05:06 PM PST 24
Finished Jan 17 01:05:08 PM PST 24
Peak memory 200652 kb
Host smart-cb13c637-f203-47a3-ac25-dd57fc78c4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774138123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3774138123
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3128693258
Short name T133
Test name
Test status
Simulation time 328908915728 ps
CPU time 177.38 seconds
Started Jan 17 01:04:49 PM PST 24
Finished Jan 17 01:07:48 PM PST 24
Peak memory 200924 kb
Host smart-aabe85b3-2292-4b5b-9dec-2a9350816a77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128693258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3128693258
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1105850255
Short name T777
Test name
Test status
Simulation time 336591357863 ps
CPU time 757.61 seconds
Started Jan 17 01:04:52 PM PST 24
Finished Jan 17 01:17:36 PM PST 24
Peak memory 200904 kb
Host smart-aa4b1e9a-cd3c-44e5-89cc-c4d21b79afdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105850255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1105850255
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2528362012
Short name T229
Test name
Test status
Simulation time 163463733153 ps
CPU time 402.63 seconds
Started Jan 17 01:04:54 PM PST 24
Finished Jan 17 01:11:41 PM PST 24
Peak memory 200348 kb
Host smart-d8deff26-62f1-4aea-98b3-f9a4da282360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528362012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2528362012
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3395417158
Short name T434
Test name
Test status
Simulation time 499296198833 ps
CPU time 533.42 seconds
Started Jan 17 01:04:49 PM PST 24
Finished Jan 17 01:13:44 PM PST 24
Peak memory 200872 kb
Host smart-9f0fd461-02e0-4e10-9873-2b73e2339831
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395417158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3395417158
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1851937553
Short name T604
Test name
Test status
Simulation time 165627190655 ps
CPU time 98.55 seconds
Started Jan 17 01:04:54 PM PST 24
Finished Jan 17 01:06:37 PM PST 24
Peak memory 200340 kb
Host smart-53ffe052-6d66-45ae-b76c-c472c0b29826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851937553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1851937553
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2994155360
Short name T475
Test name
Test status
Simulation time 161848119895 ps
CPU time 192.01 seconds
Started Jan 17 01:04:51 PM PST 24
Finished Jan 17 01:08:04 PM PST 24
Peak memory 200924 kb
Host smart-5bc4a3b8-da54-450a-bd82-0f0a19a671f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994155360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2994155360
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3370434641
Short name T428
Test name
Test status
Simulation time 169378620251 ps
CPU time 184.87 seconds
Started Jan 17 01:04:54 PM PST 24
Finished Jan 17 01:08:03 PM PST 24
Peak memory 200796 kb
Host smart-fe3ae3c3-8a45-41be-b0ae-96b7090d7fe2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370434641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3370434641
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1090913677
Short name T529
Test name
Test status
Simulation time 126329441144 ps
CPU time 493.99 seconds
Started Jan 17 01:04:52 PM PST 24
Finished Jan 17 01:13:12 PM PST 24
Peak memory 201320 kb
Host smart-b446f62c-474a-41ef-b14e-0109091149ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090913677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1090913677
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4243824912
Short name T482
Test name
Test status
Simulation time 42676744624 ps
CPU time 24.87 seconds
Started Jan 17 01:04:54 PM PST 24
Finished Jan 17 01:05:23 PM PST 24
Peak memory 200652 kb
Host smart-7c2c13bb-a5a1-42b6-b433-e571aceaab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243824912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.4243824912
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2757177454
Short name T603
Test name
Test status
Simulation time 4841089344 ps
CPU time 3.69 seconds
Started Jan 17 01:04:52 PM PST 24
Finished Jan 17 01:05:01 PM PST 24
Peak memory 200728 kb
Host smart-6237bdec-db0b-42a7-a4f4-e4112785c5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757177454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2757177454
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.218599776
Short name T404
Test name
Test status
Simulation time 5840761058 ps
CPU time 15.89 seconds
Started Jan 17 01:04:52 PM PST 24
Finished Jan 17 01:05:14 PM PST 24
Peak memory 200624 kb
Host smart-addd90fb-2e35-48dc-8e45-2a9a909fa30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218599776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.218599776
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2641356097
Short name T609
Test name
Test status
Simulation time 38672997872 ps
CPU time 48.24 seconds
Started Jan 17 01:05:05 PM PST 24
Finished Jan 17 01:05:55 PM PST 24
Peak memory 200720 kb
Host smart-e57163a9-8b36-4293-bd9d-c035ed4fa29b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641356097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2641356097
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2231718542
Short name T517
Test name
Test status
Simulation time 369179648 ps
CPU time 0.77 seconds
Started Jan 17 01:05:08 PM PST 24
Finished Jan 17 01:05:10 PM PST 24
Peak memory 200668 kb
Host smart-c4d49dec-9bfa-4e30-b9a0-4687a24fc77d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231718542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2231718542
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.146958826
Short name T307
Test name
Test status
Simulation time 160374298450 ps
CPU time 73.11 seconds
Started Jan 17 01:05:04 PM PST 24
Finished Jan 17 01:06:19 PM PST 24
Peak memory 200832 kb
Host smart-e53b1b69-75f2-4385-98f4-62458921459a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146958826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.146958826
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3480137582
Short name T156
Test name
Test status
Simulation time 168056978329 ps
CPU time 199.78 seconds
Started Jan 17 01:05:04 PM PST 24
Finished Jan 17 01:08:26 PM PST 24
Peak memory 200940 kb
Host smart-bedeb05f-f399-4bf5-b67f-41345fce6832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480137582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3480137582
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.257534285
Short name T495
Test name
Test status
Simulation time 328990596523 ps
CPU time 174.4 seconds
Started Jan 17 01:05:05 PM PST 24
Finished Jan 17 01:08:01 PM PST 24
Peak memory 200876 kb
Host smart-168eb8ad-4ffa-4244-a679-25860d5a5b1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=257534285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.257534285
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2067983242
Short name T310
Test name
Test status
Simulation time 484210866748 ps
CPU time 315.6 seconds
Started Jan 17 01:05:04 PM PST 24
Finished Jan 17 01:10:22 PM PST 24
Peak memory 200892 kb
Host smart-6495e404-f1a9-4aff-a0a8-21c3dc9c7b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067983242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2067983242
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3892783645
Short name T580
Test name
Test status
Simulation time 326222205444 ps
CPU time 190.99 seconds
Started Jan 17 01:05:05 PM PST 24
Finished Jan 17 01:08:17 PM PST 24
Peak memory 200864 kb
Host smart-4119628b-8f48-491e-9b9d-827c893b6972
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892783645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3892783645
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3007008819
Short name T16
Test name
Test status
Simulation time 489344245633 ps
CPU time 995.89 seconds
Started Jan 17 01:05:09 PM PST 24
Finished Jan 17 01:21:45 PM PST 24
Peak memory 200760 kb
Host smart-b380eb85-f9d9-411c-80ad-5a9b84ad0eaa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007008819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3007008819
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2771500102
Short name T179
Test name
Test status
Simulation time 107765032296 ps
CPU time 345.35 seconds
Started Jan 17 01:05:05 PM PST 24
Finished Jan 17 01:10:52 PM PST 24
Peak memory 201364 kb
Host smart-93fc69bf-3acd-45ac-9302-2169f65bb6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771500102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2771500102
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1186169925
Short name T421
Test name
Test status
Simulation time 25562227536 ps
CPU time 30.38 seconds
Started Jan 17 01:05:07 PM PST 24
Finished Jan 17 01:05:38 PM PST 24
Peak memory 200676 kb
Host smart-be669e58-1c67-4143-809a-2305214416ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186169925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1186169925
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2061348775
Short name T630
Test name
Test status
Simulation time 3044998473 ps
CPU time 4.39 seconds
Started Jan 17 01:05:06 PM PST 24
Finished Jan 17 01:05:11 PM PST 24
Peak memory 200592 kb
Host smart-0ca3522f-8290-4da0-9596-fe88cfd9c963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061348775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2061348775
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1795593102
Short name T592
Test name
Test status
Simulation time 5892411862 ps
CPU time 4.26 seconds
Started Jan 17 01:05:04 PM PST 24
Finished Jan 17 01:05:10 PM PST 24
Peak memory 200744 kb
Host smart-181fb712-e48f-433e-95bf-aa6603b4a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795593102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1795593102
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.165870619
Short name T115
Test name
Test status
Simulation time 215496298019 ps
CPU time 255.89 seconds
Started Jan 17 01:05:16 PM PST 24
Finished Jan 17 01:09:32 PM PST 24
Peak memory 200900 kb
Host smart-fb84dde0-ae65-4bf3-b2ea-e71152e5e909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165870619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
165870619
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1750465651
Short name T709
Test name
Test status
Simulation time 441623842661 ps
CPU time 275.52 seconds
Started Jan 17 01:05:09 PM PST 24
Finished Jan 17 01:09:45 PM PST 24
Peak memory 209592 kb
Host smart-e4bdee64-45aa-4168-ba66-57a5476482e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750465651 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1750465651
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1750475479
Short name T786
Test name
Test status
Simulation time 491553027 ps
CPU time 1.76 seconds
Started Jan 17 01:05:19 PM PST 24
Finished Jan 17 01:05:22 PM PST 24
Peak memory 200632 kb
Host smart-25bfe2c4-d0e7-4aff-949e-1bce8b0ecbd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750475479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1750475479
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3717943241
Short name T283
Test name
Test status
Simulation time 322624966668 ps
CPU time 196.49 seconds
Started Jan 17 01:05:14 PM PST 24
Finished Jan 17 01:08:32 PM PST 24
Peak memory 200984 kb
Host smart-f20c3817-ba95-4b3b-85a5-98cbca27ca3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717943241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3717943241
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.190247383
Short name T216
Test name
Test status
Simulation time 168077469578 ps
CPU time 98.13 seconds
Started Jan 17 01:05:18 PM PST 24
Finished Jan 17 01:06:57 PM PST 24
Peak memory 200940 kb
Host smart-27065dbe-01ed-4f4d-bc99-23a0efe880d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190247383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.190247383
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3364508033
Short name T766
Test name
Test status
Simulation time 166757274995 ps
CPU time 39.72 seconds
Started Jan 17 01:05:18 PM PST 24
Finished Jan 17 01:05:58 PM PST 24
Peak memory 200912 kb
Host smart-0ca1cade-bb90-43fb-b7af-3763d118b3d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364508033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3364508033
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2555513005
Short name T522
Test name
Test status
Simulation time 492367168093 ps
CPU time 190.58 seconds
Started Jan 17 01:05:18 PM PST 24
Finished Jan 17 01:08:29 PM PST 24
Peak memory 201220 kb
Host smart-4c7ff3ca-759c-4229-800e-3b90afd4bd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555513005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2555513005
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1154706060
Short name T437
Test name
Test status
Simulation time 332353943454 ps
CPU time 394.14 seconds
Started Jan 17 01:05:15 PM PST 24
Finished Jan 17 01:11:50 PM PST 24
Peak memory 200864 kb
Host smart-589561cd-1b23-4a10-8f3b-cd2726b278fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154706060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1154706060
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1411078784
Short name T821
Test name
Test status
Simulation time 164200495970 ps
CPU time 95.93 seconds
Started Jan 17 01:05:07 PM PST 24
Finished Jan 17 01:06:44 PM PST 24
Peak memory 201008 kb
Host smart-853d0dcb-c9b2-45bb-9dc3-e0cfb29e4118
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411078784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1411078784
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4173510837
Short name T804
Test name
Test status
Simulation time 169264712227 ps
CPU time 375.77 seconds
Started Jan 17 01:05:16 PM PST 24
Finished Jan 17 01:11:33 PM PST 24
Peak memory 200932 kb
Host smart-0671f1fd-679c-4fd8-9269-9a2abd8c94cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173510837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4173510837
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.266756207
Short name T653
Test name
Test status
Simulation time 108529328014 ps
CPU time 537.42 seconds
Started Jan 17 01:05:10 PM PST 24
Finished Jan 17 01:14:08 PM PST 24
Peak memory 201548 kb
Host smart-64c3aa78-d022-437f-a438-faf4e2ee4ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266756207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.266756207
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3941785534
Short name T710
Test name
Test status
Simulation time 38663738605 ps
CPU time 86.7 seconds
Started Jan 17 01:05:21 PM PST 24
Finished Jan 17 01:06:49 PM PST 24
Peak memory 200704 kb
Host smart-74f1bb4d-92b2-4c2a-ab32-d3af37ca6c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941785534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3941785534
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3198643929
Short name T472
Test name
Test status
Simulation time 5483674119 ps
CPU time 13.57 seconds
Started Jan 17 01:05:17 PM PST 24
Finished Jan 17 01:05:31 PM PST 24
Peak memory 200964 kb
Host smart-df5e951a-6b14-4797-a8e8-c8580431f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198643929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3198643929
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1980872258
Short name T454
Test name
Test status
Simulation time 5772809180 ps
CPU time 14.07 seconds
Started Jan 17 01:05:15 PM PST 24
Finished Jan 17 01:05:30 PM PST 24
Peak memory 200628 kb
Host smart-50e5cb54-b121-4011-bd9b-1838dbe3df84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980872258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1980872258
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3915898251
Short name T832
Test name
Test status
Simulation time 347638150992 ps
CPU time 211.36 seconds
Started Jan 17 01:05:13 PM PST 24
Finished Jan 17 01:08:46 PM PST 24
Peak memory 200896 kb
Host smart-67469367-067f-45ca-9ea5-47812c8bbaf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915898251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3915898251
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1503782103
Short name T845
Test name
Test status
Simulation time 324623720 ps
CPU time 1.37 seconds
Started Jan 17 01:05:32 PM PST 24
Finished Jan 17 01:05:35 PM PST 24
Peak memory 200612 kb
Host smart-b9cdbfa3-3122-4f78-aca6-fa0ff0910a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503782103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1503782103
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1612308535
Short name T59
Test name
Test status
Simulation time 327956630054 ps
CPU time 197.86 seconds
Started Jan 17 01:05:25 PM PST 24
Finished Jan 17 01:08:50 PM PST 24
Peak memory 200856 kb
Host smart-3f9a42d7-9bc7-4d1b-9c41-8d466869c645
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612308535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1612308535
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.453660500
Short name T765
Test name
Test status
Simulation time 164811382111 ps
CPU time 199.15 seconds
Started Jan 17 01:05:09 PM PST 24
Finished Jan 17 01:08:30 PM PST 24
Peak memory 200876 kb
Host smart-07f430f1-b564-4056-8248-a43cc6f41aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453660500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.453660500
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.733828686
Short name T683
Test name
Test status
Simulation time 485629511321 ps
CPU time 1157.45 seconds
Started Jan 17 01:05:20 PM PST 24
Finished Jan 17 01:24:40 PM PST 24
Peak memory 200912 kb
Host smart-7776d268-328f-4ba6-a86e-f6761d17f925
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=733828686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.733828686
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2857690888
Short name T848
Test name
Test status
Simulation time 166283951387 ps
CPU time 90.84 seconds
Started Jan 17 01:05:08 PM PST 24
Finished Jan 17 01:06:39 PM PST 24
Peak memory 200896 kb
Host smart-48755aa8-e957-49b6-8278-f278f9c059c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857690888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2857690888
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.737761020
Short name T433
Test name
Test status
Simulation time 480902714834 ps
CPU time 806.86 seconds
Started Jan 17 01:05:15 PM PST 24
Finished Jan 17 01:18:43 PM PST 24
Peak memory 200908 kb
Host smart-75a62799-cec4-4ac2-80d9-0990b7223052
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=737761020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.737761020
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.4158446628
Short name T57
Test name
Test status
Simulation time 502048865862 ps
CPU time 604.45 seconds
Started Jan 17 01:05:14 PM PST 24
Finished Jan 17 01:15:20 PM PST 24
Peak memory 200868 kb
Host smart-45afea96-58d9-4d26-aca4-cc773c75b078
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158446628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.4158446628
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1889171440
Short name T420
Test name
Test status
Simulation time 326833569444 ps
CPU time 762.42 seconds
Started Jan 17 01:05:25 PM PST 24
Finished Jan 17 01:18:15 PM PST 24
Peak memory 200920 kb
Host smart-73b0cbf2-8dcd-4e98-a40f-6bd4d635280b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889171440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1889171440
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1717033130
Short name T335
Test name
Test status
Simulation time 82938714789 ps
CPU time 506.99 seconds
Started Jan 17 01:05:24 PM PST 24
Finished Jan 17 01:13:52 PM PST 24
Peak memory 201312 kb
Host smart-2a82eafc-f7a7-40b5-9ad3-cb1202dbf887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717033130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1717033130
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3208078058
Short name T406
Test name
Test status
Simulation time 31988940044 ps
CPU time 72.37 seconds
Started Jan 17 01:05:23 PM PST 24
Finished Jan 17 01:06:37 PM PST 24
Peak memory 200664 kb
Host smart-b29afe15-4179-4a84-b29e-65a953e4e2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208078058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3208078058
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1242272160
Short name T834
Test name
Test status
Simulation time 4659756996 ps
CPU time 3.74 seconds
Started Jan 17 01:05:23 PM PST 24
Finished Jan 17 01:05:29 PM PST 24
Peak memory 200684 kb
Host smart-25fbe417-b26f-4c54-8582-003d63aa4f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242272160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1242272160
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1050523948
Short name T450
Test name
Test status
Simulation time 5723711206 ps
CPU time 3.95 seconds
Started Jan 17 01:05:15 PM PST 24
Finished Jan 17 01:05:20 PM PST 24
Peak memory 200708 kb
Host smart-57aa025d-68b3-42ba-9ebb-8a90da7c551e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050523948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1050523948
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3376047148
Short name T264
Test name
Test status
Simulation time 57393872832 ps
CPU time 89.94 seconds
Started Jan 17 01:05:25 PM PST 24
Finished Jan 17 01:07:02 PM PST 24
Peak memory 209636 kb
Host smart-27382751-8b44-45b4-952e-597777260367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376047148 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3376047148
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2580753029
Short name T862
Test name
Test status
Simulation time 418403190 ps
CPU time 1.57 seconds
Started Jan 17 01:05:34 PM PST 24
Finished Jan 17 01:05:36 PM PST 24
Peak memory 200576 kb
Host smart-e856200b-878a-47c9-b9a5-20b5c571b30c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580753029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2580753029
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1056495840
Short name T762
Test name
Test status
Simulation time 497455485256 ps
CPU time 1130.97 seconds
Started Jan 17 01:05:28 PM PST 24
Finished Jan 17 01:24:24 PM PST 24
Peak memory 200840 kb
Host smart-241242bd-b423-4282-aa6d-0cefbda9e283
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056495840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1056495840
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.508030517
Short name T236
Test name
Test status
Simulation time 325186139062 ps
CPU time 760.35 seconds
Started Jan 17 01:05:35 PM PST 24
Finished Jan 17 01:18:16 PM PST 24
Peak memory 200980 kb
Host smart-4002b35c-75ab-4149-ae70-4e6edfbc53e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508030517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.508030517
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3493169944
Short name T585
Test name
Test status
Simulation time 326556979217 ps
CPU time 185.91 seconds
Started Jan 17 01:05:28 PM PST 24
Finished Jan 17 01:08:39 PM PST 24
Peak memory 200936 kb
Host smart-5c299b3c-2fb1-4650-a3a6-c7a4c083760c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493169944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3493169944
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.321077394
Short name T624
Test name
Test status
Simulation time 509959457647 ps
CPU time 630.87 seconds
Started Jan 17 01:05:26 PM PST 24
Finished Jan 17 01:16:04 PM PST 24
Peak memory 200900 kb
Host smart-654528b2-c80b-4b47-9eae-dcd78c11f744
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=321077394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.321077394
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3667775813
Short name T93
Test name
Test status
Simulation time 334184054792 ps
CPU time 194.98 seconds
Started Jan 17 01:05:28 PM PST 24
Finished Jan 17 01:08:48 PM PST 24
Peak memory 200804 kb
Host smart-0c629a20-7837-433e-b23d-84dc461ec5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667775813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3667775813
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2207585177
Short name T507
Test name
Test status
Simulation time 165798803746 ps
CPU time 88.43 seconds
Started Jan 17 01:05:35 PM PST 24
Finished Jan 17 01:07:04 PM PST 24
Peak memory 200844 kb
Host smart-0d242ae4-3b82-4946-93a1-b0fdfd707526
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207585177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2207585177
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2765037891
Short name T593
Test name
Test status
Simulation time 166939283607 ps
CPU time 150.58 seconds
Started Jan 17 01:05:32 PM PST 24
Finished Jan 17 01:08:04 PM PST 24
Peak memory 200884 kb
Host smart-4298981c-af34-428c-8c1f-0b348de77cb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765037891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2765037891
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.509793819
Short name T446
Test name
Test status
Simulation time 161190751582 ps
CPU time 28.45 seconds
Started Jan 17 01:05:33 PM PST 24
Finished Jan 17 01:06:02 PM PST 24
Peak memory 200864 kb
Host smart-1cb0e1ec-a3ca-4959-b8b8-4e1a72b56cb6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509793819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.509793819
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.682084237
Short name T706
Test name
Test status
Simulation time 81526973829 ps
CPU time 404.82 seconds
Started Jan 17 01:05:35 PM PST 24
Finished Jan 17 01:12:20 PM PST 24
Peak memory 201252 kb
Host smart-c393260c-127d-4c55-8bcb-cc26272db5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682084237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.682084237
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.717728461
Short name T412
Test name
Test status
Simulation time 40011363748 ps
CPU time 96.05 seconds
Started Jan 17 01:05:32 PM PST 24
Finished Jan 17 01:07:09 PM PST 24
Peak memory 200728 kb
Host smart-488801aa-67fb-4701-acba-8633e8b05584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717728461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.717728461
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2266770371
Short name T566
Test name
Test status
Simulation time 4636873758 ps
CPU time 6.17 seconds
Started Jan 17 01:05:36 PM PST 24
Finished Jan 17 01:05:42 PM PST 24
Peak memory 200696 kb
Host smart-caebcba6-3c70-40b3-93f4-9334a7a9f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266770371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2266770371
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.755316347
Short name T20
Test name
Test status
Simulation time 5727354973 ps
CPU time 14.74 seconds
Started Jan 17 01:05:32 PM PST 24
Finished Jan 17 01:05:48 PM PST 24
Peak memory 200600 kb
Host smart-a9407cde-9955-43f4-88ee-3dbdd7bc3d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755316347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.755316347
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1926760859
Short name T787
Test name
Test status
Simulation time 99377259589 ps
CPU time 335.06 seconds
Started Jan 17 01:05:33 PM PST 24
Finished Jan 17 01:11:09 PM PST 24
Peak memory 216724 kb
Host smart-fdfc939a-5007-4e52-b982-84d05f2d6efc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926760859 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1926760859
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1664999729
Short name T575
Test name
Test status
Simulation time 447715191 ps
CPU time 0.86 seconds
Started Jan 17 01:05:42 PM PST 24
Finished Jan 17 01:05:43 PM PST 24
Peak memory 200560 kb
Host smart-cdaf947e-bf9d-4eda-a5a9-ba644712e932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664999729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1664999729
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2082228650
Short name T297
Test name
Test status
Simulation time 498632424684 ps
CPU time 277.4 seconds
Started Jan 17 01:05:35 PM PST 24
Finished Jan 17 01:10:13 PM PST 24
Peak memory 200820 kb
Host smart-3507ac81-d3a2-4c24-a291-90e0890f6556
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082228650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2082228650
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1917195548
Short name T200
Test name
Test status
Simulation time 328540391105 ps
CPU time 185.6 seconds
Started Jan 17 01:05:36 PM PST 24
Finished Jan 17 01:08:42 PM PST 24
Peak memory 200944 kb
Host smart-eae9ea95-9782-4930-bacd-905f9f2454db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917195548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1917195548
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1262399530
Short name T758
Test name
Test status
Simulation time 327957318882 ps
CPU time 187.25 seconds
Started Jan 17 01:05:37 PM PST 24
Finished Jan 17 01:08:45 PM PST 24
Peak memory 200868 kb
Host smart-6e32c724-bbd5-43a3-b5fa-30b0bfd684df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262399530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1262399530
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3440084778
Short name T419
Test name
Test status
Simulation time 334369574575 ps
CPU time 413.22 seconds
Started Jan 17 01:05:37 PM PST 24
Finished Jan 17 01:12:31 PM PST 24
Peak memory 200872 kb
Host smart-37a43031-c8b3-4098-8c2a-36da08b09abb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440084778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3440084778
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2816381126
Short name T97
Test name
Test status
Simulation time 324070444512 ps
CPU time 336.95 seconds
Started Jan 17 01:05:34 PM PST 24
Finished Jan 17 01:11:11 PM PST 24
Peak memory 200840 kb
Host smart-8c23aa7b-4763-455c-a04c-1fbe40645ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816381126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2816381126
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.871296532
Short name T560
Test name
Test status
Simulation time 480190440819 ps
CPU time 988.55 seconds
Started Jan 17 01:05:35 PM PST 24
Finished Jan 17 01:22:04 PM PST 24
Peak memory 200812 kb
Host smart-0eaf70d1-74f4-4ee4-b9b6-1efa4f7d40f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=871296532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.871296532
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.453908829
Short name T813
Test name
Test status
Simulation time 511000656008 ps
CPU time 1143.91 seconds
Started Jan 17 01:05:36 PM PST 24
Finished Jan 17 01:24:41 PM PST 24
Peak memory 200876 kb
Host smart-25c15ca1-297c-4ba6-b93d-eb0a6c4370c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453908829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.453908829
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.140880355
Short name T713
Test name
Test status
Simulation time 501560470852 ps
CPU time 478.4 seconds
Started Jan 17 01:05:35 PM PST 24
Finished Jan 17 01:13:34 PM PST 24
Peak memory 200828 kb
Host smart-33a0e6fe-84c7-4820-8018-83a2ea9b9be5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140880355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.140880355
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3846849033
Short name T194
Test name
Test status
Simulation time 128772128275 ps
CPU time 478.32 seconds
Started Jan 17 01:05:37 PM PST 24
Finished Jan 17 01:13:36 PM PST 24
Peak memory 201268 kb
Host smart-3730cf53-ede9-4a81-8146-2f525d692fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846849033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3846849033
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1401362575
Short name T18
Test name
Test status
Simulation time 41530590652 ps
CPU time 16.24 seconds
Started Jan 17 01:05:41 PM PST 24
Finished Jan 17 01:05:58 PM PST 24
Peak memory 200652 kb
Host smart-ba363073-f3ec-457e-8813-a2ec2457a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401362575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1401362575
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.361424469
Short name T820
Test name
Test status
Simulation time 3688086946 ps
CPU time 9.8 seconds
Started Jan 17 01:05:37 PM PST 24
Finished Jan 17 01:05:47 PM PST 24
Peak memory 200740 kb
Host smart-117328b9-491c-4f9a-86e1-1857eeb6a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361424469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.361424469
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2182865763
Short name T728
Test name
Test status
Simulation time 5835263173 ps
CPU time 4.22 seconds
Started Jan 17 01:05:37 PM PST 24
Finished Jan 17 01:05:42 PM PST 24
Peak memory 200724 kb
Host smart-3edd4ce1-3505-4092-a755-10592f8dbd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182865763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2182865763
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1086104020
Short name T746
Test name
Test status
Simulation time 54433460274 ps
CPU time 30.77 seconds
Started Jan 17 01:05:36 PM PST 24
Finished Jan 17 01:06:07 PM PST 24
Peak memory 209184 kb
Host smart-6d5bd4ba-ec2c-4771-ad6f-38adbd106f8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086104020 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1086104020
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3418935069
Short name T854
Test name
Test status
Simulation time 493773134 ps
CPU time 1.56 seconds
Started Jan 17 01:05:48 PM PST 24
Finished Jan 17 01:05:50 PM PST 24
Peak memory 200664 kb
Host smart-6a70e064-306d-4ac2-b3e8-ec547e3dfaea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418935069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3418935069
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2008842897
Short name T737
Test name
Test status
Simulation time 162235552245 ps
CPU time 88.14 seconds
Started Jan 17 01:05:46 PM PST 24
Finished Jan 17 01:07:15 PM PST 24
Peak memory 200800 kb
Host smart-97e9db33-0bee-4ac2-8847-843de5213f0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008842897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2008842897
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2274312941
Short name T597
Test name
Test status
Simulation time 165119451209 ps
CPU time 119.37 seconds
Started Jan 17 01:05:44 PM PST 24
Finished Jan 17 01:07:44 PM PST 24
Peak memory 200852 kb
Host smart-4021a11b-0951-4644-923f-fcb57cc7fb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274312941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2274312941
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3309959588
Short name T127
Test name
Test status
Simulation time 323717106832 ps
CPU time 208.51 seconds
Started Jan 17 01:05:45 PM PST 24
Finished Jan 17 01:09:14 PM PST 24
Peak memory 200828 kb
Host smart-2ded8b08-3f73-47c5-a6dd-4bac3f7c1d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309959588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3309959588
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.784652015
Short name T637
Test name
Test status
Simulation time 499025417150 ps
CPU time 459.65 seconds
Started Jan 17 01:05:44 PM PST 24
Finished Jan 17 01:13:25 PM PST 24
Peak memory 200860 kb
Host smart-14be2b5a-0e4d-40c3-bc7b-52a7490fcec4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=784652015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.784652015
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.378129186
Short name T157
Test name
Test status
Simulation time 332494109520 ps
CPU time 731.2 seconds
Started Jan 17 01:05:36 PM PST 24
Finished Jan 17 01:17:48 PM PST 24
Peak memory 200892 kb
Host smart-44bd8f95-4161-415d-ae7c-be2335164107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378129186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.378129186
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.935105073
Short name T629
Test name
Test status
Simulation time 326320318679 ps
CPU time 781.63 seconds
Started Jan 17 01:05:37 PM PST 24
Finished Jan 17 01:18:39 PM PST 24
Peak memory 200888 kb
Host smart-e25745ab-4114-4936-bc81-72e793a76e9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=935105073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.935105073
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.505586005
Short name T322
Test name
Test status
Simulation time 338778205545 ps
CPU time 310.85 seconds
Started Jan 17 01:05:44 PM PST 24
Finished Jan 17 01:10:56 PM PST 24
Peak memory 200784 kb
Host smart-5313247e-4445-48ce-a45a-8bdff2bdb54f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505586005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.505586005
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3093274692
Short name T815
Test name
Test status
Simulation time 164477045991 ps
CPU time 371.83 seconds
Started Jan 17 01:05:46 PM PST 24
Finished Jan 17 01:11:59 PM PST 24
Peak memory 200888 kb
Host smart-f69ff8d8-a324-4ea9-84dc-503536d02e12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093274692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3093274692
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.248812285
Short name T186
Test name
Test status
Simulation time 83250373285 ps
CPU time 399.19 seconds
Started Jan 17 01:05:44 PM PST 24
Finished Jan 17 01:12:23 PM PST 24
Peak memory 201344 kb
Host smart-88b22a65-991a-4ab0-9303-951f322948bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248812285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.248812285
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.551304032
Short name T761
Test name
Test status
Simulation time 33268710940 ps
CPU time 79.61 seconds
Started Jan 17 01:05:44 PM PST 24
Finished Jan 17 01:07:04 PM PST 24
Peak memory 200692 kb
Host smart-2c2ab51e-55f9-4336-9946-a4fe99aead46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551304032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.551304032
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3331849896
Short name T809
Test name
Test status
Simulation time 3819120616 ps
CPU time 1.45 seconds
Started Jan 17 01:05:48 PM PST 24
Finished Jan 17 01:05:50 PM PST 24
Peak memory 200724 kb
Host smart-600b4f45-079b-4171-adb2-f00f57e93276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331849896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3331849896
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2832947323
Short name T718
Test name
Test status
Simulation time 5878383195 ps
CPU time 7.5 seconds
Started Jan 17 01:05:37 PM PST 24
Finished Jan 17 01:05:46 PM PST 24
Peak memory 200688 kb
Host smart-cf30401a-57ae-4174-833e-a51e7c74c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832947323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2832947323
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1823333183
Short name T828
Test name
Test status
Simulation time 389148020935 ps
CPU time 908.19 seconds
Started Jan 17 01:05:44 PM PST 24
Finished Jan 17 01:20:52 PM PST 24
Peak memory 200956 kb
Host smart-f00aab67-5c5d-419b-a6a4-0304a2d1933f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823333183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1823333183
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1506800444
Short name T772
Test name
Test status
Simulation time 368503921 ps
CPU time 1.5 seconds
Started Jan 17 01:05:59 PM PST 24
Finished Jan 17 01:06:01 PM PST 24
Peak memory 200668 kb
Host smart-19bd5a71-d891-4162-a871-b568a4467958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506800444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1506800444
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1789605086
Short name T313
Test name
Test status
Simulation time 322984995728 ps
CPU time 96.99 seconds
Started Jan 17 01:06:00 PM PST 24
Finished Jan 17 01:07:37 PM PST 24
Peak memory 200864 kb
Host smart-a47c62dd-cac0-4879-ade5-8915b7f5cf7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789605086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1789605086
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2857042566
Short name T489
Test name
Test status
Simulation time 160994492793 ps
CPU time 188.12 seconds
Started Jan 17 01:06:02 PM PST 24
Finished Jan 17 01:09:15 PM PST 24
Peak memory 200940 kb
Host smart-1cac1cb1-c313-4cb9-8975-05528e3808d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857042566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2857042566
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1962002917
Short name T276
Test name
Test status
Simulation time 478888556025 ps
CPU time 1145.2 seconds
Started Jan 17 01:05:47 PM PST 24
Finished Jan 17 01:24:53 PM PST 24
Peak memory 200808 kb
Host smart-2b927ff1-1047-47c2-bd40-03585dc9fa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962002917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1962002917
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3103964041
Short name T212
Test name
Test status
Simulation time 490226298091 ps
CPU time 569.48 seconds
Started Jan 17 01:05:46 PM PST 24
Finished Jan 17 01:15:16 PM PST 24
Peak memory 200892 kb
Host smart-3def7c5e-da2f-49d1-a154-3710e8bbb1f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103964041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3103964041
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2891285048
Short name T833
Test name
Test status
Simulation time 161568392109 ps
CPU time 105.53 seconds
Started Jan 17 01:05:45 PM PST 24
Finished Jan 17 01:07:31 PM PST 24
Peak memory 200896 kb
Host smart-109df7ad-928c-4482-bc97-fe3760c36d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891285048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2891285048
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1922511483
Short name T405
Test name
Test status
Simulation time 164361670572 ps
CPU time 181.81 seconds
Started Jan 17 01:05:49 PM PST 24
Finished Jan 17 01:08:51 PM PST 24
Peak memory 200816 kb
Host smart-1cadf2d8-0a8f-473c-9bcf-a5879c81ca9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922511483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1922511483
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.35912866
Short name T669
Test name
Test status
Simulation time 169913294458 ps
CPU time 390.41 seconds
Started Jan 17 01:05:59 PM PST 24
Finished Jan 17 01:12:30 PM PST 24
Peak memory 200848 kb
Host smart-e3fd6f56-75dc-4227-b353-9ac016c316ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_w
akeup.35912866
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.553259100
Short name T490
Test name
Test status
Simulation time 328037367162 ps
CPU time 180.07 seconds
Started Jan 17 01:05:57 PM PST 24
Finished Jan 17 01:09:00 PM PST 24
Peak memory 200852 kb
Host smart-43c7ef28-b231-4e0c-a651-185170d446b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553259100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.553259100
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1716118060
Short name T38
Test name
Test status
Simulation time 103021189406 ps
CPU time 524.08 seconds
Started Jan 17 01:05:59 PM PST 24
Finished Jan 17 01:14:44 PM PST 24
Peak memory 201376 kb
Host smart-535a93a9-5513-4f1b-919b-35e7dd282639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716118060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1716118060
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1478301470
Short name T668
Test name
Test status
Simulation time 40218573869 ps
CPU time 22.07 seconds
Started Jan 17 01:06:02 PM PST 24
Finished Jan 17 01:06:29 PM PST 24
Peak memory 200724 kb
Host smart-829eb06a-edd5-4845-81f9-ddec0d5af9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478301470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1478301470
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2545631506
Short name T602
Test name
Test status
Simulation time 5023369693 ps
CPU time 12.54 seconds
Started Jan 17 01:05:57 PM PST 24
Finished Jan 17 01:06:11 PM PST 24
Peak memory 200728 kb
Host smart-8493d4a0-4bd5-4591-8960-1390d2a6e4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545631506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2545631506
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.4123049105
Short name T145
Test name
Test status
Simulation time 5984157173 ps
CPU time 14.64 seconds
Started Jan 17 01:05:43 PM PST 24
Finished Jan 17 01:05:58 PM PST 24
Peak memory 200704 kb
Host smart-80c8b6e4-48f7-4fc1-aca9-64dfb1433b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123049105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.4123049105
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2746633196
Short name T55
Test name
Test status
Simulation time 488700974131 ps
CPU time 1116.03 seconds
Started Jan 17 01:05:58 PM PST 24
Finished Jan 17 01:24:36 PM PST 24
Peak memory 201396 kb
Host smart-c6a93f14-6680-410d-88ea-6a65d8c9aa3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746633196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2746633196
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4185218807
Short name T614
Test name
Test status
Simulation time 41245311022 ps
CPU time 93.04 seconds
Started Jan 17 01:05:59 PM PST 24
Finished Jan 17 01:07:33 PM PST 24
Peak memory 201032 kb
Host smart-d2b125ac-ebda-4c03-b0e4-6600712fb092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185218807 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4185218807
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2428962703
Short name T754
Test name
Test status
Simulation time 550457277 ps
CPU time 0.69 seconds
Started Jan 17 01:06:19 PM PST 24
Finished Jan 17 01:06:21 PM PST 24
Peak memory 200672 kb
Host smart-e1ca6bd0-dc75-4f23-b2db-e750407568b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428962703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2428962703
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3789750764
Short name T162
Test name
Test status
Simulation time 165965593558 ps
CPU time 100.92 seconds
Started Jan 17 01:06:21 PM PST 24
Finished Jan 17 01:08:03 PM PST 24
Peak memory 200964 kb
Host smart-c1c4a400-d750-4170-8241-8c04e07ce024
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789750764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3789750764
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3918111941
Short name T227
Test name
Test status
Simulation time 497317231894 ps
CPU time 1076.38 seconds
Started Jan 17 01:06:17 PM PST 24
Finished Jan 17 01:24:17 PM PST 24
Peak memory 200892 kb
Host smart-40131461-558d-402b-a5b7-d113efeb7fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918111941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3918111941
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3146507769
Short name T784
Test name
Test status
Simulation time 163961789889 ps
CPU time 418.5 seconds
Started Jan 17 01:06:18 PM PST 24
Finished Jan 17 01:13:19 PM PST 24
Peak memory 200884 kb
Host smart-6d684c7e-aa59-4c37-b613-24f08864b469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146507769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3146507769
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3693236879
Short name T436
Test name
Test status
Simulation time 166142208111 ps
CPU time 190.04 seconds
Started Jan 17 01:06:18 PM PST 24
Finished Jan 17 01:09:30 PM PST 24
Peak memory 200776 kb
Host smart-6b2da0b3-bc80-4923-824a-7a95108e567a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693236879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3693236879
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3182982432
Short name T22
Test name
Test status
Simulation time 332720556312 ps
CPU time 763.25 seconds
Started Jan 17 01:05:57 PM PST 24
Finished Jan 17 01:18:42 PM PST 24
Peak memory 200988 kb
Host smart-011a38f6-dbef-4e1a-a1cb-bcd62ed93efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182982432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3182982432
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.4150535803
Short name T411
Test name
Test status
Simulation time 496449989645 ps
CPU time 335.78 seconds
Started Jan 17 01:06:19 PM PST 24
Finished Jan 17 01:11:57 PM PST 24
Peak memory 200808 kb
Host smart-5f8163e9-12bb-4ccd-900a-5f7a57790ef1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150535803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.4150535803
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1102434434
Short name T314
Test name
Test status
Simulation time 495176537951 ps
CPU time 557.4 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:15:39 PM PST 24
Peak memory 200844 kb
Host smart-06792e77-6f70-4e81-a0be-94e8d3986dc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102434434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1102434434
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3596221663
Short name T724
Test name
Test status
Simulation time 164542265608 ps
CPU time 101.22 seconds
Started Jan 17 01:06:17 PM PST 24
Finished Jan 17 01:08:01 PM PST 24
Peak memory 200860 kb
Host smart-50909864-0492-4e12-8ad2-dba811e3e4ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596221663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3596221663
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2863585175
Short name T58
Test name
Test status
Simulation time 140124957018 ps
CPU time 450.04 seconds
Started Jan 17 01:06:19 PM PST 24
Finished Jan 17 01:13:51 PM PST 24
Peak memory 201264 kb
Host smart-3aa0291e-d967-4dee-b63c-1ce8e3d714c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863585175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2863585175
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.139511348
Short name T409
Test name
Test status
Simulation time 28958298090 ps
CPU time 4.98 seconds
Started Jan 17 01:06:19 PM PST 24
Finished Jan 17 01:06:26 PM PST 24
Peak memory 200688 kb
Host smart-250b369a-4781-4b90-bbf4-26e0a9079a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139511348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.139511348
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.492655428
Short name T631
Test name
Test status
Simulation time 3607805794 ps
CPU time 2.74 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:06:24 PM PST 24
Peak memory 200724 kb
Host smart-f974318a-ebdc-41ac-9d70-0cb6c324eabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492655428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.492655428
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3237240322
Short name T810
Test name
Test status
Simulation time 5883578012 ps
CPU time 13.9 seconds
Started Jan 17 01:05:59 PM PST 24
Finished Jan 17 01:06:14 PM PST 24
Peak memory 200676 kb
Host smart-e5204ac6-3621-4c4b-b193-2a6d064a4b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237240322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3237240322
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3080916988
Short name T571
Test name
Test status
Simulation time 179727637146 ps
CPU time 66.63 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:07:28 PM PST 24
Peak memory 201612 kb
Host smart-a5a2380a-cb52-4be8-99ad-7fdd1c2092c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080916988 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3080916988
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1420758829
Short name T579
Test name
Test status
Simulation time 385651192 ps
CPU time 0.84 seconds
Started Jan 17 01:06:31 PM PST 24
Finished Jan 17 01:06:33 PM PST 24
Peak memory 200660 kb
Host smart-49cb90dd-30cc-4663-973a-3fcb69995985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420758829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1420758829
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2930013881
Short name T741
Test name
Test status
Simulation time 321381404242 ps
CPU time 235.82 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:10:17 PM PST 24
Peak memory 200896 kb
Host smart-766cc702-c780-48db-a2ba-b39644a9e3da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930013881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2930013881
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3808213446
Short name T14
Test name
Test status
Simulation time 331232617504 ps
CPU time 397.08 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:12:59 PM PST 24
Peak memory 200860 kb
Host smart-37f90c73-de19-4f97-8ec7-2857f109664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808213446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3808213446
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.360952345
Short name T792
Test name
Test status
Simulation time 330789610899 ps
CPU time 198.23 seconds
Started Jan 17 01:06:19 PM PST 24
Finished Jan 17 01:09:39 PM PST 24
Peak memory 200800 kb
Host smart-684c9aa0-a923-46de-8ed8-bca4e62e793c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360952345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.360952345
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2036306828
Short name T407
Test name
Test status
Simulation time 493010630528 ps
CPU time 456.74 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:13:58 PM PST 24
Peak memory 200936 kb
Host smart-36a11c59-11d7-4ea5-a131-9e50d8704f20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036306828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2036306828
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1122018404
Short name T203
Test name
Test status
Simulation time 485460175752 ps
CPU time 364.91 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:12:26 PM PST 24
Peak memory 200852 kb
Host smart-c35d7f14-b9c1-4da4-bbc0-83eb483a0a40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122018404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1122018404
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.4105274331
Short name T533
Test name
Test status
Simulation time 157357468478 ps
CPU time 363.13 seconds
Started Jan 17 01:06:19 PM PST 24
Finished Jan 17 01:12:24 PM PST 24
Peak memory 201232 kb
Host smart-65fb5ab0-188d-4095-8140-c3e940b15a87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105274331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.4105274331
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2156782573
Short name T773
Test name
Test status
Simulation time 165420591433 ps
CPU time 99.61 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:08:01 PM PST 24
Peak memory 200876 kb
Host smart-29e42273-fa4b-404e-ab47-ea7eb02d5020
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156782573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2156782573
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.597101275
Short name T753
Test name
Test status
Simulation time 23946802261 ps
CPU time 29.4 seconds
Started Jan 17 01:06:19 PM PST 24
Finished Jan 17 01:06:50 PM PST 24
Peak memory 200728 kb
Host smart-4b842e51-9efb-4b37-b0b8-88909d55e32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597101275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.597101275
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.723596446
Short name T441
Test name
Test status
Simulation time 3656368954 ps
CPU time 8.33 seconds
Started Jan 17 01:06:20 PM PST 24
Finished Jan 17 01:06:29 PM PST 24
Peak memory 200728 kb
Host smart-9dddbb19-d832-4bf8-a85d-a22bf1d44123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723596446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.723596446
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.4105537163
Short name T541
Test name
Test status
Simulation time 5497599286 ps
CPU time 13.43 seconds
Started Jan 17 01:06:22 PM PST 24
Finished Jan 17 01:06:36 PM PST 24
Peak memory 200640 kb
Host smart-e95a0a6c-1cd0-476b-a7d1-aa7df11b4a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105537163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4105537163
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2170882943
Short name T316
Test name
Test status
Simulation time 367003913489 ps
CPU time 919.55 seconds
Started Jan 17 01:06:31 PM PST 24
Finished Jan 17 01:21:52 PM PST 24
Peak memory 200888 kb
Host smart-dcb9b17c-824f-4995-ab32-25482fe2bf8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170882943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2170882943
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3008824777
Short name T680
Test name
Test status
Simulation time 430875595 ps
CPU time 0.94 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:03:05 PM PST 24
Peak memory 200660 kb
Host smart-1497bad8-47d8-4908-9ffd-298161bf1503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008824777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3008824777
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1591969411
Short name T232
Test name
Test status
Simulation time 167461847260 ps
CPU time 346.46 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:08:51 PM PST 24
Peak memory 200872 kb
Host smart-59a44835-7b55-4d62-b29c-12bd238269b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591969411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1591969411
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1434717249
Short name T643
Test name
Test status
Simulation time 487599376008 ps
CPU time 990.68 seconds
Started Jan 17 01:02:58 PM PST 24
Finished Jan 17 01:19:29 PM PST 24
Peak memory 200968 kb
Host smart-1151b1f8-4e72-4499-8422-638b7a6aa3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434717249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1434717249
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3497110144
Short name T578
Test name
Test status
Simulation time 319259984713 ps
CPU time 791.55 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:16:15 PM PST 24
Peak memory 200880 kb
Host smart-803bcad2-05e5-4650-ab9f-88fc3f72e519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497110144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3497110144
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2333257607
Short name T837
Test name
Test status
Simulation time 321982138407 ps
CPU time 754.25 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:15:38 PM PST 24
Peak memory 200936 kb
Host smart-b2a579d0-8e2f-410d-a4db-cd93cbac7307
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333257607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2333257607
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2703231387
Short name T113
Test name
Test status
Simulation time 495167948802 ps
CPU time 271.98 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:07:35 PM PST 24
Peak memory 200828 kb
Host smart-2aa17ca6-8038-4d49-9857-7b7cad256e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703231387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2703231387
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1196167485
Short name T788
Test name
Test status
Simulation time 324491849361 ps
CPU time 195.53 seconds
Started Jan 17 01:02:57 PM PST 24
Finished Jan 17 01:06:13 PM PST 24
Peak memory 200868 kb
Host smart-96ca49c0-1cef-4d53-90a0-703696b24ce9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196167485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1196167485
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.923120068
Short name T435
Test name
Test status
Simulation time 494878361649 ps
CPU time 1077.32 seconds
Started Jan 17 01:02:59 PM PST 24
Finished Jan 17 01:21:00 PM PST 24
Peak memory 200828 kb
Host smart-10e3260b-2d13-4f7d-8759-07d5f455586b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923120068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.923120068
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.4216305632
Short name T343
Test name
Test status
Simulation time 80360482565 ps
CPU time 239.46 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:07:04 PM PST 24
Peak memory 201328 kb
Host smart-16239f97-3878-43ca-9dec-889eba45b8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216305632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.4216305632
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1077463735
Short name T840
Test name
Test status
Simulation time 39357155249 ps
CPU time 22.25 seconds
Started Jan 17 01:03:08 PM PST 24
Finished Jan 17 01:03:31 PM PST 24
Peak memory 200556 kb
Host smart-21532718-0dac-4bc0-b9d7-d5ac806c54af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077463735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1077463735
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.143403908
Short name T647
Test name
Test status
Simulation time 4003081154 ps
CPU time 1.17 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:03:06 PM PST 24
Peak memory 200740 kb
Host smart-fad5ec41-3ba8-4806-ad2c-31b41022e761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143403908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.143403908
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.506850532
Short name T50
Test name
Test status
Simulation time 4788008950 ps
CPU time 1.45 seconds
Started Jan 17 01:02:59 PM PST 24
Finished Jan 17 01:03:04 PM PST 24
Peak memory 215824 kb
Host smart-c5d9dc81-5da1-4bc5-a785-0f58d145b169
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506850532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.506850532
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2957741579
Short name T584
Test name
Test status
Simulation time 5720294779 ps
CPU time 14.74 seconds
Started Jan 17 01:02:57 PM PST 24
Finished Jan 17 01:03:13 PM PST 24
Peak memory 200724 kb
Host smart-0a406a56-3862-4e7a-b2b3-6e5170fb8778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957741579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2957741579
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1612679949
Short name T528
Test name
Test status
Simulation time 175457973410 ps
CPU time 90.43 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:04:35 PM PST 24
Peak memory 209920 kb
Host smart-10be42e2-e7c5-4e1c-a87b-11ea9ef74fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612679949 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1612679949
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.322193160
Short name T811
Test name
Test status
Simulation time 509978053 ps
CPU time 0.97 seconds
Started Jan 17 01:06:28 PM PST 24
Finished Jan 17 01:06:29 PM PST 24
Peak memory 200676 kb
Host smart-872bf97a-5d15-42db-82e9-dcdd536e9c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322193160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.322193160
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3633742310
Short name T851
Test name
Test status
Simulation time 160218493079 ps
CPU time 91.69 seconds
Started Jan 17 01:06:33 PM PST 24
Finished Jan 17 01:08:07 PM PST 24
Peak memory 200856 kb
Host smart-cd37f22e-13d3-49d4-9d06-7ab3a462d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633742310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3633742310
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1213089842
Short name T112
Test name
Test status
Simulation time 165260154528 ps
CPU time 199.63 seconds
Started Jan 17 01:06:28 PM PST 24
Finished Jan 17 01:09:48 PM PST 24
Peak memory 200912 kb
Host smart-3f886a84-d410-40a6-9392-32034369259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213089842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1213089842
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1724469934
Short name T664
Test name
Test status
Simulation time 493260593557 ps
CPU time 287.22 seconds
Started Jan 17 01:06:31 PM PST 24
Finished Jan 17 01:11:19 PM PST 24
Peak memory 200928 kb
Host smart-2722212c-f4d5-4eac-976e-e7b6996e5608
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724469934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1724469934
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3406183696
Short name T21
Test name
Test status
Simulation time 167226513653 ps
CPU time 42.07 seconds
Started Jan 17 01:06:27 PM PST 24
Finished Jan 17 01:07:10 PM PST 24
Peak memory 200828 kb
Host smart-1d91dec5-f12e-4027-9338-70c1dbb1d596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406183696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3406183696
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3383169405
Short name T479
Test name
Test status
Simulation time 490091816340 ps
CPU time 582.71 seconds
Started Jan 17 01:06:28 PM PST 24
Finished Jan 17 01:16:12 PM PST 24
Peak memory 200788 kb
Host smart-6dd56e19-79fe-4a4c-921a-92df20b3fb6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383169405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3383169405
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3865098761
Short name T814
Test name
Test status
Simulation time 324817683381 ps
CPU time 355.3 seconds
Started Jan 17 01:06:29 PM PST 24
Finished Jan 17 01:12:25 PM PST 24
Peak memory 200872 kb
Host smart-0fba41db-f5fa-45e3-a7c4-fdd4e1bea90f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865098761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3865098761
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3549615050
Short name T682
Test name
Test status
Simulation time 333817516585 ps
CPU time 687.08 seconds
Started Jan 17 01:06:30 PM PST 24
Finished Jan 17 01:17:59 PM PST 24
Peak memory 200820 kb
Host smart-f6bb35ea-1f73-40b1-a285-3a09e70ffaba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549615050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3549615050
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.939206474
Short name T332
Test name
Test status
Simulation time 102195132710 ps
CPU time 521.95 seconds
Started Jan 17 01:06:28 PM PST 24
Finished Jan 17 01:15:11 PM PST 24
Peak memory 201372 kb
Host smart-e65be382-67ec-4fbf-983a-6188c89dbe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939206474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.939206474
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3463305695
Short name T778
Test name
Test status
Simulation time 44580370971 ps
CPU time 15.66 seconds
Started Jan 17 01:06:30 PM PST 24
Finished Jan 17 01:06:46 PM PST 24
Peak memory 200688 kb
Host smart-81298fda-27a6-407d-a0e4-39fda703243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463305695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3463305695
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3158075578
Short name T470
Test name
Test status
Simulation time 2784321886 ps
CPU time 3.56 seconds
Started Jan 17 01:06:28 PM PST 24
Finished Jan 17 01:06:32 PM PST 24
Peak memory 200660 kb
Host smart-097668b8-07e5-4002-8343-e0f39d620d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158075578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3158075578
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.4122898623
Short name T858
Test name
Test status
Simulation time 5731691552 ps
CPU time 3.96 seconds
Started Jan 17 01:06:28 PM PST 24
Finished Jan 17 01:06:33 PM PST 24
Peak memory 200632 kb
Host smart-b4929b9e-afd1-4eeb-82ca-9ae725a3647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122898623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4122898623
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1107723744
Short name T99
Test name
Test status
Simulation time 333971410055 ps
CPU time 189.75 seconds
Started Jan 17 01:06:31 PM PST 24
Finished Jan 17 01:09:42 PM PST 24
Peak memory 200988 kb
Host smart-ce072aa0-ca0a-4531-859b-bb8421975981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107723744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1107723744
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3605547347
Short name T721
Test name
Test status
Simulation time 55647804333 ps
CPU time 64.19 seconds
Started Jan 17 01:06:30 PM PST 24
Finished Jan 17 01:07:34 PM PST 24
Peak memory 209576 kb
Host smart-b1dcea2d-fb37-4063-8f39-0bc385bbddad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605547347 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3605547347
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3715876878
Short name T537
Test name
Test status
Simulation time 394773729 ps
CPU time 1.53 seconds
Started Jan 17 01:06:37 PM PST 24
Finished Jan 17 01:06:45 PM PST 24
Peak memory 200672 kb
Host smart-bed45f44-2cd7-4338-9f52-c5e880efda9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715876878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3715876878
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.644709744
Short name T770
Test name
Test status
Simulation time 334686810547 ps
CPU time 807.55 seconds
Started Jan 17 01:06:40 PM PST 24
Finished Jan 17 01:20:11 PM PST 24
Peak memory 200848 kb
Host smart-63ab5795-1a64-47cb-bab1-caaa0daade36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644709744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.644709744
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2746804624
Short name T829
Test name
Test status
Simulation time 319507366048 ps
CPU time 795.15 seconds
Started Jan 17 01:06:29 PM PST 24
Finished Jan 17 01:19:45 PM PST 24
Peak memory 200872 kb
Host smart-788b590f-20f5-41f2-a285-b2a7d1b5a7e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746804624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2746804624
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2243753992
Short name T151
Test name
Test status
Simulation time 499635169565 ps
CPU time 298.68 seconds
Started Jan 17 01:06:29 PM PST 24
Finished Jan 17 01:11:29 PM PST 24
Peak memory 200920 kb
Host smart-e76a8bb6-87ca-4069-aee4-7d7a82a8684c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243753992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2243753992
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2096536379
Short name T638
Test name
Test status
Simulation time 163403338644 ps
CPU time 408.07 seconds
Started Jan 17 01:06:30 PM PST 24
Finished Jan 17 01:13:18 PM PST 24
Peak memory 200824 kb
Host smart-8f7756f6-fb8e-499c-bcd8-f19be2e60659
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096536379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2096536379
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2064197441
Short name T223
Test name
Test status
Simulation time 159949466960 ps
CPU time 172.15 seconds
Started Jan 17 01:06:36 PM PST 24
Finished Jan 17 01:09:35 PM PST 24
Peak memory 200812 kb
Host smart-f489173a-4d91-4883-8242-0fe58d0ad152
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064197441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2064197441
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1682063730
Short name T439
Test name
Test status
Simulation time 329058632506 ps
CPU time 706.31 seconds
Started Jan 17 01:06:38 PM PST 24
Finished Jan 17 01:18:30 PM PST 24
Peak memory 200820 kb
Host smart-db1b36ae-6347-44cc-bcf7-0d8fa940d39a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682063730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1682063730
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2624383729
Short name T807
Test name
Test status
Simulation time 133957699849 ps
CPU time 723.36 seconds
Started Jan 17 01:06:41 PM PST 24
Finished Jan 17 01:18:47 PM PST 24
Peak memory 201300 kb
Host smart-fcddaf87-570b-4ba7-a76d-dd775e9520d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624383729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2624383729
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1584342477
Short name T422
Test name
Test status
Simulation time 31782764024 ps
CPU time 77.18 seconds
Started Jan 17 01:06:38 PM PST 24
Finished Jan 17 01:08:00 PM PST 24
Peak memory 200684 kb
Host smart-eda2fe04-e0fc-493e-92b8-3ffe5d6c8a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584342477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1584342477
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.775286887
Short name T745
Test name
Test status
Simulation time 4953514152 ps
CPU time 6.67 seconds
Started Jan 17 01:06:38 PM PST 24
Finished Jan 17 01:06:50 PM PST 24
Peak memory 200736 kb
Host smart-7f04480c-5a92-4d7e-a596-4d732b69d235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775286887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.775286887
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.4142087933
Short name T403
Test name
Test status
Simulation time 5741625580 ps
CPU time 1.48 seconds
Started Jan 17 01:06:28 PM PST 24
Finished Jan 17 01:06:30 PM PST 24
Peak memory 200688 kb
Host smart-7c94aaf1-ea91-48e7-ab0f-1cc109a3c0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142087933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4142087933
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1803422203
Short name T816
Test name
Test status
Simulation time 327280820626 ps
CPU time 706.73 seconds
Started Jan 17 01:06:36 PM PST 24
Finished Jan 17 01:18:29 PM PST 24
Peak memory 200864 kb
Host smart-3af161b9-c6ea-4b9c-81b9-6474b8949f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803422203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1803422203
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2028295429
Short name T651
Test name
Test status
Simulation time 653071570041 ps
CPU time 462.35 seconds
Started Jan 17 01:06:37 PM PST 24
Finished Jan 17 01:14:26 PM PST 24
Peak memory 209580 kb
Host smart-6b2e82d0-90ab-441a-9137-9c36cd89c9ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028295429 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2028295429
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1501984072
Short name T45
Test name
Test status
Simulation time 472658979 ps
CPU time 1.71 seconds
Started Jan 17 01:06:50 PM PST 24
Finished Jan 17 01:06:53 PM PST 24
Peak memory 200684 kb
Host smart-23e3b3bb-abf0-4e6e-9990-7d3eea3d9e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501984072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1501984072
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2326269252
Short name T556
Test name
Test status
Simulation time 167253865710 ps
CPU time 309.28 seconds
Started Jan 17 01:06:51 PM PST 24
Finished Jan 17 01:12:01 PM PST 24
Peak memory 200900 kb
Host smart-f9510292-f3db-4e31-9823-6088c0f06071
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326269252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2326269252
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.261778951
Short name T625
Test name
Test status
Simulation time 487347417629 ps
CPU time 283.52 seconds
Started Jan 17 01:06:50 PM PST 24
Finished Jan 17 01:11:34 PM PST 24
Peak memory 200800 kb
Host smart-e5246b91-58b7-4de4-ae55-0ad399635ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261778951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.261778951
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2537580945
Short name T600
Test name
Test status
Simulation time 328462181212 ps
CPU time 842.76 seconds
Started Jan 17 01:06:46 PM PST 24
Finished Jan 17 01:20:50 PM PST 24
Peak memory 200868 kb
Host smart-07581956-2a81-490a-ba17-188905cbd359
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537580945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2537580945
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.805988510
Short name T523
Test name
Test status
Simulation time 328508724766 ps
CPU time 197.34 seconds
Started Jan 17 01:06:41 PM PST 24
Finished Jan 17 01:10:01 PM PST 24
Peak memory 200792 kb
Host smart-2eff8ef2-318a-416c-90ab-f918356ddfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805988510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.805988510
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3614854408
Short name T827
Test name
Test status
Simulation time 488874145157 ps
CPU time 482.54 seconds
Started Jan 17 01:06:37 PM PST 24
Finished Jan 17 01:14:46 PM PST 24
Peak memory 200968 kb
Host smart-8b0e6c2b-d3d6-4b28-8e2c-116beef21d6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614854408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3614854408
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1687588702
Short name T315
Test name
Test status
Simulation time 327065064808 ps
CPU time 206.89 seconds
Started Jan 17 01:06:45 PM PST 24
Finished Jan 17 01:10:13 PM PST 24
Peak memory 200880 kb
Host smart-6010b9c5-7a93-4008-ab34-4abb9351860b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687588702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1687588702
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2401599713
Short name T646
Test name
Test status
Simulation time 324744546168 ps
CPU time 306.48 seconds
Started Jan 17 01:06:48 PM PST 24
Finished Jan 17 01:11:55 PM PST 24
Peak memory 200808 kb
Host smart-a37ffbec-71b3-487c-a841-b2e571cd3960
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401599713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2401599713
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.651649682
Short name T767
Test name
Test status
Simulation time 75574501220 ps
CPU time 398.11 seconds
Started Jan 17 01:06:48 PM PST 24
Finished Jan 17 01:13:27 PM PST 24
Peak memory 201368 kb
Host smart-f36d1e26-a6f8-49e4-9fa2-e27d7ce619a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651649682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.651649682
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3698675190
Short name T555
Test name
Test status
Simulation time 40651701570 ps
CPU time 99.38 seconds
Started Jan 17 01:06:51 PM PST 24
Finished Jan 17 01:08:31 PM PST 24
Peak memory 200676 kb
Host smart-304ef9f8-9e07-433e-8afe-cb9c47778758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698675190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3698675190
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.4242719839
Short name T708
Test name
Test status
Simulation time 3083278437 ps
CPU time 4.89 seconds
Started Jan 17 01:06:47 PM PST 24
Finished Jan 17 01:06:52 PM PST 24
Peak memory 200556 kb
Host smart-2605f1a9-83c9-40fe-aa63-edd138ba0900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242719839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4242719839
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1362152408
Short name T527
Test name
Test status
Simulation time 5501637028 ps
CPU time 3.99 seconds
Started Jan 17 01:06:39 PM PST 24
Finished Jan 17 01:06:47 PM PST 24
Peak memory 200704 kb
Host smart-98b99f0e-de5d-4894-a03b-6c57947c24ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362152408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1362152408
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.336677193
Short name T231
Test name
Test status
Simulation time 412589698385 ps
CPU time 1386.13 seconds
Started Jan 17 01:06:47 PM PST 24
Finished Jan 17 01:29:53 PM PST 24
Peak memory 209508 kb
Host smart-543cc90d-132a-4772-86a0-1d9decdc4320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336677193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
336677193
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1275986303
Short name T208
Test name
Test status
Simulation time 11574871309 ps
CPU time 29.21 seconds
Started Jan 17 01:06:48 PM PST 24
Finished Jan 17 01:07:18 PM PST 24
Peak memory 209196 kb
Host smart-503cce70-0617-4646-97e0-2ed20b2af1eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275986303 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1275986303
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1297817265
Short name T622
Test name
Test status
Simulation time 424483693 ps
CPU time 1.6 seconds
Started Jan 17 01:07:06 PM PST 24
Finished Jan 17 01:07:08 PM PST 24
Peak memory 200408 kb
Host smart-7f0de8f6-35c8-461a-b2dc-4d4ec76ff4fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297817265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1297817265
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1271219344
Short name T304
Test name
Test status
Simulation time 164482342226 ps
CPU time 33.25 seconds
Started Jan 17 01:07:06 PM PST 24
Finished Jan 17 01:07:42 PM PST 24
Peak memory 200844 kb
Host smart-4f5ff7d3-9862-4b52-8778-68d89d9eb2f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271219344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1271219344
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.898173461
Short name T800
Test name
Test status
Simulation time 168112067495 ps
CPU time 91.97 seconds
Started Jan 17 01:07:06 PM PST 24
Finished Jan 17 01:08:41 PM PST 24
Peak memory 200888 kb
Host smart-64d8cc05-a1c4-4610-bac9-707117f9f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898173461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.898173461
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1264669985
Short name T451
Test name
Test status
Simulation time 167240956704 ps
CPU time 110.83 seconds
Started Jan 17 01:07:09 PM PST 24
Finished Jan 17 01:09:03 PM PST 24
Peak memory 200892 kb
Host smart-c6e5600e-507b-4f8d-b026-ceb7b905d82f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264669985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1264669985
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1037598112
Short name T324
Test name
Test status
Simulation time 331393931704 ps
CPU time 223.13 seconds
Started Jan 17 01:07:01 PM PST 24
Finished Jan 17 01:10:45 PM PST 24
Peak memory 200932 kb
Host smart-99e3e28b-5f7e-4f49-ae0c-8934fa369c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037598112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1037598112
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2372878896
Short name T835
Test name
Test status
Simulation time 160720038108 ps
CPU time 177.85 seconds
Started Jan 17 01:07:07 PM PST 24
Finished Jan 17 01:10:08 PM PST 24
Peak memory 200844 kb
Host smart-682e05aa-bd96-4a0e-92da-8be6bd1f91b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372878896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2372878896
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2564842700
Short name T126
Test name
Test status
Simulation time 165774803417 ps
CPU time 48.21 seconds
Started Jan 17 01:07:04 PM PST 24
Finished Jan 17 01:07:53 PM PST 24
Peak memory 200800 kb
Host smart-53a856bc-4c22-4909-b012-56f002e43c73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564842700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2564842700
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3293546954
Short name T521
Test name
Test status
Simulation time 490422692885 ps
CPU time 553.69 seconds
Started Jan 17 01:07:07 PM PST 24
Finished Jan 17 01:16:24 PM PST 24
Peak memory 200928 kb
Host smart-a84d8b1b-86d7-44c2-8673-3d3dbb5c4d97
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293546954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3293546954
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.46225457
Short name T632
Test name
Test status
Simulation time 70800386126 ps
CPU time 379.13 seconds
Started Jan 17 01:07:02 PM PST 24
Finished Jan 17 01:13:22 PM PST 24
Peak memory 201320 kb
Host smart-b6ddca08-381e-4bfc-8ac3-b6bc1ab11256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46225457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.46225457
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1494377451
Short name T801
Test name
Test status
Simulation time 26068178350 ps
CPU time 31.24 seconds
Started Jan 17 01:07:03 PM PST 24
Finished Jan 17 01:07:34 PM PST 24
Peak memory 200704 kb
Host smart-29046e80-4160-4232-871b-6e5ee668f6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494377451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1494377451
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4211040710
Short name T619
Test name
Test status
Simulation time 3488402185 ps
CPU time 4.83 seconds
Started Jan 17 01:07:10 PM PST 24
Finished Jan 17 01:07:17 PM PST 24
Peak memory 200680 kb
Host smart-1c67984c-8f94-410e-b944-de70f5064ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211040710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4211040710
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1102337741
Short name T863
Test name
Test status
Simulation time 5781282927 ps
CPU time 3.18 seconds
Started Jan 17 01:06:47 PM PST 24
Finished Jan 17 01:06:50 PM PST 24
Peak memory 200680 kb
Host smart-ded21231-163f-4d4a-b630-c51cc8b317f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102337741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1102337741
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.132603020
Short name T287
Test name
Test status
Simulation time 333128159429 ps
CPU time 332.8 seconds
Started Jan 17 01:07:03 PM PST 24
Finished Jan 17 01:12:36 PM PST 24
Peak memory 200872 kb
Host smart-27ea9877-95e1-43b1-8115-229f49426e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132603020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
132603020
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3788708357
Short name T341
Test name
Test status
Simulation time 694720059837 ps
CPU time 663.1 seconds
Started Jan 17 01:07:09 PM PST 24
Finished Jan 17 01:18:15 PM PST 24
Peak memory 209636 kb
Host smart-8fe939a6-801d-486d-9bcd-2dead3f83d57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788708357 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3788708357
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1318718391
Short name T477
Test name
Test status
Simulation time 400561218 ps
CPU time 1.43 seconds
Started Jan 17 01:07:09 PM PST 24
Finished Jan 17 01:07:13 PM PST 24
Peak memory 200672 kb
Host smart-5c4cc3a6-54f6-4a8b-8d34-ef24a5eacd24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318718391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1318718391
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1301078652
Short name T292
Test name
Test status
Simulation time 164486598711 ps
CPU time 98.62 seconds
Started Jan 17 01:07:11 PM PST 24
Finished Jan 17 01:08:51 PM PST 24
Peak memory 200800 kb
Host smart-06ce66e8-1fa9-4c23-86de-d4eae7070a44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301078652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1301078652
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3876111165
Short name T665
Test name
Test status
Simulation time 331303378207 ps
CPU time 198.09 seconds
Started Jan 17 01:07:06 PM PST 24
Finished Jan 17 01:10:24 PM PST 24
Peak memory 200888 kb
Host smart-16b641c6-4c4c-4a00-b9d1-a42da5fb23f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876111165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3876111165
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.273383538
Short name T636
Test name
Test status
Simulation time 497802657086 ps
CPU time 624.35 seconds
Started Jan 17 01:07:08 PM PST 24
Finished Jan 17 01:17:35 PM PST 24
Peak memory 200936 kb
Host smart-e8a83ead-bf55-4f93-9cae-8cd766787260
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=273383538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.273383538
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.880476464
Short name T23
Test name
Test status
Simulation time 164078977712 ps
CPU time 53.93 seconds
Started Jan 17 01:07:01 PM PST 24
Finished Jan 17 01:07:56 PM PST 24
Peak memory 200892 kb
Host smart-8e173072-1cb0-47d6-8757-5c9f8423be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880476464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.880476464
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3661330828
Short name T471
Test name
Test status
Simulation time 327238033227 ps
CPU time 379.13 seconds
Started Jan 17 01:07:07 PM PST 24
Finished Jan 17 01:13:29 PM PST 24
Peak memory 200864 kb
Host smart-eb725607-2cec-4adb-95bc-3f078f37609d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661330828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3661330828
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1787941281
Short name T249
Test name
Test status
Simulation time 488393535209 ps
CPU time 1210.06 seconds
Started Jan 17 01:07:07 PM PST 24
Finished Jan 17 01:27:21 PM PST 24
Peak memory 200952 kb
Host smart-9679a2aa-d67d-4bbd-a18a-d38fc65d88b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787941281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1787941281
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.487842571
Short name T601
Test name
Test status
Simulation time 161988943128 ps
CPU time 413.26 seconds
Started Jan 17 01:07:09 PM PST 24
Finished Jan 17 01:14:05 PM PST 24
Peak memory 200808 kb
Host smart-e8a7abe6-5f5e-48dd-a4f8-f7548de20eb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487842571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.487842571
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1050561519
Short name T613
Test name
Test status
Simulation time 107510732724 ps
CPU time 592.77 seconds
Started Jan 17 01:07:09 PM PST 24
Finished Jan 17 01:17:04 PM PST 24
Peak memory 201176 kb
Host smart-a030bece-a1e3-4379-90c6-4cac87fd7eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050561519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1050561519
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2638437918
Short name T739
Test name
Test status
Simulation time 34846731569 ps
CPU time 39.63 seconds
Started Jan 17 01:07:09 PM PST 24
Finished Jan 17 01:07:51 PM PST 24
Peak memory 200660 kb
Host smart-37c675e0-7d91-4b4c-a0e9-b928316c5f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638437918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2638437918
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.535064076
Short name T91
Test name
Test status
Simulation time 4378972604 ps
CPU time 10.07 seconds
Started Jan 17 01:07:09 PM PST 24
Finished Jan 17 01:07:22 PM PST 24
Peak memory 200748 kb
Host smart-34af399d-2e9b-40a8-b8ad-f184c84b2c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535064076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.535064076
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3477242050
Short name T594
Test name
Test status
Simulation time 5966887668 ps
CPU time 15.43 seconds
Started Jan 17 01:07:08 PM PST 24
Finished Jan 17 01:07:26 PM PST 24
Peak memory 200668 kb
Host smart-06ddf1c9-1b98-4d5b-8b11-bcca4a3cbfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477242050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3477242050
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2663832949
Short name T749
Test name
Test status
Simulation time 166044808969 ps
CPU time 91.62 seconds
Started Jan 17 01:07:11 PM PST 24
Finished Jan 17 01:08:44 PM PST 24
Peak memory 200884 kb
Host smart-2f6f689d-51ce-4def-bf83-a39cdc9a6034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663832949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2663832949
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.739067981
Short name T243
Test name
Test status
Simulation time 109481192157 ps
CPU time 86.6 seconds
Started Jan 17 01:07:09 PM PST 24
Finished Jan 17 01:08:38 PM PST 24
Peak memory 209588 kb
Host smart-65b4e034-e599-4783-8e6f-bf21dda03714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739067981 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.739067981
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1879936044
Short name T554
Test name
Test status
Simulation time 512266708 ps
CPU time 0.88 seconds
Started Jan 17 01:07:21 PM PST 24
Finished Jan 17 01:07:23 PM PST 24
Peak memory 200584 kb
Host smart-9313154d-4869-4e5d-b2f3-9e2751af9542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879936044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1879936044
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.4186343254
Short name T235
Test name
Test status
Simulation time 163570702276 ps
CPU time 362.93 seconds
Started Jan 17 01:07:25 PM PST 24
Finished Jan 17 01:13:28 PM PST 24
Peak memory 200868 kb
Host smart-9f480af6-8c20-4c23-8b85-9bb6353ca1cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186343254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.4186343254
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4214350396
Short name T277
Test name
Test status
Simulation time 485110694640 ps
CPU time 190.98 seconds
Started Jan 17 01:07:20 PM PST 24
Finished Jan 17 01:10:32 PM PST 24
Peak memory 200948 kb
Host smart-ec2e9fd7-58ba-47f3-9c04-6b37706111e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214350396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4214350396
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2554791055
Short name T136
Test name
Test status
Simulation time 331478649916 ps
CPU time 94.32 seconds
Started Jan 17 01:07:11 PM PST 24
Finished Jan 17 01:08:47 PM PST 24
Peak memory 200932 kb
Host smart-678e384b-15ea-4c16-b2a2-2a1d3e1a42bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554791055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2554791055
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2853546975
Short name T408
Test name
Test status
Simulation time 491310520568 ps
CPU time 1135.97 seconds
Started Jan 17 01:07:21 PM PST 24
Finished Jan 17 01:26:18 PM PST 24
Peak memory 200820 kb
Host smart-4eb5c53c-31a8-46aa-822b-881945b7a4c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853546975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2853546975
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.556811288
Short name T797
Test name
Test status
Simulation time 331263667036 ps
CPU time 217.47 seconds
Started Jan 17 01:07:11 PM PST 24
Finished Jan 17 01:10:50 PM PST 24
Peak memory 200888 kb
Host smart-9410e57f-af72-4dc5-9778-d27d10693eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556811288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.556811288
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1178842776
Short name T591
Test name
Test status
Simulation time 492761815257 ps
CPU time 358.3 seconds
Started Jan 17 01:07:08 PM PST 24
Finished Jan 17 01:13:09 PM PST 24
Peak memory 200824 kb
Host smart-031f247a-070e-4730-afac-898340a93d99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178842776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1178842776
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1204730783
Short name T634
Test name
Test status
Simulation time 498249889886 ps
CPU time 1127.35 seconds
Started Jan 17 01:07:20 PM PST 24
Finished Jan 17 01:26:09 PM PST 24
Peak memory 201116 kb
Host smart-bd8bf295-6eae-42bc-bec2-b637e97f4604
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204730783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1204730783
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1962255818
Short name T589
Test name
Test status
Simulation time 325447740023 ps
CPU time 741.57 seconds
Started Jan 17 01:07:21 PM PST 24
Finished Jan 17 01:19:43 PM PST 24
Peak memory 200792 kb
Host smart-23eea0ff-21ce-486a-bfda-e412becd633a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962255818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1962255818
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2226064956
Short name T39
Test name
Test status
Simulation time 97901067971 ps
CPU time 518.95 seconds
Started Jan 17 01:07:19 PM PST 24
Finished Jan 17 01:16:00 PM PST 24
Peak memory 201268 kb
Host smart-aa0cc207-c1aa-4af8-be15-d58b2b514632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226064956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2226064956
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1780992053
Short name T799
Test name
Test status
Simulation time 28970044375 ps
CPU time 66.3 seconds
Started Jan 17 01:07:21 PM PST 24
Finished Jan 17 01:08:28 PM PST 24
Peak memory 200700 kb
Host smart-dabd87aa-84be-40a5-9daa-cd272f43c293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780992053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1780992053
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4187223622
Short name T639
Test name
Test status
Simulation time 4901573550 ps
CPU time 3.86 seconds
Started Jan 17 01:07:18 PM PST 24
Finished Jan 17 01:07:25 PM PST 24
Peak memory 200720 kb
Host smart-a3cc773c-3d35-4b66-bc00-2748a1b879ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187223622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4187223622
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.426828311
Short name T147
Test name
Test status
Simulation time 5930594151 ps
CPU time 4.17 seconds
Started Jan 17 01:07:09 PM PST 24
Finished Jan 17 01:07:16 PM PST 24
Peak memory 200708 kb
Host smart-6b91b187-79b0-468e-9601-153cbe1ca690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426828311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.426828311
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3194106414
Short name T180
Test name
Test status
Simulation time 408916191113 ps
CPU time 317.06 seconds
Started Jan 17 01:07:21 PM PST 24
Finished Jan 17 01:12:39 PM PST 24
Peak memory 209564 kb
Host smart-3f04f5f7-4a78-49c5-a5eb-c9f7c0ae4163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194106414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3194106414
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1909445092
Short name T339
Test name
Test status
Simulation time 20553863086 ps
CPU time 69.34 seconds
Started Jan 17 01:07:21 PM PST 24
Finished Jan 17 01:08:31 PM PST 24
Peak memory 209608 kb
Host smart-0797f768-50a8-4147-bcd8-0795f07ac940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909445092 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1909445092
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2098768388
Short name T455
Test name
Test status
Simulation time 387712598 ps
CPU time 0.75 seconds
Started Jan 17 01:07:28 PM PST 24
Finished Jan 17 01:07:30 PM PST 24
Peak memory 200712 kb
Host smart-f208c577-261f-47a5-9287-40049a2bc5d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098768388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2098768388
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.102724859
Short name T242
Test name
Test status
Simulation time 329830320756 ps
CPU time 208.8 seconds
Started Jan 17 01:07:22 PM PST 24
Finished Jan 17 01:10:51 PM PST 24
Peak memory 200904 kb
Host smart-8797ada1-2784-4170-abac-013123920360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102724859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.102724859
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.937322082
Short name T675
Test name
Test status
Simulation time 330358614874 ps
CPU time 805.09 seconds
Started Jan 17 01:07:22 PM PST 24
Finished Jan 17 01:20:48 PM PST 24
Peak memory 200852 kb
Host smart-e0379450-c589-4e75-963c-d4480fbeade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937322082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.937322082
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1535720490
Short name T509
Test name
Test status
Simulation time 491465258681 ps
CPU time 304.35 seconds
Started Jan 17 01:07:21 PM PST 24
Finished Jan 17 01:12:26 PM PST 24
Peak memory 200824 kb
Host smart-33e4ac22-206a-469f-ae18-d6a687ab72dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535720490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1535720490
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2250548122
Short name T95
Test name
Test status
Simulation time 330786710160 ps
CPU time 807.35 seconds
Started Jan 17 01:07:20 PM PST 24
Finished Jan 17 01:20:48 PM PST 24
Peak memory 201000 kb
Host smart-7c7c0181-3511-4fa4-8e45-fb8d67bdd1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250548122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2250548122
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2120694070
Short name T852
Test name
Test status
Simulation time 485301781171 ps
CPU time 1027.06 seconds
Started Jan 17 01:07:20 PM PST 24
Finished Jan 17 01:24:28 PM PST 24
Peak memory 200760 kb
Host smart-61b2d9e8-3d39-45be-87a0-db8db76cfbd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120694070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2120694070
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.950317898
Short name T781
Test name
Test status
Simulation time 494887954528 ps
CPU time 1145.05 seconds
Started Jan 17 01:07:19 PM PST 24
Finished Jan 17 01:26:26 PM PST 24
Peak memory 200904 kb
Host smart-d5262c23-6c40-4948-aa50-cbbebe30bcb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950317898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.950317898
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.714157770
Short name T197
Test name
Test status
Simulation time 91078843381 ps
CPU time 521.94 seconds
Started Jan 17 01:07:28 PM PST 24
Finished Jan 17 01:16:12 PM PST 24
Peak memory 201368 kb
Host smart-d9d209d6-fc07-4d21-a851-0744aec34806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714157770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.714157770
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.408050038
Short name T416
Test name
Test status
Simulation time 44222885960 ps
CPU time 15.66 seconds
Started Jan 17 01:07:28 PM PST 24
Finished Jan 17 01:07:46 PM PST 24
Peak memory 200728 kb
Host smart-31969434-df8c-4a55-b59b-fbe0b96f4556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408050038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.408050038
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3081855174
Short name T628
Test name
Test status
Simulation time 3601041210 ps
CPU time 9.27 seconds
Started Jan 17 01:07:29 PM PST 24
Finished Jan 17 01:07:40 PM PST 24
Peak memory 200672 kb
Host smart-661c2094-78bc-4cdc-9d85-bf24096b738f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081855174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3081855174
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2419935650
Short name T760
Test name
Test status
Simulation time 6118562149 ps
CPU time 3.6 seconds
Started Jan 17 01:07:18 PM PST 24
Finished Jan 17 01:07:24 PM PST 24
Peak memory 200684 kb
Host smart-b0aa8553-f5ba-4e28-bf9f-ce1abdceb1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419935650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2419935650
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2354130735
Short name T293
Test name
Test status
Simulation time 58790821253 ps
CPU time 95.94 seconds
Started Jan 17 01:07:28 PM PST 24
Finished Jan 17 01:09:05 PM PST 24
Peak memory 209584 kb
Host smart-97cc5f4f-2207-4c92-89d3-12fe97fe4b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354130735 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2354130735
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1765061769
Short name T621
Test name
Test status
Simulation time 313396358 ps
CPU time 0.75 seconds
Started Jan 17 01:07:38 PM PST 24
Finished Jan 17 01:07:39 PM PST 24
Peak memory 200640 kb
Host smart-181851ec-9a30-4f9b-b594-609531c664c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765061769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1765061769
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1619614043
Short name T300
Test name
Test status
Simulation time 165574098220 ps
CPU time 91.4 seconds
Started Jan 17 01:07:29 PM PST 24
Finished Jan 17 01:09:02 PM PST 24
Peak memory 200964 kb
Host smart-77e98323-6139-4010-8a6d-6ebf942e8e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619614043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1619614043
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3814301062
Short name T160
Test name
Test status
Simulation time 321987942801 ps
CPU time 673.11 seconds
Started Jan 17 01:07:29 PM PST 24
Finished Jan 17 01:18:44 PM PST 24
Peak memory 200864 kb
Host smart-106a3e62-67b8-4b8b-87ed-272e2a65229f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814301062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3814301062
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3410751967
Short name T573
Test name
Test status
Simulation time 490165060025 ps
CPU time 1112.15 seconds
Started Jan 17 01:07:31 PM PST 24
Finished Jan 17 01:26:04 PM PST 24
Peak memory 200832 kb
Host smart-ac46a9bf-0f0a-47e8-8b47-a44cca45aab1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410751967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3410751967
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1131390954
Short name T544
Test name
Test status
Simulation time 329135594199 ps
CPU time 132.51 seconds
Started Jan 17 01:07:29 PM PST 24
Finished Jan 17 01:09:43 PM PST 24
Peak memory 201004 kb
Host smart-b1a25194-d301-4987-8faa-89d8db894790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131390954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1131390954
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4212498634
Short name T764
Test name
Test status
Simulation time 166228698434 ps
CPU time 185.95 seconds
Started Jan 17 01:07:31 PM PST 24
Finished Jan 17 01:10:38 PM PST 24
Peak memory 200816 kb
Host smart-b71fb620-1fb8-46be-98a6-70c4bcb6b181
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212498634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4212498634
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2452057464
Short name T298
Test name
Test status
Simulation time 165976167605 ps
CPU time 107.58 seconds
Started Jan 17 01:07:29 PM PST 24
Finished Jan 17 01:09:19 PM PST 24
Peak memory 200812 kb
Host smart-111a5571-b1a7-4084-838e-3a1753e6e68f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452057464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2452057464
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1936965262
Short name T531
Test name
Test status
Simulation time 164702983584 ps
CPU time 192.49 seconds
Started Jan 17 01:07:37 PM PST 24
Finished Jan 17 01:10:50 PM PST 24
Peak memory 200900 kb
Host smart-0413084f-10ed-46df-bebc-80500bb1842d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936965262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1936965262
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3930856488
Short name T175
Test name
Test status
Simulation time 81250544509 ps
CPU time 455.71 seconds
Started Jan 17 01:07:37 PM PST 24
Finished Jan 17 01:15:14 PM PST 24
Peak memory 201348 kb
Host smart-16854e99-9d27-4b74-b1a3-c02d2c88bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930856488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3930856488
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1906275696
Short name T598
Test name
Test status
Simulation time 23695918895 ps
CPU time 11.83 seconds
Started Jan 17 01:07:28 PM PST 24
Finished Jan 17 01:07:42 PM PST 24
Peak memory 200764 kb
Host smart-39fdb11e-8609-4da7-9079-4b105b3fa952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906275696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1906275696
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2002771286
Short name T512
Test name
Test status
Simulation time 4657203450 ps
CPU time 10.47 seconds
Started Jan 17 01:07:28 PM PST 24
Finished Jan 17 01:07:41 PM PST 24
Peak memory 200732 kb
Host smart-ec2c6b0d-f5df-4d4f-aa5e-b19bbc9483eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002771286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2002771286
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3540898948
Short name T442
Test name
Test status
Simulation time 6093144179 ps
CPU time 15.74 seconds
Started Jan 17 01:07:29 PM PST 24
Finished Jan 17 01:07:47 PM PST 24
Peak memory 200676 kb
Host smart-2e61631d-1010-47b1-983e-45a60592a990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540898948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3540898948
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2373676034
Short name T86
Test name
Test status
Simulation time 163598783174 ps
CPU time 375.78 seconds
Started Jan 17 01:07:29 PM PST 24
Finished Jan 17 01:13:47 PM PST 24
Peak memory 200828 kb
Host smart-035e53a3-4270-4063-86af-aebd7d45e78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373676034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2373676034
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.964827955
Short name T856
Test name
Test status
Simulation time 78819143612 ps
CPU time 144.02 seconds
Started Jan 17 01:07:29 PM PST 24
Finished Jan 17 01:09:55 PM PST 24
Peak memory 217012 kb
Host smart-2f9780ed-a0e5-46a2-a268-e2f5701604e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964827955 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.964827955
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2007905498
Short name T572
Test name
Test status
Simulation time 499043259 ps
CPU time 1.16 seconds
Started Jan 17 01:07:46 PM PST 24
Finished Jan 17 01:07:49 PM PST 24
Peak memory 200448 kb
Host smart-58ca8218-d03e-4a37-b9aa-2f136e201db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007905498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2007905498
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3442275339
Short name T213
Test name
Test status
Simulation time 493525495880 ps
CPU time 962.49 seconds
Started Jan 17 01:07:45 PM PST 24
Finished Jan 17 01:23:51 PM PST 24
Peak memory 200836 kb
Host smart-ab62867f-a733-45ca-8114-4f9c14fef883
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442275339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3442275339
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1455120053
Short name T841
Test name
Test status
Simulation time 160178134145 ps
CPU time 201.27 seconds
Started Jan 17 01:07:44 PM PST 24
Finished Jan 17 01:11:08 PM PST 24
Peak memory 200912 kb
Host smart-9c92cdbc-b7b3-44d6-9324-5b581fe20897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455120053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1455120053
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4050063342
Short name T518
Test name
Test status
Simulation time 326224788293 ps
CPU time 785.82 seconds
Started Jan 17 01:07:45 PM PST 24
Finished Jan 17 01:20:54 PM PST 24
Peak memory 200912 kb
Host smart-42cb5323-8e39-4cdd-a36a-b373a7e1b7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050063342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4050063342
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2021284288
Short name T459
Test name
Test status
Simulation time 489774203259 ps
CPU time 1076.22 seconds
Started Jan 17 01:07:43 PM PST 24
Finished Jan 17 01:25:41 PM PST 24
Peak memory 200868 kb
Host smart-4abeb962-21c0-40b4-9b76-9f667ccc2d76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021284288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2021284288
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.171608509
Short name T101
Test name
Test status
Simulation time 332377081537 ps
CPU time 739.13 seconds
Started Jan 17 01:07:39 PM PST 24
Finished Jan 17 01:19:58 PM PST 24
Peak memory 200928 kb
Host smart-3b082131-3f86-4e52-8ab4-32a9db4b55cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171608509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.171608509
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.854436438
Short name T717
Test name
Test status
Simulation time 161573164770 ps
CPU time 95.55 seconds
Started Jan 17 01:07:38 PM PST 24
Finished Jan 17 01:09:14 PM PST 24
Peak memory 200840 kb
Host smart-f2444ec4-7905-4657-8610-673c69e34df0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=854436438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.854436438
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2489356909
Short name T839
Test name
Test status
Simulation time 329614534914 ps
CPU time 811.88 seconds
Started Jan 17 01:07:47 PM PST 24
Finished Jan 17 01:21:20 PM PST 24
Peak memory 200880 kb
Host smart-831669d7-3680-4d16-9ebc-d54f248f0ce7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489356909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2489356909
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3736852795
Short name T823
Test name
Test status
Simulation time 168340949204 ps
CPU time 59.38 seconds
Started Jan 17 01:07:45 PM PST 24
Finished Jan 17 01:08:48 PM PST 24
Peak memory 200872 kb
Host smart-1beddacd-d7a3-4e96-9282-393ddfe51aef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736852795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3736852795
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4149412851
Short name T494
Test name
Test status
Simulation time 61931710085 ps
CPU time 247.87 seconds
Started Jan 17 01:07:44 PM PST 24
Finished Jan 17 01:11:53 PM PST 24
Peak memory 201312 kb
Host smart-9d36ec27-f342-47a8-85e6-1b4f7efb93c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149412851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4149412851
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.831538992
Short name T715
Test name
Test status
Simulation time 31427312363 ps
CPU time 40.53 seconds
Started Jan 17 01:07:46 PM PST 24
Finished Jan 17 01:08:29 PM PST 24
Peak memory 200732 kb
Host smart-0037057e-2cc7-4cf4-8098-66a43d45a12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831538992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.831538992
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1367499308
Short name T480
Test name
Test status
Simulation time 3039471260 ps
CPU time 7.49 seconds
Started Jan 17 01:07:45 PM PST 24
Finished Jan 17 01:07:56 PM PST 24
Peak memory 200688 kb
Host smart-66dd5a0a-8bb2-45d8-846b-be9096dfbfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367499308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1367499308
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2542612437
Short name T656
Test name
Test status
Simulation time 5741113362 ps
CPU time 4.39 seconds
Started Jan 17 01:07:29 PM PST 24
Finished Jan 17 01:07:35 PM PST 24
Peak memory 200676 kb
Host smart-14f0c33d-a8b7-4d74-a292-93aeb76078ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542612437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2542612437
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2218097054
Short name T240
Test name
Test status
Simulation time 16922396943 ps
CPU time 42.82 seconds
Started Jan 17 01:07:44 PM PST 24
Finished Jan 17 01:08:29 PM PST 24
Peak memory 200992 kb
Host smart-0073b700-ef2c-4864-8962-d5bbb409721a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218097054 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2218097054
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1907478556
Short name T747
Test name
Test status
Simulation time 451727019 ps
CPU time 1.66 seconds
Started Jan 17 01:07:50 PM PST 24
Finished Jan 17 01:07:58 PM PST 24
Peak memory 200728 kb
Host smart-9a8433d9-0254-45fc-a0ec-71861001ab30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907478556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1907478556
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.4015044687
Short name T844
Test name
Test status
Simulation time 160809301676 ps
CPU time 94.25 seconds
Started Jan 17 01:07:52 PM PST 24
Finished Jan 17 01:09:31 PM PST 24
Peak memory 200868 kb
Host smart-2dcb1849-b36f-4de2-85a6-6691a665edd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015044687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.4015044687
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.385361385
Short name T205
Test name
Test status
Simulation time 162301328805 ps
CPU time 366.24 seconds
Started Jan 17 01:07:50 PM PST 24
Finished Jan 17 01:14:03 PM PST 24
Peak memory 200924 kb
Host smart-f1fb1f93-d5ce-4707-b7dc-0efb7c8788e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385361385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.385361385
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1115628733
Short name T312
Test name
Test status
Simulation time 325241401952 ps
CPU time 129.76 seconds
Started Jan 17 01:07:46 PM PST 24
Finished Jan 17 01:09:58 PM PST 24
Peak memory 200956 kb
Host smart-3d2ed8f5-8f65-4355-90b4-c72a7b0debc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115628733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1115628733
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2017095914
Short name T501
Test name
Test status
Simulation time 322901148178 ps
CPU time 694.02 seconds
Started Jan 17 01:07:44 PM PST 24
Finished Jan 17 01:19:21 PM PST 24
Peak memory 200892 kb
Host smart-4376462a-af14-4cd4-b061-6ed947b233dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017095914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2017095914
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1080914859
Short name T817
Test name
Test status
Simulation time 493363224692 ps
CPU time 1170.08 seconds
Started Jan 17 01:07:45 PM PST 24
Finished Jan 17 01:27:18 PM PST 24
Peak memory 200884 kb
Host smart-937e2c3b-0c33-498c-a9e5-2b20c4ce6a6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080914859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1080914859
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2004250118
Short name T539
Test name
Test status
Simulation time 498909133078 ps
CPU time 1155.13 seconds
Started Jan 17 01:07:50 PM PST 24
Finished Jan 17 01:27:12 PM PST 24
Peak memory 200880 kb
Host smart-6c63dcc8-c7aa-4d64-8a10-31f37c54133a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004250118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2004250118
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.819913645
Short name T400
Test name
Test status
Simulation time 30009462563 ps
CPU time 66.18 seconds
Started Jan 17 01:07:45 PM PST 24
Finished Jan 17 01:08:54 PM PST 24
Peak memory 200652 kb
Host smart-d4e44143-8230-437a-95d2-42575d89c211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819913645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.819913645
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1553704118
Short name T705
Test name
Test status
Simulation time 3338378881 ps
CPU time 7.82 seconds
Started Jan 17 01:07:46 PM PST 24
Finished Jan 17 01:07:56 PM PST 24
Peak memory 200728 kb
Host smart-86728183-c559-40e4-af6c-cb5a0f4563f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553704118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1553704118
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3550055056
Short name T60
Test name
Test status
Simulation time 5953017281 ps
CPU time 4.3 seconds
Started Jan 17 01:07:50 PM PST 24
Finished Jan 17 01:08:01 PM PST 24
Peak memory 200712 kb
Host smart-49428a45-4568-4193-8e74-629e83711789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550055056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3550055056
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.96092940
Short name T733
Test name
Test status
Simulation time 130272483057 ps
CPU time 129.36 seconds
Started Jan 17 01:07:49 PM PST 24
Finished Jan 17 01:10:06 PM PST 24
Peak memory 209592 kb
Host smart-f6aa0428-9d48-4635-8aed-1f54c170f5c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96092940 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.96092940
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2704102595
Short name T650
Test name
Test status
Simulation time 289701308 ps
CPU time 0.94 seconds
Started Jan 17 01:03:01 PM PST 24
Finished Jan 17 01:03:05 PM PST 24
Peak memory 200668 kb
Host smart-c22ad6ea-65b0-424b-b66d-da28c39877e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704102595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2704102595
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1913393601
Short name T237
Test name
Test status
Simulation time 328985284140 ps
CPU time 522.27 seconds
Started Jan 17 01:02:59 PM PST 24
Finished Jan 17 01:11:45 PM PST 24
Peak memory 200704 kb
Host smart-754bf5b4-caf2-478a-8fda-9d2d14e7206f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913393601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1913393601
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2493293409
Short name T860
Test name
Test status
Simulation time 167285649397 ps
CPU time 297.49 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:08:02 PM PST 24
Peak memory 200920 kb
Host smart-eeb51542-28e8-4703-a3de-4ab1d1858ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493293409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2493293409
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.4002542632
Short name T110
Test name
Test status
Simulation time 493687983601 ps
CPU time 305.44 seconds
Started Jan 17 01:03:01 PM PST 24
Finished Jan 17 01:08:09 PM PST 24
Peak memory 200936 kb
Host smart-2a73a7a2-e838-450f-89fb-3fdf2b2118b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002542632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4002542632
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2504404037
Short name T740
Test name
Test status
Simulation time 488450476262 ps
CPU time 1177.43 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:22:42 PM PST 24
Peak memory 200812 kb
Host smart-d595837c-179a-49e3-b7a1-5d001da3e4de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504404037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2504404037
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1977840182
Short name T308
Test name
Test status
Simulation time 160094231733 ps
CPU time 83.59 seconds
Started Jan 17 01:02:56 PM PST 24
Finished Jan 17 01:04:20 PM PST 24
Peak memory 200936 kb
Host smart-d94aeaeb-b6cb-4659-98bf-1b2bc6a94100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977840182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1977840182
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2125405953
Short name T552
Test name
Test status
Simulation time 328482182294 ps
CPU time 722.26 seconds
Started Jan 17 01:03:07 PM PST 24
Finished Jan 17 01:15:10 PM PST 24
Peak memory 200700 kb
Host smart-a917c486-4f4e-4151-adb5-abe7b12d2570
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125405953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2125405953
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3186154143
Short name T234
Test name
Test status
Simulation time 164472576317 ps
CPU time 35.93 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:03:39 PM PST 24
Peak memory 200956 kb
Host smart-f66a5a92-b462-4ebb-91e8-1bfc3382bba5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186154143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3186154143
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1836613644
Short name T246
Test name
Test status
Simulation time 165915940975 ps
CPU time 394.59 seconds
Started Jan 17 01:02:58 PM PST 24
Finished Jan 17 01:09:33 PM PST 24
Peak memory 200868 kb
Host smart-b4db0c28-24ca-48e5-a6e5-b293fba0c5ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836613644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1836613644
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.325756751
Short name T755
Test name
Test status
Simulation time 117842641502 ps
CPU time 437.11 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:10:22 PM PST 24
Peak memory 201376 kb
Host smart-2d0fd80a-c4c7-4913-8527-7833e06d3630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325756751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.325756751
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.850620273
Short name T796
Test name
Test status
Simulation time 34771423249 ps
CPU time 36.65 seconds
Started Jan 17 01:03:01 PM PST 24
Finished Jan 17 01:03:41 PM PST 24
Peak memory 200784 kb
Host smart-7bd91393-f9e1-4197-a2a8-deaf428e93c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850620273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.850620273
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1393298970
Short name T857
Test name
Test status
Simulation time 4262050972 ps
CPU time 10.69 seconds
Started Jan 17 01:03:00 PM PST 24
Finished Jan 17 01:03:14 PM PST 24
Peak memory 200676 kb
Host smart-0b075d83-2e6c-4f8f-8296-35447110d454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393298970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1393298970
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3665768473
Short name T515
Test name
Test status
Simulation time 5725787103 ps
CPU time 15.65 seconds
Started Jan 17 01:03:07 PM PST 24
Finished Jan 17 01:03:24 PM PST 24
Peak memory 200504 kb
Host smart-e383393e-92b1-459c-8887-6e080f1d1d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665768473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3665768473
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3362096859
Short name T158
Test name
Test status
Simulation time 34142073097 ps
CPU time 37.46 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:03:42 PM PST 24
Peak memory 200580 kb
Host smart-33cf771b-24a1-4092-973c-0d96f7247f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362096859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3362096859
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1286142981
Short name T148
Test name
Test status
Simulation time 151082577591 ps
CPU time 281.07 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:07:45 PM PST 24
Peak memory 209588 kb
Host smart-9c295919-9fff-4262-ad0a-caa036e641f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286142981 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1286142981
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1574162165
Short name T47
Test name
Test status
Simulation time 437322582 ps
CPU time 1.03 seconds
Started Jan 17 01:03:13 PM PST 24
Finished Jan 17 01:03:15 PM PST 24
Peak memory 200668 kb
Host smart-3ecbd637-2c05-4165-ac10-8fcf1a3b7ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574162165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1574162165
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.546239125
Short name T536
Test name
Test status
Simulation time 328960210251 ps
CPU time 745.92 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:15:30 PM PST 24
Peak memory 200876 kb
Host smart-12e717fb-a650-440e-844c-ffc440e3bdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546239125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.546239125
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2326163033
Short name T452
Test name
Test status
Simulation time 331734618212 ps
CPU time 757.57 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:15:42 PM PST 24
Peak memory 200812 kb
Host smart-77d1081d-90ee-4f73-80aa-196f32ab6024
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326163033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2326163033
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.243580296
Short name T163
Test name
Test status
Simulation time 331523127811 ps
CPU time 154.3 seconds
Started Jan 17 01:03:01 PM PST 24
Finished Jan 17 01:05:38 PM PST 24
Peak memory 200888 kb
Host smart-bfb10a1a-f288-4220-a228-a74142a06e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243580296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.243580296
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2674671716
Short name T427
Test name
Test status
Simulation time 327272692303 ps
CPU time 383.33 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:09:28 PM PST 24
Peak memory 200808 kb
Host smart-71152093-ebb3-495c-b978-a7e6c915c893
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674671716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2674671716
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.284997807
Short name T727
Test name
Test status
Simulation time 159797474791 ps
CPU time 350.33 seconds
Started Jan 17 01:03:02 PM PST 24
Finished Jan 17 01:08:55 PM PST 24
Peak memory 200740 kb
Host smart-d193cc86-0d1a-4336-be71-907a5fc17b7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284997807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.284997807
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.911830289
Short name T775
Test name
Test status
Simulation time 165608780813 ps
CPU time 98.38 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:04:43 PM PST 24
Peak memory 200872 kb
Host smart-1c0c8562-fad8-4566-ade7-3b86f49e8d6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911830289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.911830289
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3634972059
Short name T549
Test name
Test status
Simulation time 99221822694 ps
CPU time 525.74 seconds
Started Jan 17 01:03:10 PM PST 24
Finished Jan 17 01:11:58 PM PST 24
Peak memory 201256 kb
Host smart-6147addd-b922-49d5-aead-54806e654487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634972059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3634972059
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4293846253
Short name T846
Test name
Test status
Simulation time 31743383958 ps
CPU time 21.25 seconds
Started Jan 17 01:03:08 PM PST 24
Finished Jan 17 01:03:30 PM PST 24
Peak memory 200560 kb
Host smart-0fda5fcc-6c6c-44ff-88bb-25ba3bf2e411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293846253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4293846253
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.467630272
Short name T445
Test name
Test status
Simulation time 4377967787 ps
CPU time 11.02 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:03:16 PM PST 24
Peak memory 200740 kb
Host smart-64fefc23-98d2-4dec-8650-438773ccebf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467630272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.467630272
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4142373576
Short name T734
Test name
Test status
Simulation time 6034224702 ps
CPU time 15.11 seconds
Started Jan 17 01:03:03 PM PST 24
Finished Jan 17 01:03:20 PM PST 24
Peak memory 200676 kb
Host smart-864eba0f-9e81-452f-baaf-aa9e3c29eaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142373576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4142373576
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2162835954
Short name T695
Test name
Test status
Simulation time 333657421432 ps
CPU time 416.76 seconds
Started Jan 17 01:03:10 PM PST 24
Finished Jan 17 01:10:09 PM PST 24
Peak memory 200880 kb
Host smart-df3fd4c4-3c32-4807-b0bd-b4c86e2055fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162835954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2162835954
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2223635367
Short name T663
Test name
Test status
Simulation time 332880706 ps
CPU time 0.81 seconds
Started Jan 17 01:03:09 PM PST 24
Finished Jan 17 01:03:11 PM PST 24
Peak memory 200664 kb
Host smart-6bc8380e-614c-43ac-8cd0-8806b88be889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223635367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2223635367
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.490972077
Short name T294
Test name
Test status
Simulation time 161252439258 ps
CPU time 389.91 seconds
Started Jan 17 01:03:07 PM PST 24
Finished Jan 17 01:09:38 PM PST 24
Peak memory 200932 kb
Host smart-8c945e47-626e-468f-b52f-d6e3aea749c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490972077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.490972077
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.119228177
Short name T485
Test name
Test status
Simulation time 327782566904 ps
CPU time 191.23 seconds
Started Jan 17 01:03:05 PM PST 24
Finished Jan 17 01:06:17 PM PST 24
Peak memory 200884 kb
Host smart-ed0574fb-8299-4617-bed6-263655aafbd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=119228177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.119228177
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2345121681
Short name T785
Test name
Test status
Simulation time 338862951899 ps
CPU time 204.68 seconds
Started Jan 17 01:03:15 PM PST 24
Finished Jan 17 01:06:46 PM PST 24
Peak memory 200160 kb
Host smart-050f16bc-dc1d-474a-aced-caee75a30404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345121681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2345121681
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1211450550
Short name T798
Test name
Test status
Simulation time 162811678846 ps
CPU time 80.77 seconds
Started Jan 17 01:03:07 PM PST 24
Finished Jan 17 01:04:28 PM PST 24
Peak memory 200844 kb
Host smart-20ae03cd-e483-43b4-bfdd-2b81c07beb5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211450550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1211450550
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2519052607
Short name T590
Test name
Test status
Simulation time 165679501763 ps
CPU time 213.67 seconds
Started Jan 17 01:03:08 PM PST 24
Finished Jan 17 01:06:43 PM PST 24
Peak memory 200880 kb
Host smart-0cf2d535-fc38-46c0-ad6b-6c017a143f61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519052607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2519052607
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1146686766
Short name T562
Test name
Test status
Simulation time 485552076504 ps
CPU time 280.86 seconds
Started Jan 17 01:03:14 PM PST 24
Finished Jan 17 01:08:01 PM PST 24
Peak memory 201084 kb
Host smart-1960903c-d398-4e44-bafa-013b00566e71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146686766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1146686766
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2334601661
Short name T177
Test name
Test status
Simulation time 80633142509 ps
CPU time 257.53 seconds
Started Jan 17 01:03:13 PM PST 24
Finished Jan 17 01:07:32 PM PST 24
Peak memory 201312 kb
Host smart-285700f8-e2ad-4b16-9d21-82a70d61e2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334601661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2334601661
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3325161673
Short name T504
Test name
Test status
Simulation time 35383744907 ps
CPU time 59.6 seconds
Started Jan 17 01:03:14 PM PST 24
Finished Jan 17 01:04:20 PM PST 24
Peak memory 200948 kb
Host smart-74d18562-4fed-4a78-aca4-91242b2aa679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325161673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3325161673
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2762356934
Short name T842
Test name
Test status
Simulation time 4974193435 ps
CPU time 1.41 seconds
Started Jan 17 01:03:15 PM PST 24
Finished Jan 17 01:03:22 PM PST 24
Peak memory 199928 kb
Host smart-9c101513-af90-44dc-b27a-024b28e4086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762356934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2762356934
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.370279788
Short name T453
Test name
Test status
Simulation time 5925895696 ps
CPU time 3.75 seconds
Started Jan 17 01:03:10 PM PST 24
Finished Jan 17 01:03:16 PM PST 24
Peak memory 200668 kb
Host smart-c8760d70-aa46-45d5-90c0-8a3d7b142385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370279788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.370279788
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2837333840
Short name T338
Test name
Test status
Simulation time 460045582722 ps
CPU time 1993.2 seconds
Started Jan 17 01:03:09 PM PST 24
Finished Jan 17 01:36:24 PM PST 24
Peak memory 201320 kb
Host smart-2051d36a-d6ac-4aea-a2a2-d8d822593d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837333840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2837333840
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3205853674
Short name T185
Test name
Test status
Simulation time 56964624821 ps
CPU time 212.85 seconds
Started Jan 17 01:03:09 PM PST 24
Finished Jan 17 01:06:43 PM PST 24
Peak memory 209524 kb
Host smart-e87ba931-c4a1-402e-8808-107de08d70be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205853674 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3205853674
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2242816189
Short name T476
Test name
Test status
Simulation time 340057331 ps
CPU time 0.83 seconds
Started Jan 17 01:03:12 PM PST 24
Finished Jan 17 01:03:14 PM PST 24
Peak memory 200652 kb
Host smart-6b6085b2-29ae-4ba5-aac2-98254ea3cd66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242816189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2242816189
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2176619351
Short name T318
Test name
Test status
Simulation time 495751147776 ps
CPU time 377.22 seconds
Started Jan 17 01:03:18 PM PST 24
Finished Jan 17 01:09:38 PM PST 24
Peak memory 200840 kb
Host smart-71d80572-e8e2-4933-af32-db0d4a124e10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176619351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2176619351
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.455809171
Short name T274
Test name
Test status
Simulation time 327343856821 ps
CPU time 293.47 seconds
Started Jan 17 01:03:10 PM PST 24
Finished Jan 17 01:08:06 PM PST 24
Peak memory 200916 kb
Host smart-e5aa326e-1803-4351-b867-2bc65088925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455809171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.455809171
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3596589856
Short name T286
Test name
Test status
Simulation time 498550435969 ps
CPU time 293.44 seconds
Started Jan 17 01:03:10 PM PST 24
Finished Jan 17 01:08:06 PM PST 24
Peak memory 200960 kb
Host smart-b0981bf0-d8ef-4ca8-a2e7-fc02c516f818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596589856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3596589856
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3869924672
Short name T704
Test name
Test status
Simulation time 323075084992 ps
CPU time 776.78 seconds
Started Jan 17 01:03:14 PM PST 24
Finished Jan 17 01:16:18 PM PST 24
Peak memory 200800 kb
Host smart-2bdf7bda-9ccc-4560-9eb9-b50cbd220f4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869924672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3869924672
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3323621840
Short name T687
Test name
Test status
Simulation time 170010174057 ps
CPU time 178.15 seconds
Started Jan 17 01:03:14 PM PST 24
Finished Jan 17 01:06:18 PM PST 24
Peak memory 200816 kb
Host smart-4c06de3f-8f44-4b44-811e-520919806c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323621840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3323621840
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1919096019
Short name T514
Test name
Test status
Simulation time 331112917552 ps
CPU time 747.88 seconds
Started Jan 17 01:03:14 PM PST 24
Finished Jan 17 01:15:48 PM PST 24
Peak memory 200736 kb
Host smart-14d5ec41-73ab-42ef-93c0-6b24f5b71de0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919096019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1919096019
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3281254873
Short name T836
Test name
Test status
Simulation time 495458199052 ps
CPU time 263.97 seconds
Started Jan 17 01:03:09 PM PST 24
Finished Jan 17 01:07:35 PM PST 24
Peak memory 200856 kb
Host smart-68819e28-6fb7-4f40-baec-6c8580382ead
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281254873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3281254873
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2312493706
Short name T726
Test name
Test status
Simulation time 328743171559 ps
CPU time 262.59 seconds
Started Jan 17 01:03:09 PM PST 24
Finished Jan 17 01:07:34 PM PST 24
Peak memory 200848 kb
Host smart-02d598ce-8bff-4d5d-9f5c-c8e0927a3fbb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312493706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2312493706
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.865405746
Short name T189
Test name
Test status
Simulation time 120951824326 ps
CPU time 356.96 seconds
Started Jan 17 01:03:09 PM PST 24
Finished Jan 17 01:09:09 PM PST 24
Peak memory 201240 kb
Host smart-3259291b-4c13-49f9-951c-c480be001406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865405746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.865405746
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1391666020
Short name T635
Test name
Test status
Simulation time 35042065990 ps
CPU time 74.74 seconds
Started Jan 17 01:03:09 PM PST 24
Finished Jan 17 01:04:25 PM PST 24
Peak memory 200788 kb
Host smart-92d6e4f7-2d4a-4656-9f83-55b5eea39856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391666020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1391666020
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3649680025
Short name T805
Test name
Test status
Simulation time 5471685896 ps
CPU time 3.84 seconds
Started Jan 17 01:03:18 PM PST 24
Finished Jan 17 01:03:25 PM PST 24
Peak memory 200720 kb
Host smart-de63c9ad-4d1a-4348-a432-f713c6d3cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649680025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3649680025
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.183470497
Short name T526
Test name
Test status
Simulation time 5796613493 ps
CPU time 15.36 seconds
Started Jan 17 01:03:14 PM PST 24
Finished Jan 17 01:03:36 PM PST 24
Peak memory 200720 kb
Host smart-008931fd-7bf2-40d7-81f2-3fa3ef85aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183470497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.183470497
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.4085319613
Short name T568
Test name
Test status
Simulation time 174136072943 ps
CPU time 101.73 seconds
Started Jan 17 01:03:10 PM PST 24
Finished Jan 17 01:04:54 PM PST 24
Peak memory 200788 kb
Host smart-3da1caad-7c4e-4715-b120-8abe8e78b222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085319613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
4085319613
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1442810621
Short name T220
Test name
Test status
Simulation time 63067926066 ps
CPU time 247.01 seconds
Started Jan 17 01:03:11 PM PST 24
Finished Jan 17 01:07:20 PM PST 24
Peak memory 209568 kb
Host smart-ecf3e699-bd75-4f53-812c-92655de6ca13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442810621 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1442810621
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3831342959
Short name T410
Test name
Test status
Simulation time 378995564 ps
CPU time 1.09 seconds
Started Jan 17 01:03:18 PM PST 24
Finished Jan 17 01:03:22 PM PST 24
Peak memory 200616 kb
Host smart-be9eaece-0f6a-4461-b6a2-aad7cc24f9dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831342959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3831342959
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1669815554
Short name T553
Test name
Test status
Simulation time 162386906095 ps
CPU time 12.56 seconds
Started Jan 17 01:03:19 PM PST 24
Finished Jan 17 01:03:34 PM PST 24
Peak memory 200864 kb
Host smart-0172f06e-26bf-4316-be08-e0f434ed5f85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669815554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1669815554
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3018101345
Short name T303
Test name
Test status
Simulation time 331150570290 ps
CPU time 745.07 seconds
Started Jan 17 01:03:16 PM PST 24
Finished Jan 17 01:15:46 PM PST 24
Peak memory 200880 kb
Host smart-da37b65b-6308-49ba-b911-1583823f13df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018101345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3018101345
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.628977839
Short name T633
Test name
Test status
Simulation time 166842444699 ps
CPU time 34.71 seconds
Started Jan 17 01:03:13 PM PST 24
Finished Jan 17 01:03:49 PM PST 24
Peak memory 200764 kb
Host smart-6f327a35-185c-4e52-be83-7a374fed081c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=628977839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.628977839
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2572824517
Short name T768
Test name
Test status
Simulation time 497772707280 ps
CPU time 170.07 seconds
Started Jan 17 01:03:13 PM PST 24
Finished Jan 17 01:06:10 PM PST 24
Peak memory 200924 kb
Host smart-7d64e3a4-7049-4e80-a464-4002e588be1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572824517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2572824517
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.302843547
Short name T543
Test name
Test status
Simulation time 488641900464 ps
CPU time 104.09 seconds
Started Jan 17 01:04:22 PM PST 24
Finished Jan 17 01:06:07 PM PST 24
Peak memory 200864 kb
Host smart-50452ff6-9bec-4bbc-943c-37c06dcbaf11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=302843547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.302843547
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.670080052
Short name T506
Test name
Test status
Simulation time 506135121347 ps
CPU time 548.14 seconds
Started Jan 17 01:03:12 PM PST 24
Finished Jan 17 01:12:21 PM PST 24
Peak memory 200884 kb
Host smart-1c8f030c-434c-40e0-8bee-07908edce405
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670080052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.670080052
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.4083886437
Short name T711
Test name
Test status
Simulation time 336242106901 ps
CPU time 653.99 seconds
Started Jan 17 01:03:21 PM PST 24
Finished Jan 17 01:14:16 PM PST 24
Peak memory 200856 kb
Host smart-1ab53dc3-0dc8-41eb-87f7-0d0a0e17b337
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083886437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.4083886437
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3224311247
Short name T699
Test name
Test status
Simulation time 97311655429 ps
CPU time 313.62 seconds
Started Jan 17 01:03:19 PM PST 24
Finished Jan 17 01:08:35 PM PST 24
Peak memory 201372 kb
Host smart-01fabe80-6341-42fa-9b39-a15ca33243bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224311247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3224311247
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2809601371
Short name T641
Test name
Test status
Simulation time 23948519089 ps
CPU time 8.93 seconds
Started Jan 17 01:03:17 PM PST 24
Finished Jan 17 01:03:30 PM PST 24
Peak memory 200688 kb
Host smart-361abe5e-0fcc-4247-8e40-0734c086017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809601371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2809601371
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1677250224
Short name T458
Test name
Test status
Simulation time 4816235926 ps
CPU time 6.44 seconds
Started Jan 17 01:03:17 PM PST 24
Finished Jan 17 01:03:27 PM PST 24
Peak memory 200716 kb
Host smart-c7767539-6c29-437c-902c-32604ad085c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677250224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1677250224
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.592297855
Short name T508
Test name
Test status
Simulation time 6059334349 ps
CPU time 2.17 seconds
Started Jan 17 01:03:16 PM PST 24
Finished Jan 17 01:03:23 PM PST 24
Peak memory 200668 kb
Host smart-0bc19753-fbd1-4727-a270-7a2a61fd40bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592297855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.592297855
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2265476547
Short name T319
Test name
Test status
Simulation time 293244628328 ps
CPU time 673.87 seconds
Started Jan 17 01:03:18 PM PST 24
Finished Jan 17 01:14:35 PM PST 24
Peak memory 209520 kb
Host smart-ff6ea152-2c52-4014-ab11-1fb3c42ec61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265476547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2265476547
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.457389066
Short name T674
Test name
Test status
Simulation time 68029763950 ps
CPU time 43.15 seconds
Started Jan 17 01:03:16 PM PST 24
Finished Jan 17 01:04:04 PM PST 24
Peak memory 201004 kb
Host smart-33bb0ab0-398b-4306-8ba2-7673447431ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457389066 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.457389066
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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