Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6205	1			T9	8		T16	20		T19	47
testmodes[AdcCtrlTestmodeNormal]	4938	1			T9	3		T10	4		T11	1
testmodes[AdcCtrlTestmodeLowpower]	5147	1			T10	1		T11	20		T12	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3408	1			T9	5		T16	19		T19	20
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1519	1			T9	3		T19	19		T83	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1170	1			T19	7		T33	17		T169	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1520	1			T9	2		T19	18		T83	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1834	1			T10	3		T12	2		T14	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1234	1			T12	1		T19	12		T106	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1162	1			T19	9		T33	18		T169	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1247	1			T10	1		T11	1		T12	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2507	1			T11	19		T17	11		T19	16