Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20576

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3446

1

T10

33

T14

1

T20

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18326

1

T31

1

T32

1

T38

2

auto[1]

5696

1

T10

14

T11

13

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	41	1			T10	14		T46	17		T202	10
values[0]	75	1			T105	11		T203	11		T204	22
values[1]	549	1			T118	1		T120	14		T107	1
values[2]	598	1			T205	22		T100	19		T206	2
values[3]	690	1			T11	13		T21	1		T119	1
values[4]	699	1			T170	1		T115	1		T169	3
values[5]	707	1			T10	19		T12	12		T14	1
values[6]	739	1			T21	1		T53	16		T170	1
values[7]	535	1			T14	1		T20	3		T21	1
values[8]	2853	1			T13	1		T18	3		T106	11
values[9]	1206	1			T19	2		T20	21		T53	12
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	735	1			T118	1		T120	14		T100	19
values[1]	619	1			T206	2		T89	29		T151	12
values[2]	756	1			T11	13		T21	1		T119	1
values[3]	741	1			T15	5		T52	1		T118	1
values[4]	693	1			T10	19		T12	12		T14	1
values[5]	621	1			T21	1		T120	9		T207	30
values[6]	2760	1			T13	1		T14	1		T18	3
values[7]	691	1			T205	26		T89	11		T169	2
values[8]	874	1			T19	2		T20	21		T53	12
values[9]	196	1			T10	14		T103	23		T132	9
minimum	15336	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T118	1		T100	13		T147	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T120	8		T107	1		T104	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T206	2		T89	15		T151	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T108	10		T93	1		T109	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	11		T21	1		T208	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T119	1		T205	12		T102	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T118	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T52	1		T119	1		T99	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	10		T52	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	12		T14	1		T207	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	1		T120	5		T116	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T207	14		T90	12		T151	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T13	1		T14	1		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T169	1		T110	3		T209	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T89	11		T185	3		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T205	12		T169	1		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T19	1		T53	1		T106	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T20	10		T106	9		T99	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T103	12		T93	1		T124	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T10	7		T132	9		T46	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15220	1			T9	11		T11	20		T16	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T100	6		T130	3		T140	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T120	6		T104	8		T105	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T89	14		T92	10		T105	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T108	10		T210	11		T211	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	2		T132	16		T48	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T205	10		T142	14		T46	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	4		T89	5		T169	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T99	8		T212	7		T135	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	2		T53	15		T124	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	7		T207	6		T102	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T120	4		T108	7		T117	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T207	16		T90	13		T43	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1120	1			T20	2		T83	7		T106	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T169	1		T110	6		T209	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T185	2		T213	2		T214	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T205	14		T169	1		T215	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T19	1		T53	11		T106	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T20	11		T106	2		T99	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T103	11		T93	13		T124	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T10	7		T46	4		T216	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T31	1		T32	1		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T10	7		T46	13		T202	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T203	11		T217	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T105	6		T204	12		T218	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T118	1		T89	15		T147	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T120	8		T107	1		T104	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T100	13		T206	2		T151	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T205	12		T109	10		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	11		T21	1		T208	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T119	1		T99	5		T108	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T170	1		T115	1		T169	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T135	1		T102	2		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	10		T15	1		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	12		T14	1		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T21	1		T53	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T207	14		T90	12		T151	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T14	1		T20	1		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T169	1		T209	13		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T13	1		T18	3		T106	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T205	12		T169	1		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T19	1		T53	1		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T20	10		T106	9		T99	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T10	7		T46	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T105	5		T204	10		T218	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T89	14		T103	2		T130	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T120	6		T104	8		T105	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T100	6		T105	7		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T205	10		T111	3		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	2		T92	10		T185	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T99	8		T108	10		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T169	1		T108	7		T132	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T135	13		T110	1		T175	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	2		T15	4		T120	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	7		T207	6		T212	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T53	15		T108	7		T117	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T207	16		T90	13		T110	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T20	2		T83	7		T104	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T169	1		T209	2		T175	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T106	8		T219	12		T150	29
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T205	14		T169	1		T164	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T19	1		T53	11		T106	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T20	11		T106	2		T99	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T118	1		T100	7		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T120	7		T107	1		T104	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T206	1		T89	15		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T108	11		T93	1		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	3		T21	1		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T119	1		T205	11		T102	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	5		T118	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T52	1		T119	1		T99	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	7		T52	1		T53	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	10		T14	1		T207	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T21	1		T120	5		T116	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T207	17		T90	14		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T13	1		T14	1		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T169	2		T110	8		T209	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T89	1		T185	4		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T205	15		T169	2		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T19	2		T53	12		T106	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T20	12		T106	3		T99	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T103	13		T93	14		T124	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T10	9		T132	1		T46	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15336	1			T31	1		T32	1		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T100	12		T147	2		T101	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T120	7		T105	10		T220	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T206	1		T89	14		T151	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T108	9		T109	9		T221	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	10		T208	2		T117	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T205	11		T142	13		T221	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T89	3		T169	1		T108	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T99	4		T212	8		T124	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	5		T124	6		T222	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	9		T207	7		T223	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T120	4		T108	11		T117	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T207	13		T90	11		T151	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T83	2		T106	2		T224	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T110	1		T209	12		T46	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T89	10		T185	1		T213	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T205	11		T215	5		T112	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T106	5		T100	6		T140	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T20	9		T106	8		T99	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T103	10		T124	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T10	5		T132	8		T46	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T10	9		T46	5		T202	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T203	1		T217	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T105	6		T204	11		T218	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T118	1		T89	15		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T120	7		T107	1		T104	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T100	7		T206	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T205	11		T109	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	3		T21	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T119	1		T99	9		T108	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T170	1		T115	1		T169	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T135	14		T102	2		T110	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	7		T15	5		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	10		T14	1		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T21	1		T53	16		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T207	17		T90	14		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	1		T20	3		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T169	2		T209	3		T175	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T13	1		T18	3		T106	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T205	15		T169	2		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T19	2		T53	12		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T20	12		T106	3		T99	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T10	5		T46	12		T202	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T203	10		T217	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T105	5		T204	11		T218	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T89	14		T147	2		T101	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T120	7		T105	5		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T100	12		T206	1		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T205	11		T109	9		T225	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	10		T208	2		T92	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T99	4		T108	9		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T169	1		T108	7		T132	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T124	2		T222	5		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	5		T120	4		T89	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	9		T207	7		T212	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T108	11		T117	5		T110	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T207	13		T90	11		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T83	2		T214	12		T227	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T209	12		T46	13		T210	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T106	2		T224	12		T174	30
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T205	11		T164	13		T215	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T106	5		T100	6		T89	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T20	9		T106	8		T99	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19025

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

4997

1

T10

33

T11

13

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18431

1

T31

1

T32

1

T38

2

auto[1]

5591

1

T10

14

T12

12

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T14	1		T91	1		T228	14
values[0]	45	1			T129	1		T229	12		T230	11
values[1]	734	1			T120	14		T100	13		T89	11
values[2]	687	1			T83	13		T53	16		T106	11
values[3]	550	1			T19	2		T119	1		T107	1
values[4]	540	1			T21	1		T118	1		T89	38
values[5]	623	1			T120	9		T100	19		T206	2
values[6]	658	1			T12	12		T20	3		T52	2
values[7]	685	1			T10	14		T21	1		T170	1
values[8]	637	1			T10	19		T15	5		T53	12
values[9]	3513	1			T11	13		T13	1		T14	1
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1066	1			T83	13		T53	16		T119	1
values[1]	2677	1			T13	1		T18	3		T106	11
values[2]	544	1			T19	2		T107	1		T89	9
values[3]	632	1			T21	1		T118	1		T120	9
values[4]	471	1			T20	3		T52	1		T170	1
values[5]	782	1			T10	14		T12	12		T52	1
values[6]	630	1			T15	5		T21	1		T106	11
values[7]	723	1			T10	19		T20	21		T53	12
values[8]	832	1			T14	2		T21	1		T106	11
values[9]	334	1			T11	13		T90	25		T135	14
minimum	15331	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T83	6		T120	8		T99	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T53	1		T119	1		T207	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T99	5		T205	24		T103	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1368	1			T13	1		T18	3		T106	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T19	1		T107	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T89	4		T208	3		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T21	1		T118	1		T120	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T89	15		T151	12		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T20	1		T52	1		T206	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T170	1		T169	2		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	10		T52	1		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	7		T170	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T21	1		T107	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	1		T106	3		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T20	10		T101	19		T124	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	12		T53	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T14	1		T118	1		T151	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	1		T21	1		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T105	6		T50	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T11	11		T90	12		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T232	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T83	7		T120	6		T99	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T53	15		T207	6		T100	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T99	8		T205	24		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1028	1			T106	2		T219	12		T150	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	1		T131	1		T132	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T89	5		T140	1		T96	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T120	4		T100	6		T110	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T89	14		T215	6		T233	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T20	2		T105	9		T110	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T169	1		T121	16		T185	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	2		T135	4		T103	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	7		T169	1		T102	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T164	10		T93	14		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	4		T106	8		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T20	11		T124	14		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	7		T53	11		T169	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T130	3		T117	16		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T106	5		T207	16		T212	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T105	5		T50	11		T235	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T11	2		T90	13		T135	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T14	1		T91	1		T228	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T129	1		T229	1		T230	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T236	9		T237	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T120	8		T238	1		T108	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T100	7		T89	11		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T83	6		T99	21		T205	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T53	1		T106	9		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T19	1		T107	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T119	1		T208	3		T108	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T21	1		T118	1		T117	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T89	19		T151	12		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T120	5		T100	13		T206	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T169	3		T121	1		T185	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	10		T20	1		T52	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T170	1		T115	1		T147	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T21	1		T107	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T10	7		T170	1		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T101	19		T137	1		T164	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	12		T15	1		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	439	1			T14	1		T20	10		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1504	1			T11	11		T13	1		T18	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T228	13		T239	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T229	11		T230	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T236	7		T237	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T120	6		T108	10		T97	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T100	6		T175	11		T48	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T83	7		T99	23		T205	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T53	15		T106	2		T207	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T19	1		T131	1		T240	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T108	7		T209	2		T46	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T132	16		T110	6		T43	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T89	19		T140	1		T96	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T120	4		T100	6		T105	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T169	2		T121	16		T185	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	2		T20	2		T135	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	10		T93	13		T214	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T93	14		T43	15		T234	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	7		T102	1		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T164	10		T124	14		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	7		T15	4		T53	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T20	11		T105	5		T130	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1245	1			T11	2		T106	5		T207	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2