Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20768

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3254

1

T10

14

T14

2

T19

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18584

1

T31

1

T32

1

T38

2

auto[1]

5438

1

T10

33

T11

13

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	286	1			T53	16		T170	1		T107	1
values[0]	20	1			T102	2		T103	6		T302	12
values[1]	655	1			T11	13		T15	5		T21	2
values[2]	755	1			T205	22		T100	19		T116	1
values[3]	738	1			T21	1		T119	1		T148	1
values[4]	543	1			T12	12		T52	1		T106	11
values[5]	2809	1			T13	1		T14	1		T18	3
values[6]	565	1			T10	19		T170	1		T205	26
values[7]	779	1			T118	1		T120	9		T170	1
values[8]	582	1			T106	11		T100	13		T151	12
values[9]	960	1			T10	14		T14	1		T19	2
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	585	1			T11	13		T21	1		T106	11
values[1]	741	1			T21	1		T205	22		T100	19
values[2]	715	1			T12	12		T52	1		T106	11
values[3]	2715	1			T13	1		T18	3		T224	13
values[4]	672	1			T14	1		T118	1		T207	30
values[5]	634	1			T10	19		T118	1		T170	2
values[6]	671	1			T120	9		T207	14		T99	13
values[7]	621	1			T20	24		T106	11		T89	9
values[8]	950	1			T10	14		T14	1		T83	13
values[9]	129	1			T19	2		T241	23		T177	1
minimum	15589	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	11		T21	1		T106	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T115	1		T208	3		T91	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T21	1		T205	12		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T100	13		T116	1		T169	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	10		T52	1		T106	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T101	19		T140	1		T142	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T13	1		T18	3		T224	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T107	1		T115	1		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T135	1		T91	1		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	1		T118	1		T207	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	12		T118	1		T170	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T89	15		T223	13		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T120	5		T100	7		T108	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T207	8		T99	5		T212	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T20	11		T106	9		T89	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T169	1		T91	1		T117	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T53	1		T120	8		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T10	7		T14	1		T83	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T241	10		T177	1		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T19	1		T305	4		T314	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15295	1			T9	11		T11	20		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T21	1		T147	3		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	2		T106	5		T121	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T175	13		T123	7		T124	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T205	10		T108	10		T103	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T100	6		T169	1		T135	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	2		T106	8		T93	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T140	1		T311	3		T233	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T219	12		T150	29		T271	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T108	7		T103	4		T240	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T135	13		T140	8		T124	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T207	16		T104	8		T131	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	7		T205	14		T169	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T89	14		T104	14		T209	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T120	4		T100	6		T108	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T207	6		T99	8		T212	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T20	13		T106	2		T89	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T169	1		T142	14		T124	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T53	15		T120	6		T92	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T10	7		T83	7		T53	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T241	13		T229	11		T313	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T19	1		T305	1		T314	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T46	5		T302	6		T308	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T53	1		T107	1		T241	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T170	1		T130	1		T109	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T102	2		T103	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T302	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	11		T15	1		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T21	1		T115	1		T147	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T205	12		T108	10		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T100	13		T116	1		T208	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T21	1		T119	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T169	2		T101	19		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	10		T52	1		T106	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T115	1		T238	1		T108	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T13	1		T18	3		T224	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	1		T118	1		T207	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	12		T170	1		T205	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T223	13		T104	1		T96	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T118	1		T120	5		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T207	8		T99	5		T89	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T106	9		T100	7		T151	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T169	1		T117	2		T132	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T20	11		T120	8		T89	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	7		T14	1		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T53	15		T241	13		T316	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T130	3		T323	6		T253	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T103	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T302	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	2		T15	4		T106	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T175	13		T123	7		T46	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T205	10		T108	10		T103	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T100	6		T135	4		T105	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T93	14		T185	1		T175	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T169	1		T140	1		T127	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	2		T106	8		T265	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T108	7		T103	4		T104	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T219	12		T150	29		T271	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T207	16		T131	1		T50	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	7		T205	14		T135	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T104	14		T96	5		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T120	4		T169	1		T105	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T207	6		T99	8		T89	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T106	2		T100	6		T108	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T169	1		T142	14		T112	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T20	13		T120	6		T89	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	7		T19	1		T83	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	3		T21	1		T106	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T115	1		T208	1		T91	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T21	1		T205	11		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T100	7		T116	1		T169	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	7		T52	1		T106	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T101	1		T140	2		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T13	1		T18	3		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T107	1		T115	1		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T135	14		T91	1		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	1		T118	1		T207	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	10		T118	1		T170	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T89	15		T223	1		T104	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T120	5		T100	7		T108	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T207	7		T99	9		T212	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T20	15		T106	3		T89	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T169	2		T91	1		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T53	16		T120	7		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T10	9		T14	1		T83	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T241	14		T177	1		T229	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T19	2		T305	4		T314	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15421	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T21	1		T147	1		T46	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	10		T106	5		T110	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T208	2		T123	6		T124	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T205	11		T108	9		T103	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T100	12		T169	1		T135	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	5		T106	2		T222	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T101	18		T142	3		T233	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T224	12		T206	1		T89	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T108	11		T103	7		T210	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T140	1		T124	12		T300	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T207	13		T96	2		T112	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	9		T205	11		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T89	14		T223	12		T209	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T120	4		T100	6		T108	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T207	7		T99	4		T212	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T20	9		T106	8		T89	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T117	1		T132	8		T249	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T120	7		T92	4		T46	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	5		T83	2		T117	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T241	9		T313	6		T324	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T305	1		T314	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T99	15		T90	11		T265	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T147	2		T304	11		T302	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T53	16		T107	1		T241	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T170	1		T130	4		T109	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T102	2		T103	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T302	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	3		T15	5		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T21	1		T115	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T205	11		T108	11		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T100	7		T116	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T21	1		T119	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T169	2		T101	1		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	7		T52	1		T106	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T115	1		T238	1		T108	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T13	1		T18	3		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	1		T118	1		T207	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	10		T170	1		T205	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T223	1		T104	15		T96	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T118	1		T120	5		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T207	7		T99	9		T89	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T106	3		T100	7		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T169	2		T117	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T20	15		T120	7		T89	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T10	9		T14	1		T19	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T241	9		T293	2		T252	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T109	9		T253	13		T312	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T302	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	10		T106	5		T99	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T147	2		T123	6		T46	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T205	11		T108	9		T103	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T100	12		T208	2		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T222	5		T234	19		T210	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T169	1		T101	18		T235	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	5		T106	2		T206	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T108	11		T103	7		T142	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T224	12		T89	10		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T207	13		T112	6		T210	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	9		T205	11		T226	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T223	12		T96	2		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T120	4		T105	10		T117	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T207	7		T99	4		T89	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T106	8		T100	6		T151	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T117	1		T132	8		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T20	9		T120	7		T89	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	5		T83	2		T117	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5