Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20610

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3412

1

T10

33

T14

1

T20

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18310

1

T31

1

T32

1

T38

2

auto[1]

5712

1

T10

14

T11

13

T12

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	318	1			T99	31		T100	13		T238	1
values[0]	24	1			T105	11		T291	11		T217	2
values[1]	564	1			T118	1		T100	19		T107	1
values[2]	624	1			T120	14		T206	2		T89	29
values[3]	725	1			T11	13		T21	1		T119	1
values[4]	670	1			T170	1		T115	1		T169	3
values[5]	696	1			T10	19		T12	12		T14	1
values[6]	751	1			T21	1		T53	16		T170	1
values[7]	567	1			T14	1		T20	3		T21	1
values[8]	2798	1			T13	1		T18	3		T106	11
values[9]	955	1			T10	14		T19	2		T20	21
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	588	1			T118	1		T120	14		T100	19
values[1]	605	1			T206	2		T89	29		T151	12
values[2]	831	1			T11	13		T21	1		T119	1
values[3]	646	1			T52	1		T118	1		T119	1
values[4]	719	1			T10	19		T12	12		T14	1
values[5]	683	1			T21	1		T83	13		T170	1
values[6]	2731	1			T13	1		T14	1		T18	3
values[7]	658	1			T205	26		T89	11		T169	2
values[8]	987	1			T10	14		T19	2		T20	21
values[9]	96	1			T135	17		T103	23		T131	7
minimum	15478	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T118	1		T100	13		T147	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T120	8		T107	1		T105	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T206	2		T151	12		T92	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T89	15		T108	10		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	11		T21	1		T99	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T119	1		T205	12		T102	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T118	1		T170	1		T89	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T52	1		T119	1		T212	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	10		T15	1		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	12		T14	1		T207	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T21	1		T83	6		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T207	14		T90	12		T151	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T13	1		T14	1		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T169	1		T209	13		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T89	11		T140	9		T185	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T205	12		T169	1		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T19	1		T53	1		T106	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T10	7		T20	10		T106	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T103	12		T131	6		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T135	13		T132	9		T325	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15264	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T104	1		T105	6		T311	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T100	6		T103	2		T130	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T120	6		T105	9		T269	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T92	10		T105	7		T140	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T89	14		T108	10		T210	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	2		T99	8		T132	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T205	10		T175	10		T240	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T89	5		T169	1		T108	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T212	7		T135	13		T110	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	2		T15	4		T53	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	7		T207	6		T102	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T83	7		T108	7		T117	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T207	16		T90	13		T110	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T20	2		T106	8		T219	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T169	1		T209	2		T175	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T140	7		T185	2		T213	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T205	14		T169	1		T215	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T19	1		T53	11		T106	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T10	7		T20	11		T106	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T103	11		T131	1		T93	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T135	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T104	8		T105	5		T311	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T100	7		T238	1		T93	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T99	16		T135	13		T121	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T291	11		T217	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T105	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T118	1		T100	13		T147	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T107	1		T104	1		T105	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T206	2		T151	12		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T120	8		T89	15		T109	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	11		T21	1		T99	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T119	1		T205	12		T108	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T170	1		T115	1		T169	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T135	1		T102	2		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	10		T15	1		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	12		T14	1		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T21	1		T53	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T207	14		T90	12		T151	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T14	1		T20	1		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T169	1		T110	3		T209	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T13	1		T18	3		T106	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T205	12		T169	1		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T19	1		T53	1		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	7		T20	10		T106	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T100	6		T93	13		T241	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T99	15		T135	4		T121	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T105	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T100	6		T103	2		T130	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T104	8		T105	9		T311	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T105	7		T140	9		T142	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T120	6		T89	14		T210	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	2		T99	8		T92	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T205	10		T108	10		T111	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T169	1		T108	7		T132	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T135	13		T110	1		T175	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	2		T15	4		T120	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	7		T207	6		T212	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T53	15		T108	7		T117	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T207	16		T90	13		T43	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T20	2		T83	7		T104	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T169	1		T110	6		T209	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T106	8		T219	12		T150	29
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T205	14		T169	1		T215	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T19	1		T53	11		T106	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	7		T20	11		T106	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T118	1		T100	7		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T120	7		T107	1		T105	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T206	1		T151	1		T92	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T89	15		T108	11		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T11	3		T21	1		T99	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T119	1		T205	11		T102	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T118	1		T170	1		T89	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T52	1		T119	1		T212	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	7		T15	5		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	10		T14	1		T207	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T21	1		T83	11		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T207	17		T90	14		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1477	1			T13	1		T14	1		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T169	2		T209	3		T175	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T89	1		T140	8		T185	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T205	15		T169	2		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T19	2		T53	12		T106	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T10	9		T20	12		T106	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T103	13		T131	7		T93	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T135	5		T132	1		T325	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15363	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T104	9		T105	6		T311	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T100	12		T147	2		T101	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T120	7		T105	5		T220	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T206	1		T151	11		T92	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T89	14		T108	9		T109	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	10		T99	4		T208	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T205	11		T221	2		T210	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T89	3		T169	1		T108	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T212	8		T124	2		T222	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	5		T120	4		T124	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	9		T207	7		T223	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T83	2		T108	11		T117	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T207	13		T90	11		T151	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T106	2		T224	12		T174	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T209	12		T46	13		T225	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T89	10		T140	8		T185	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T205	11		T215	5		T112	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T106	5		T100	6		T241	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	5		T20	9		T106	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T103	10		T263	10		T326	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T135	12		T132	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T327	7		T328	12		T291	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T105	5		T293	3		T257	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T100	7		T238	1		T93	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T99	16		T135	5		T121	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T291	1		T217	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T105	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T118	1		T100	7		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T107	1		T104	9		T105	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T206	1		T151	1		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T120	7		T89	15		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T11	3		T21	1		T99	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T119	1		T205	11		T108	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T170	1		T115	1		T169	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T135	14		T102	2		T110	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	7		T15	5		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	10		T14	1		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T21	1		T53	16		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T207	17		T90	14		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	1		T20	3		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T169	2		T110	8		T209	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T13	1		T18	3		T106	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T205	15		T169	2		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T19	2		T53	12		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T10	9		T20	12		T106	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T100	6		T241	9		T124	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T99	15		T135	12		T132	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T291	10		T217	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T105	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T100	12		T147	2		T101	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T105	5		T220	11		T265	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T206	1		T151	11		T105	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T120	7		T89	14		T109	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	10		T99	4		T208	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T205	11		T108	9		T221	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T169	1		T108	7		T132	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T124	2		T222	5		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	5		T120	4		T89	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	9		T207	7		T212	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T108	11		T117	5		T110	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T207	13		T90	11		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T83	2		T227	7		T329	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T110	1		T209	12		T46	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T106	2		T224	12		T174	30
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T205	11		T215	5		T112	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T106	5		T89	10		T103	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	5		T20	9		T106	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5