Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20843

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3179

1

T10

19

T11

13

T12

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18194

1

T31

1

T32

1

T38

2

auto[1]

5828

1

T10

14

T11

13

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	218	1			T12	12		T99	13		T117	11
values[0]	59	1			T119	1		T265	1		T318	10
values[1]	904	1			T19	2		T53	12		T207	14
values[2]	2815	1			T13	1		T18	3		T20	3
values[3]	576	1			T15	5		T52	1		T53	16
values[4]	653	1			T14	2		T118	1		T170	1
values[5]	599	1			T10	19		T21	2		T106	11
values[6]	741	1			T83	13		T120	9		T207	30
values[7]	560	1			T118	1		T120	14		T205	22
values[8]	560	1			T106	22		T170	1		T169	2
values[9]	1007	1			T10	14		T11	13		T20	21
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	896	1			T19	2		T53	12		T119	1
values[1]	2770	1			T13	1		T18	3		T20	3
values[2]	627	1			T15	5		T52	1		T137	1
values[3]	628	1			T10	19		T14	2		T21	1
values[4]	588	1			T21	1		T106	11		T205	26
values[5]	676	1			T83	13		T118	1		T120	9
values[6]	588	1			T120	14		T107	1		T212	16
values[7]	637	1			T10	14		T106	22		T119	1
values[8]	850	1			T11	13		T12	12		T20	21
values[9]	149	1			T99	13		T107	1		T97	3
minimum	15613	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T19	1		T148	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T53	1		T119	1		T100	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T13	1		T18	3		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T53	1		T89	11		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	1		T95	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	1		T52	1		T130	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T14	2		T170	1		T206	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	12		T21	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T21	1		T106	3		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T205	12		T151	3		T140	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T120	5		T205	12		T147	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T83	6		T118	1		T207	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T120	8		T212	9		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T107	1		T137	1		T92	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	7		T106	9		T151	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T106	6		T119	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T20	10		T169	2		T102	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	11		T12	10		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T99	5		T97	1		T124	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T107	1		T296	2		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T207	8		T190	1		T126	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T19	1		T135	13		T185	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T53	11		T100	6		T89	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T20	2		T219	12		T150	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	15		T108	7		T104	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T140	1		T124	4		T43	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	4		T130	10		T175	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T102	1		T140	8		T43	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	7		T99	15		T100	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T106	8		T135	4		T103	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T205	14		T140	7		T315	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T120	4		T205	10		T131	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T83	7		T207	16		T104	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T120	6		T212	7		T169	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T92	10		T130	3		T110	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	7		T106	2		T241	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T106	5		T108	10		T121	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T20	11		T169	1		T117	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	2		T12	2		T89	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T99	8		T97	2		T124	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T316	15		T322	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T207	6		T126	13		T251	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T99	5		T117	6		T124	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T12	10		T316	1		T330	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T265	1		T318	10		T274	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T119	1		T319	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T19	1		T148	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T53	1		T207	8		T100	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T13	1		T18	3		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T89	11		T90	12		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T137	1		T103	12		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	1		T52	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	2		T170	1		T206	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T118	1		T99	16		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T21	1		T106	3		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	12		T21	1		T205	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T120	5		T147	3		T94	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T83	6		T207	14		T208	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T120	8		T205	12		T212	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T118	1		T107	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T106	9		T169	1		T117	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T106	6		T170	1		T108	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T10	7		T20	10		T151	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	11		T52	1		T119	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T99	8		T117	5		T124	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T12	2		T316	15		T146	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T274	2		T331	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T319	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T19	1		T135	13		T108	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T53	11		T207	6		T100	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1101	1			T20	2		T219	12		T150	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T90	13		T132	16		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T103	11		T140	1		T124	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	4		T53	15		T108	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T102	1		T140	8		T43	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T99	15		T164	10		T296	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T106	8		T135	4		T103	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	7		T205	14		T100	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T120	4		T210	23		T165	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T83	7		T207	16		T104	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T120	6		T205	10		T212	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T92	10		T130	3		T110	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T106	2		T169	1		T185	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T106	5		T108	10		T110	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T10	7		T20	11		T169	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	2		T89	14		T121	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T19	2		T148	1		T135	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T53	12		T119	1		T100	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T13	1		T18	3		T20	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T53	16		T89	1		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T137	1		T95	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	5		T52	1		T130	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	2		T170	1		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	10		T21	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T21	1		T106	9		T135	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T205	15		T151	1		T140	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T120	5		T205	11		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T83	11		T118	1		T207	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T120	7		T212	8		T169	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T107	1		T137	1		T92	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	9		T106	3		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T106	6		T119	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T20	12		T169	2		T102	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	3		T12	7		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T99	9		T97	3		T124	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T107	1		T296	2		T316	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15398	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T207	7		T190	1		T126	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T209	7		T222	5		T221	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T100	12		T89	3		T90	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T224	12		T174	30		T103	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T89	10		T108	11		T223	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T124	6		T242	1		T159	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T130	9		T190	1		T112	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T206	1		T132	8		T140	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	9		T99	15		T100	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T106	2		T135	12		T103	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T205	11		T151	2		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T120	4		T205	11		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T83	2		T207	13		T208	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T120	7		T212	8		T117	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T92	4		T110	7		T222	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	5		T106	8		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T106	5		T108	9		T142	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T20	9		T169	1		T117	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	10		T12	5		T89	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T99	4		T124	12		T288	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T322	7		T202	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T108	7		T234	10		T300	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T207	7		T126	12		T253	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T99	9		T117	6		T124	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T12	7		T316	16		T330	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T265	1		T318	1		T274	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T119	1		T319	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T19	2		T148	1		T135	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T53	12		T207	7		T100	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1455	1			T13	1		T18	3		T20	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T89	1		T90	14		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	1		T103	13		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	5		T52	1		T53	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	2		T170	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T118	1		T99	16		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T21	1		T106	9		T135	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	10		T21	1		T205	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T120	5		T147	1		T94	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T83	11		T207	17		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T120	7		T205	11		T212	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T118	1		T107	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T106	3		T169	2		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T106	6		T170	1		T108	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T10	9		T20	12		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T11	3		T52	1		T119	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T99	4		T117	5		T124	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T12	5		T332	4		T202	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T318	9		T274	13		T331	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T108	7		T209	7		T222	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T207	7		T100	12		T89	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T224	12		T174	30		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T89	10		T90	11		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T103	10		T124	6		T226	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T108	11		T130	9		T190	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T206	1		T132	8		T140	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T99	15		T164	13		T245	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T106	2		T135	12		T103	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	9		T205	11		T100	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T120	4		T147	2		T142	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T83	2		T207	13		T208	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T120	7		T205	11		T212	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T92	4		T110	7		T222	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T106	8		T117	1		T109	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T106	5		T108	9		T142	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	5		T20	9		T151	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	10		T89	14		T105	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5