Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20866

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3156

1

T11

13

T12

12

T14

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18301

1

T31

1

T32

1

T38

2

auto[1]

5721

1

T10

14

T11

13

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	186	1			T83	13		T118	1		T148	1
values[0]	62	1			T170	1		T244	6		T253	29
values[1]	651	1			T21	1		T106	11		T205	22
values[2]	861	1			T53	12		T120	14		T207	30
values[3]	670	1			T52	2		T106	11		T119	1
values[4]	714	1			T11	13		T14	1		T119	1
values[5]	719	1			T12	12		T19	2		T120	9
values[6]	591	1			T10	14		T20	21		T115	1
values[7]	620	1			T14	1		T53	16		T89	11
values[8]	607	1			T10	19		T107	1		T89	38
values[9]	3011	1			T13	1		T15	5		T18	3
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	691	1			T21	1		T205	22		T100	19
values[1]	796	1			T53	12		T120	14		T207	30
values[2]	727	1			T52	2		T106	11		T119	1
values[3]	634	1			T11	13		T14	1		T19	2
values[4]	771	1			T12	12		T99	31		T115	1
values[5]	541	1			T10	14		T20	21		T169	2
values[6]	2817	1			T13	1		T14	1		T18	3
values[7]	532	1			T10	19		T100	13		T89	29
values[8]	805	1			T20	3		T21	2		T83	13
values[9]	130	1			T15	5		T206	2		T151	3
minimum	15578	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T21	1		T91	1		T92	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T205	12		T100	13		T107	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T120	8		T207	14		T99	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T53	1		T95	1		T110	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T106	3		T170	1		T208	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T52	2		T119	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T19	1		T151	12		T103	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	11		T14	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T115	1		T130	15		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	10		T99	16		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	7		T20	10		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T169	1		T164	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T13	1		T18	3		T224	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T14	1		T53	1		T117	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	12		T100	7		T89	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T116	1		T169	2		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T20	1		T21	1		T83	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T21	1		T118	1		T207	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T15	1		T206	2		T151	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T108	10		T111	1		T289	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15265	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T106	6		T170	1		T135	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T92	10		T105	7		T117	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T205	10		T100	6		T104	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T120	6		T207	16		T99	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T53	11		T110	6		T185	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T106	8		T103	11		T142	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T90	13		T212	7		T102	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T19	1		T103	4		T175	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	2		T120	4		T104	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T130	10		T48	14		T233	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	2		T99	15		T169	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	7		T20	11		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T169	1		T130	3		T132	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T219	12		T89	5		T150	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T53	15		T117	5		T93	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T10	7		T100	6		T89	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T169	1		T121	16		T124	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T20	2		T83	7		T106	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T207	6		T205	14		T105	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T15	4		T110	8		T250	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T108	10		T111	3		T289	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T106	5		T135	13		T253	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T83	6		T118	1		T151	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T148	1		T123	1		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T244	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T170	1		T253	14		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T21	1		T108	12		T91	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T106	6		T205	12		T100	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T120	8		T207	14		T99	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T53	1		T95	1		T185	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T106	3		T170	1		T208	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T52	2		T119	1		T90	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T151	12		T103	10		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	11		T14	1		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T19	1		T130	15		T269	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	10		T120	5		T99	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	7		T20	10		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T169	1		T164	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T89	11		T91	1		T124	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T14	1		T53	1		T117	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	12		T107	1		T89	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T169	2		T121	1		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T13	1		T15	1		T18	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T21	1		T118	1		T207	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T83	7		T250	3		T266	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T111	3		T333	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T244	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T253	15		T155	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T108	7		T92	10		T105	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T106	5		T205	10		T100	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T120	6		T207	16		T99	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T53	11		T185	2		T241	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T106	8		T108	7		T103	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T90	13		T212	7		T102	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T103	4		T175	10		T112	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	2		T104	8		T46	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T19	1		T130	10		T269	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	2		T120	4		T99	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T10	7		T20	11		T164	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T169	1		T130	3		T132	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T124	4		T240	6		T210	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T53	15		T117	5		T123	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T10	7		T89	19		T140	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T169	1		T121	16		T93	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T15	4		T20	2		T106	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T207	6		T205	14		T108	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T21	1		T91	1		T92	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T205	11		T100	7		T107	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T120	7		T207	17		T99	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T53	12		T95	1		T110	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T106	9		T170	1		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T52	2		T119	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T19	2		T151	1		T103	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	3		T14	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T115	1		T130	16		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	7		T99	16		T169	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	9		T20	12		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T169	2		T164	1		T130	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T13	1		T18	3		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	1		T53	16		T117	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	10		T100	7		T89	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T116	1		T169	2		T121	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T20	3		T21	1		T83	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T21	1		T118	1		T207	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T15	5		T206	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T108	11		T111	4		T289	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15423	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T106	6		T170	1		T135	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T92	4		T105	6		T117	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T205	11		T100	12		T46	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T120	7		T207	13		T99	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T110	1		T185	1		T241	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T106	2		T208	2		T103	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T90	11		T212	8		T46	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T151	11		T103	7		T251	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	10		T120	4		T96	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	9		T142	3		T233	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	5		T99	15		T132	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T10	5		T20	9		T164	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T132	11		T215	5		T222	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1102	1			T224	12		T89	13		T174	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T117	5		T123	6		T113	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T10	9		T100	6		T89	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T169	1		T117	1		T124	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T83	2		T106	8		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T207	7		T205	11		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T206	1		T151	2		T110	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T108	9		T289	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T108	11		T334	9		T155	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T106	5		T253	13		T236	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T83	11		T118	1		T151	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T148	1		T123	1		T111	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T244	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T170	1		T253	16		T155	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T21	1		T108	8		T91	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T106	6		T205	11		T100	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T120	7		T207	17		T99	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T53	12		T95	1		T185	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T106	9		T170	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T52	2		T119	1		T90	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T151	1		T103	7		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	3		T14	1		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T19	2		T130	16		T269	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	7		T120	5		T99	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	9		T20	12		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T169	2		T164	1		T130	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T89	1		T91	1		T124	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T14	1		T53	16		T117	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	10		T107	1		T89	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T169	2		T121	17		T93	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T13	1		T15	5		T18	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	1		T118	1		T207	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T83	2		T151	2		T225	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T225	7		T154	10		T168	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T244	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T253	13		T155	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T108	11		T92	4		T105	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T106	5		T205	11		T100	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T120	7		T207	13		T99	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T185	1		T241	9		T226	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T106	2		T208	2		T108	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T90	11		T212	8		T110	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T151	11		T103	7		T112	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	10		T46	12		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T130	9		T293	2		T327	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	5		T120	4		T99	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T10	5		T20	9		T164	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T132	11		T215	5		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T89	10		T124	2		T210	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T117	5		T123	6		T222	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	9		T89	17		T140	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T169	1		T124	12		T222	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T106	8		T100	6		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T207	7		T205	11		T108	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5