Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20520

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3502

1

T10

19

T19

2

T20

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18257

1

T31

1

T32

1

T38

2

auto[1]

5765

1

T10

19

T11

13

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	294	1			T10	14		T170	2		T100	13
values[0]	86	1			T142	28		T259	33		T335	14
values[1]	787	1			T10	19		T14	1		T119	2
values[2]	803	1			T20	3		T99	31		T108	19
values[3]	690	1			T15	5		T52	1		T53	16
values[4]	2640	1			T13	1		T14	1		T18	3
values[5]	679	1			T21	1		T106	11		T118	1
values[6]	610	1			T21	1		T170	1		T100	19
values[7]	606	1			T20	21		T91	1		T93	1
values[8]	711	1			T83	13		T52	1		T53	12
values[9]	786	1			T11	13		T12	12		T21	1
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	750	1			T10	19		T14	1		T20	3
values[1]	720	1			T99	31		T212	16		T91	1
values[2]	639	1			T15	5		T52	1		T53	16
values[3]	2652	1			T13	1		T14	1		T18	3
values[4]	663	1			T21	1		T106	11		T118	1
values[5]	721	1			T21	1		T170	1		T100	19
values[6]	552	1			T20	21		T148	1		T91	1
values[7]	645	1			T83	13		T52	1		T53	12
values[8]	840	1			T10	14		T11	13		T12	12
values[9]	146	1			T170	1		T175	12		T124	9
minimum	15694	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T119	1		T105	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	12		T20	1		T108	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T212	9		T91	1		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T99	16		T105	7		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	1		T53	1		T99	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T52	1		T107	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T13	1		T14	1		T18	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T19	1		T115	1		T151	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T89	15		T164	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T21	1		T106	3		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T21	1		T170	1		T100	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T92	5		T117	14		T249	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T20	10		T110	3		T124	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T148	1		T91	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T83	6		T52	1		T106	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T53	1		T106	9		T207	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T10	7		T11	11		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T21	1		T120	8		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T124	5		T336	3		T158	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T170	1		T175	1		T254	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15309	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T140	9		T142	14		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T105	5		T140	1		T50	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	7		T20	2		T108	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T212	7		T124	4		T253	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T99	15		T105	7		T110	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	4		T53	15		T99	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T141	13		T210	24		T176	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T120	4		T219	12		T90	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T19	1		T135	4		T108	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T89	5		T104	8		T131	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T106	8		T169	1		T132	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T100	6		T215	6		T113	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T92	10		T117	16		T233	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T20	11		T110	6		T124	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T233	14		T113	8		T145	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T83	7		T106	5		T205	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T53	11		T106	2		T207	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	7		T11	2		T12	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T120	6		T100	6		T103	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T124	4		T237	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T175	11		T254	18		T255	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T140	7		T142	14		T46	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T10	7		T246	1		T124	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T170	2		T100	7		T117	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T258	5		T337	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T142	14		T259	17		T335	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T119	2		T207	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	12		T108	10		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T91	1		T248	1		T124	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	1		T99	16		T108	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T15	1		T53	1		T99	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T52	1		T115	1		T105	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T13	1		T14	1		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T19	1		T107	1		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T89	15		T164	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T21	1		T106	3		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T21	1		T170	1		T100	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T169	1		T92	5		T249	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T20	10		T215	6		T110	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T91	1		T93	1		T142	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T83	6		T52	1		T205	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T53	1		T106	9		T207	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	11		T12	10		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T21	1		T120	8		T151	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T10	7		T124	4		T251	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T100	6		T46	16		T211	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T258	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T142	14		T259	16		T335	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T207	6		T105	5		T140	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	7		T108	10		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T124	4		T261	8		T253	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T20	2		T99	15		T108	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	4		T53	15		T99	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T105	7		T141	13		T210	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T120	4		T219	12		T90	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T19	1		T135	4		T108	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T89	5		T104	8		T131	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T106	8		T117	16		T132	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T100	6		T97	2		T209	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T169	1		T92	10		T233	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T20	11		T215	6		T110	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T233	14		T234	2		T211	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T83	7		T205	14		T89	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	11		T106	2		T207	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	2		T12	2		T106	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T120	6		T103	4		T175	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	1		T119	1		T105	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T10	10		T20	3		T108	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T212	8		T91	1		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T99	16		T105	8		T110	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	5		T53	16		T99	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T52	1		T107	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T13	1		T14	1		T18	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T19	2		T115	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T89	7		T164	1		T104	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	1		T106	9		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	1		T170	1		T100	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T92	11		T117	17		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T20	12		T110	8		T124	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T148	1		T91	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T83	11		T52	1		T106	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T53	12		T106	3		T207	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T10	9		T11	3		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T21	1		T120	7		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T124	7		T336	3		T158	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T170	1		T175	12		T254	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15416	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T140	8		T142	15		T46	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T105	5		T261	10		T318	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	9		T108	20		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T212	8		T124	6		T226	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T99	15		T105	6		T46	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T99	4		T169	1		T223	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T210	26		T262	4		T263	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T120	4		T224	12		T206	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T151	11		T135	12		T101	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T89	13		T140	1		T209	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T106	2		T132	11		T123	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T100	12		T215	5		T222	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T92	4		T117	13		T249	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T20	9		T110	1		T124	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T142	3		T233	2		T113	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T83	2		T106	5		T205	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T106	8		T207	13		T205	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	5		T11	10		T12	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T120	7		T100	6		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T124	2		T158	1		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T255	16		T264	13		T277	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T207	7		T147	2		T110	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T140	8		T142	13		T259	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T10	9		T246	1		T124	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T170	2		T100	7		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T258	4		T337	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T142	15		T259	17		T335	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	1		T119	2		T207	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	10		T108	11		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T91	1		T248	1		T124	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T20	3		T99	16		T108	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T15	5		T53	16		T99	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T52	1		T115	1		T105	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T13	1		T14	1		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T19	2		T107	1		T135	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T89	7		T164	1		T104	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T21	1		T106	9		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T21	1		T170	1		T100	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T169	2		T92	11		T249	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T20	12		T215	7		T110	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T91	1		T93	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T83	11		T52	1		T205	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T53	12		T106	3		T207	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	3		T12	7		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T21	1		T120	7		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T10	5		T124	2		T221	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T100	6		T117	1		T46	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T258	4		T337	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T142	13		T259	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T207	7		T147	2		T105	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	9		T108	9		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T124	6		T226	9		T225	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T99	15		T108	11		T117	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T99	4		T212	8		T169	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T105	6		T210	14		T265	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T120	4		T224	12		T206	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T135	12		T101	18		T108	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T89	13		T140	1		T126	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T106	2		T151	11		T117	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T100	12		T209	12		T222	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T92	4		T249	12		T245	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T20	9		T215	5		T110	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T142	3		T233	2		T234	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T83	2		T205	11		T89	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T106	8		T207	13		T205	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	10		T12	5		T106	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T120	7		T151	2		T103	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5