Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19032

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

4990

1

T10

33

T11

13

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18400

1

T31

1

T32

1

T38

2

auto[1]

5622

1

T12

12

T13

1

T14

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	316	1			T14	1		T106	11		T135	14
values[0]	40	1			T129	1		T229	12		T230	11
values[1]	757	1			T119	1		T120	14		T100	13
values[2]	606	1			T83	13		T53	16		T106	11
values[3]	648	1			T19	2		T119	1		T107	1
values[4]	524	1			T21	1		T118	1		T89	38
values[5]	626	1			T52	1		T120	9		T100	19
values[6]	629	1			T12	12		T20	3		T52	1
values[7]	643	1			T10	14		T21	1		T107	1
values[8]	727	1			T10	19		T15	5		T53	12
values[9]	3176	1			T11	13		T13	1		T14	1
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	851	1			T83	13		T53	16		T119	1
values[1]	2638	1			T13	1		T18	3		T106	11
values[2]	568	1			T19	2		T107	1		T89	9
values[3]	616	1			T21	1		T118	1		T120	9
values[4]	526	1			T20	3		T52	1		T170	1
values[5]	767	1			T10	14		T12	12		T52	1
values[6]	600	1			T15	5		T21	1		T106	11
values[7]	748	1			T10	19		T20	21		T53	12
values[8]	922	1			T14	2		T21	1		T106	11
values[9]	217	1			T11	13		T91	1		T175	14
minimum	15569	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T83	6		T120	8		T99	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T53	1		T119	1		T207	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T99	5		T205	24		T103	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1338	1			T13	1		T18	3		T106	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	1		T107	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T89	4		T208	3		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T21	1		T118	1		T120	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T89	15		T151	12		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T20	1		T52	1		T100	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T170	1		T169	2		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	10		T52	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	7		T147	3		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T21	1		T107	1		T164	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	1		T106	3		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T20	10		T101	19		T124	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	12		T53	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T14	1		T118	1		T151	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	1		T21	1		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T235	10		T338	1		T243	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T11	11		T91	1		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15281	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T137	1		T94	1		T264	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T83	7		T120	6		T99	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T53	15		T207	6		T100	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T99	8		T205	24		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1014	1			T106	2		T219	12		T150	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	1		T131	1		T132	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T89	5		T140	1		T96	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T120	4		T110	1		T43	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T89	14		T215	6		T233	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T20	2		T100	6		T105	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T169	1		T121	16		T185	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	2		T135	4		T103	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	7		T169	1		T102	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T164	10		T93	14		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T15	4		T106	8		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T20	11		T124	14		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	7		T53	11		T169	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T105	5		T130	3		T117	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T106	5		T207	16		T90	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T235	8		T338	2		T243	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T11	2		T175	13		T244	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T264	10		T339	12		T236	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T248	1		T132	9		T249	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T14	1		T106	6		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T129	1		T229	1		T230	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T236	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T120	8		T238	1		T108	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T119	1		T100	7		T89	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T83	6		T99	21		T205	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T53	1		T106	9		T207	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T19	1		T107	1		T92	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T119	1		T208	3		T108	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T21	1		T118	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T89	19		T151	12		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T52	1		T120	5		T100	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T169	3		T121	1		T185	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	10		T20	1		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T170	1		T223	13		T130	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T21	1		T107	1		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	7		T115	1		T147	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T101	19		T164	14		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	12		T15	1		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T14	1		T20	10		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1439	1			T11	11		T13	1		T18	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T124	4		T48	14		T50	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T106	5		T135	13		T126	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T229	11		T230	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T236	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T120	6		T108	10		T97	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T100	6		T175	11		T48	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T83	7		T99	23		T205	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T53	15		T106	2		T207	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T19	1		T92	10		T131	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T108	7		T209	2		T46	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T110	7		T43	14		T311	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T89	19		T140	1		T96	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T120	4		T100	6		T105	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T169	2		T121	16		T185	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	2		T20	2		T135	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T130	10		T93	13		T214	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T93	14		T43	15		T234	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T10	7		T102	1		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T164	10		T124	14		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	7		T15	4		T53	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T20	11		T105	5		T130	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1194	1			T11	2		T207	16		T219	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T83	11		T120	7		T99	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T53	16		T119	1		T207	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T99	9		T205	26		T103	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1351	1			T13	1		T18	3		T106	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T19	2		T107	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T89	6		T208	1		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T21	1		T118	1		T120	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T89	15		T151	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T20	3		T52	1		T100	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T170	1		T169	2		T121	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T12	7		T52	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	9		T147	1		T169	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T21	1		T107	1		T164	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	5		T106	9		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T20	12		T101	1		T124	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	10		T53	12		T169	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T14	1		T118	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T14	1		T21	1		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T235	9		T338	3		T243	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T11	3		T91	1		T175	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15407	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T137	1		T94	1		T264	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T83	2		T120	7		T99	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T207	7		T100	6		T89	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T99	4		T205	22		T92	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1001	1			T106	8		T224	12		T174	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T132	11		T110	1		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T89	3		T208	2		T96	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T120	4		T117	1		T253	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T89	14		T151	11		T215	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T100	12		T206	1		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T169	1		T185	1		T241	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	5		T135	12		T103	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	5		T147	2		T223	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T164	13		T234	9		T210	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T106	2		T142	16		T300	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T20	9		T101	18		T124	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T10	9		T103	7		T245	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T151	2		T105	5		T117	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T106	5		T207	13		T90	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T235	9		T243	13		T291	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T11	10		T244	3		T326	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T142	7		T124	12		T230	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T264	6		T236	8		T155	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T248	1		T132	1		T249	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T14	1		T106	6		T135	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T129	1		T229	12		T230	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T236	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T120	7		T238	1		T108	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T119	1		T100	7		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T83	11		T99	25		T205	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T53	16		T106	3		T207	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T19	2		T107	1		T92	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T119	1		T208	1		T108	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T21	1		T118	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T89	21		T151	1		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T52	1		T120	5		T100	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T169	4		T121	17		T185	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	7		T20	3		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T170	1		T223	1		T130	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T21	1		T107	1		T93	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	9		T115	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T101	1		T164	11		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	10		T15	5		T53	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T14	1		T20	12		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1550	1			T11	3		T13	1		T18	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T132	8		T249	12		T124	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T106	5		T222	4		T126	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T230	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T236	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T120	7		T108	9		T142	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T100	6		T89	10		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T83	2		T99	19		T205	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T106	8		T207	7		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T92	4		T132	11		T226	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T208	2		T108	7		T209	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T117	1		T110	1		T143	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T89	17		T151	11		T96	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T120	4		T100	12		T206	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T169	1		T185	1		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	5		T135	12		T103	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T223	12		T130	9		T190	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T234	10		T210	3		T113	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T10	5		T147	2		T142	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T101	18		T164	13		T124	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T10	9		T106	2		T103	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T20	9		T151	2		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1083	1			T11	10		T207	13		T224	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5