Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	425	1			T83	11		T120	7		T99	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T53	16		T119	1		T207	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T99	9		T205	26		T103	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1369	1			T13	1		T18	3		T106	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T19	2		T107	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T89	6		T208	1		T140	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T21	1		T118	1		T120	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T89	15		T151	1		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T20	3		T52	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T170	1		T169	2		T121	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	7		T52	1		T135	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	9		T170	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T21	1		T107	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	5		T106	9		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T20	12		T101	1		T124	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	10		T53	12		T169	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T14	1		T118	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	1		T21	1		T106	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T105	6		T50	12		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	3		T90	14		T135	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T232	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T83	2		T120	7		T99	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T207	7		T100	6		T89	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T99	4		T205	22		T92	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1027	1			T106	8		T224	12		T174	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T132	11		T110	1		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T89	3		T208	2		T96	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T120	4		T100	12		T117	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T89	14		T151	11		T215	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T206	1		T105	5		T110	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T169	1		T185	1		T241	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	5		T135	12		T103	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	5		T223	12		T130	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T164	13		T234	9		T210	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T106	2		T147	2		T142	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T20	9		T101	18		T124	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T10	9		T103	7		T242	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T151	2		T117	13		T132	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T106	5		T207	13		T212	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T105	5		T235	9		T243	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T11	10		T90	11		T244	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T14	1		T91	1		T228	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T129	1		T229	12		T230	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T236	8		T237	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T120	7		T238	1		T108	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T100	7		T89	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T83	11		T99	25		T205	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T53	16		T106	3		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T19	2		T107	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T119	1		T208	1		T108	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T21	1		T118	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T89	21		T151	1		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T120	5		T100	7		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T169	4		T121	17		T185	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	7		T20	3		T52	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T170	1		T115	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T21	1		T107	1		T93	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	9		T170	1		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T101	1		T137	1		T164	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	10		T15	5		T53	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	409	1			T14	1		T20	12		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1607	1			T11	3		T13	1		T18	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T230	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T236	8		T237	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T120	7		T108	9		T142	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T100	6		T89	10		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T83	2		T99	19		T205	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T106	8		T207	7		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T226	9		T210	12		T227	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T208	2		T108	7		T209	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T117	1		T132	11		T110	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T89	17		T151	11		T96	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T120	4		T100	12		T206	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T169	1		T185	1		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	5		T135	12		T103	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T147	2		T223	12		T130	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T234	10		T112	3		T210	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T10	5		T142	16		T123	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T101	18		T164	13		T124	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T10	9		T106	2		T245	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T20	9		T151	2		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1142	1			T11	10		T106	5		T207	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5