Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20527

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3495

1

T10

19

T19

2

T20

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18250

1

T31

1

T32

1

T38

2

auto[1]

5772

1

T10

19

T11

13

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	40	1			T170	1		T100	13		T246	1
values[0]	95	1			T119	1		T207	14		T142	28
values[1]	802	1			T10	19		T14	1		T119	1
values[2]	781	1			T20	3		T99	31		T108	19
values[3]	662	1			T15	5		T52	1		T53	16
values[4]	2635	1			T13	1		T14	1		T18	3
values[5]	653	1			T19	2		T21	1		T106	11
values[6]	631	1			T21	1		T170	1		T100	19
values[7]	608	1			T91	1		T93	1		T215	12
values[8]	761	1			T20	21		T21	1		T83	13
values[9]	1024	1			T10	14		T11	13		T12	12
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1097	1			T10	19		T14	1		T20	3
values[1]	745	1			T99	31		T212	16		T108	19
values[2]	623	1			T15	5		T52	1		T53	16
values[3]	2597	1			T13	1		T14	1		T18	3
values[4]	775	1			T21	1		T106	11		T118	1
values[5]	648	1			T21	1		T170	1		T100	19
values[6]	573	1			T20	21		T91	1		T93	1
values[7]	624	1			T83	13		T52	1		T53	12
values[8]	796	1			T10	14		T11	13		T12	12
values[9]	206	1			T170	1		T103	23		T247	1
minimum	15338	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	1		T119	2		T207	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T10	12		T20	1		T108	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T212	9		T91	1		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T99	16		T108	12		T105	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	1		T53	1		T99	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T52	1		T107	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T13	1		T14	1		T18	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T19	1		T135	13		T101	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T89	15		T164	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T21	1		T106	3		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	1		T170	1		T100	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T92	5		T117	14		T249	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T20	10		T124	13		T234	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T91	1		T93	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T83	6		T52	1		T106	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T53	1		T106	9		T207	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	7		T11	11		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T21	1		T120	8		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T103	12		T250	5		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T170	1		T247	1		T252	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15221	1			T9	11		T11	20		T16	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T207	6		T105	5		T140	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T10	7		T20	2		T108	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T212	7		T124	4		T253	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T99	15		T108	7		T105	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	4		T53	15		T99	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T141	13		T210	24		T176	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T120	4		T219	12		T90	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T19	1		T135	4		T108	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T89	5		T104	8		T131	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T106	8		T169	1		T132	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T100	6		T215	6		T113	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T92	10		T117	16		T233	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T20	11		T124	12		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T233	14		T234	2		T113	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T83	7		T106	5		T205	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T53	11		T106	2		T207	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	7		T11	2		T12	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T120	6		T100	6		T103	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T103	11		T250	4		T251	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T252	7		T254	18		T255	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T31	1		T32	1		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T246	1		T256	15		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T170	1		T100	7		T257	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T119	1		T207	8		T258	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T142	14		T259	17		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T119	1		T147	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	12		T108	10		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T91	1		T248	1		T124	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T20	1		T99	16		T108	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	1		T53	1		T99	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T52	1		T105	7		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T13	1		T14	1		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T107	1		T115	2		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T89	15		T90	12		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T19	1		T21	1		T106	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T21	1		T170	1		T100	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T169	1		T249	13		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T215	6		T110	3		T185	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T91	1		T93	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T20	10		T83	6		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T21	1		T53	1		T106	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T10	7		T11	11		T12	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T120	8		T170	1		T151	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T100	6		T257	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T207	6		T258	3		T173	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T142	14		T259	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T105	5		T140	1		T110	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	7		T108	10		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T124	4		T50	11		T261	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T20	2		T99	15		T108	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	4		T53	15		T99	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T105	7		T141	13		T210	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T120	4		T219	12		T150	29
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T135	4		T108	7		T185	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T89	5		T90	13		T131	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T19	1		T106	8		T92	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T100	6		T104	8		T97	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T169	1		T233	5		T127	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T215	6		T110	6		T185	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T234	2		T113	4		T211	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T20	11		T83	7		T205	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T53	11		T106	2		T207	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	7		T11	2		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T120	6		T103	4		T175	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T14	1		T119	2		T207	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T10	10		T20	3		T108	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T212	8		T91	1		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T99	16		T108	8		T105	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	5		T53	16		T99	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T52	1		T107	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T13	1		T14	1		T18	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T19	2		T135	5		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T89	7		T164	1		T104	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T21	1		T106	9		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T21	1		T170	1		T100	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T92	11		T117	17		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T20	12		T124	13		T234	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T91	1		T93	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T83	11		T52	1		T106	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T53	12		T106	3		T207	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T10	9		T11	3		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T21	1		T120	7		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T103	13		T250	6		T251	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T170	1		T247	1		T252	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15334	1			T31	1		T32	1		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T207	7		T147	2		T105	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	9		T108	9		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T212	8		T124	6		T226	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T99	15		T108	11		T105	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T99	4		T169	1		T223	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T210	26		T262	4		T263	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T120	4		T224	12		T206	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T135	12		T101	18		T108	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T89	13		T140	1		T209	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T106	2		T151	11		T132	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T100	12		T215	5		T222	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T92	4		T117	13		T249	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T20	9		T124	12		T234	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T142	3		T233	2		T234	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T83	2		T106	5		T205	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T106	8		T207	13		T205	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	5		T11	10		T12	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T120	7		T100	6		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T103	10		T250	3		T158	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T252	2		T255	16		T264	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T258	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T246	1		T256	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T170	1		T100	7		T257	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T119	1		T207	7		T258	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T142	15		T259	17		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	1		T119	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T10	10		T108	11		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T91	1		T248	1		T124	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T20	3		T99	16		T108	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	5		T53	16		T99	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T52	1		T105	8		T141	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T13	1		T14	1		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T107	1		T115	2		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T89	7		T90	14		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T19	2		T21	1		T106	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T21	1		T170	1		T100	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T169	2		T249	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T215	7		T110	8		T185	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T91	1		T93	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T20	12		T83	11		T52	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	1		T53	12		T106	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	9		T11	3		T12	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T120	7		T170	1		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T256	14		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T100	6		T257	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T207	7		T258	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T142	13		T259	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T147	2		T105	5		T110	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	9		T108	9		T130	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T124	6		T226	9		T225	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T99	15		T108	11		T117	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T99	4		T212	8		T169	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T105	6		T210	14		T265	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T120	4		T224	12		T206	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T151	11		T135	12		T101	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T89	13		T90	11		T140	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T106	2		T92	4		T117	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T100	12		T209	12		T222	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T249	12		T245	12		T233	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T215	5		T110	1		T234	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T142	3		T234	10		T113	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	9		T83	2		T205	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T106	8		T207	13		T205	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	5		T11	10		T12	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T120	7		T151	2		T103	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5