Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20438

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3584

1

T10

14

T11

13

T20

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17958

1

T31

1

T32

1

T38

2

auto[1]

6064

1

T10

33

T12

12

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	653	1			T19	2		T33	4		T170	1
values[0]	64	1			T212	16		T223	13		T245	13
values[1]	552	1			T20	3		T106	11		T100	19
values[2]	2821	1			T11	13		T13	1		T14	1
values[3]	756	1			T83	13		T52	1		T99	31
values[4]	545	1			T10	14		T21	2		T89	9
values[5]	557	1			T20	21		T118	1		T119	1
values[6]	842	1			T10	19		T12	12		T118	1
values[7]	585	1			T14	1		T53	16		T207	30
values[8]	719	1			T53	12		T106	11		T119	1
values[9]	985	1			T15	5		T19	2		T21	1
minimum	14943	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	561	1			T11	13		T14	1		T106	11
values[1]	2958	1			T13	1		T18	3		T52	1
values[2]	671	1			T21	1		T83	13		T99	31
values[3]	579	1			T10	14		T21	1		T120	14
values[4]	581	1			T20	21		T118	1		T119	1
values[5]	753	1			T10	19		T12	12		T118	1
values[6]	704	1			T14	1		T53	28		T147	3
values[7]	567	1			T52	1		T106	11		T119	1
values[8]	1079	1			T15	5		T19	2		T21	1
values[9]	76	1			T50	3		T234	16		T231	1
minimum	15493	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	1		T100	13		T115	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	11		T106	3		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T13	1		T18	3		T224	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T52	1		T106	9		T104	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T83	6		T107	1		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T21	1		T99	16		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T120	8		T108	12		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	7		T21	1		T89	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T118	1		T99	5		T117	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T20	10		T119	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	12		T12	10		T205	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T118	1		T170	1		T207	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	1		T147	3		T108	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T53	2		T103	12		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T151	3		T103	10		T117	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T52	1		T106	6		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T15	1		T19	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T21	1		T205	12		T100	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T50	1		T234	10		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T231	1		T225	3		T267	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15266	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T20	1		T105	6		T43	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T100	6		T108	7		T131	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	2		T106	8		T169	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T219	12		T150	29		T164	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T106	2		T104	14		T241	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T83	7		T102	1		T124	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T99	15		T90	13		T104	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T120	6		T108	7		T142	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T10	7		T89	5		T105	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T99	8		T117	16		T175	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T20	11		T105	9		T97	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	7		T12	2		T205	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T207	16		T169	1		T92	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T108	10		T130	10		T93	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	26		T103	11		T130	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T103	4		T117	5		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T106	5		T120	4		T89	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	4		T19	1		T207	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T205	10		T100	6		T103	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T50	2		T234	6		T266	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T267	10		T216	7		T268	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T20	2		T105	5		T43	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	456	1			T19	2		T33	4		T170	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T175	1		T244	1		T210	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T212	9		T223	13		T245	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T100	13		T151	12		T208	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T20	1		T106	3		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T13	1		T14	1		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	11		T106	9		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T83	6		T107	1		T102	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T52	1		T99	16		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T260	1		T124	5		T46	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	7		T21	2		T89	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T118	1		T120	8		T99	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T20	10		T119	1		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	12		T12	10		T205	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T118	1		T170	2		T89	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	1		T108	10		T130	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T53	1		T207	14		T103	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T147	3		T151	3		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T53	1		T106	6		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T15	1		T19	1		T207	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T21	1		T52	1		T120	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14829	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T169	1		T209	2		T50	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T175	10		T210	11		T269	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T212	7		T270	13		T228	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T100	6		T108	7		T131	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T20	2		T106	8		T169	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T219	12		T150	29		T271	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	2		T106	2		T241	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T83	7		T102	1		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T99	15		T90	13		T104	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T124	4		T46	16		T234	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	7		T89	5		T105	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T120	6		T99	8		T108	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T20	11		T97	2		T124	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	7		T12	2		T205	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T169	1		T92	10		T105	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T108	10		T130	10		T93	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T53	15		T207	16		T103	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T117	5		T140	8		T110	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T53	11		T106	5		T89	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	4		T19	1		T207	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T120	4		T205	10		T100	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	1		T100	7		T115	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	3		T106	9		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T13	1		T18	3		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T52	1		T106	3		T104	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T83	11		T107	1		T102	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T21	1		T99	16		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T120	7		T108	8		T91	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	9		T21	1		T89	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T118	1		T99	9		T117	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T20	12		T119	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	10		T12	7		T205	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T118	1		T170	1		T207	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	1		T147	1		T108	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T53	28		T103	13		T130	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T151	1		T103	7		T117	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T52	1		T106	6		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	5		T19	2		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T21	1		T205	11		T100	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T50	3		T234	7		T266	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T231	1		T225	1		T267	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15387	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T20	3		T105	6		T43	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T100	12		T151	11		T108	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T11	10		T106	2		T48	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T224	12		T174	30		T164	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T106	8		T241	9		T222	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T83	2		T124	2		T234	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T99	15		T90	11		T109	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T120	7		T108	11		T142	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T10	5		T89	3		T105	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T99	4		T117	13		T272	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	9		T105	5		T124	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	9		T12	5		T205	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T207	13		T89	10		T92	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T147	2		T108	9		T130	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T103	10		T226	9		T273	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T151	2		T103	7		T117	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T106	5		T120	4		T89	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T207	7		T206	1		T169	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T205	11		T100	6		T101	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T234	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T225	2		T274	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T212	8		T208	2		T223	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T105	5		T275	8		T276	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	441	1			T19	2		T33	4		T170	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T175	11		T244	1		T210	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T212	8		T223	1		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T100	7		T151	1		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T20	3		T106	9		T169	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T13	1		T14	1		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	3		T106	3		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T83	11		T107	1		T102	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T52	1		T99	16		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T260	1		T124	7		T46	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	9		T21	2		T89	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T118	1		T120	7		T99	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T20	12		T119	1		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	10		T12	7		T205	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T118	1		T170	2		T89	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	1		T108	11		T130	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T53	16		T207	17		T103	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T147	1		T151	1		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T53	12		T106	6		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T15	5		T19	2		T207	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T21	1		T52	1		T120	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14943	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T169	1		T209	12		T221	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T210	12		T225	2		T277	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T212	8		T223	12		T245	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T100	12		T151	11		T208	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T106	2		T105	5		T48	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T224	12		T174	30		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	10		T106	8		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T83	2		T164	13		T221	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T99	15		T90	11		T109	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T124	2		T46	13		T234	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	5		T89	3		T105	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T120	7		T99	4		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T20	9		T124	12		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	9		T12	5		T205	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T89	10		T92	4		T105	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T108	9		T130	9		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T207	13		T103	10		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T147	2		T151	2		T117	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T106	5		T89	14		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T207	7		T206	1		T103	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T120	4		T205	11		T100	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5