Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20751

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3271

1

T14

2

T15

5

T19

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17841

1

T31

1

T32

1

T38

2

auto[1]

6181

1

T10

14

T12

12

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	233	1			T170	1		T207	30		T99	13
values[0]	11	1			T105	11		-	-		-	-
values[1]	572	1			T21	1		T83	13		T118	1
values[2]	550	1			T10	14		T52	1		T106	11
values[3]	600	1			T19	2		T106	11		T170	1
values[4]	697	1			T20	21		T106	11		T119	1
values[5]	2796	1			T13	1		T18	3		T20	3
values[6]	686	1			T12	12		T21	1		T53	12
values[7]	873	1			T10	19		T11	13		T14	2
values[8]	758	1			T170	1		T89	40		T164	24
values[9]	916	1			T15	5		T52	1		T53	16
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	539	1			T21	1		T52	1		T89	9
values[1]	605	1			T10	14		T106	11		T115	1
values[2]	572	1			T19	2		T20	21		T106	11
values[3]	2917	1			T13	1		T18	3		T106	11
values[4]	587	1			T20	3		T21	1		T115	1
values[5]	716	1			T10	19		T12	12		T21	1
values[6]	863	1			T11	13		T14	2		T205	26
values[7]	680	1			T120	9		T170	1		T89	40
values[8]	926	1			T15	5		T52	1		T53	16
values[9]	127	1			T119	1		T99	13		T260	1
minimum	15490	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T21	1		T52	1		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T89	4		T164	1		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	7		T115	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T106	6		T109	10		T96	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T20	10		T170	1		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T19	1		T106	3		T100	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T13	1		T18	3		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T106	9		T151	12		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	1		T21	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T148	1		T90	12		T103	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	12		T12	10		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T21	1		T53	1		T206	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T11	11		T205	12		T100	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	2		T92	5		T48	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T120	5		T170	1		T89	26
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T164	14		T248	1		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T53	1		T207	14		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T15	1		T52	1		T120	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T99	5		T260	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T119	1		T185	3		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15291	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T278	1		T279	3		T280	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T124	4		T233	14		T125	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T89	5		T140	8		T241	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	7		T102	1		T103	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T106	5		T96	5		T266	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T20	11		T124	4		T46	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	1		T106	8		T100	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T219	12		T150	29		T135	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T106	2		T169	1		T108	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T20	2		T104	8		T110	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T90	13		T103	11		T111	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	7		T12	2		T207	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T53	11		T212	7		T108	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	2		T205	14		T100	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T92	10		T48	28		T112	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T120	4		T89	14		T209	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T164	10		T121	16		T105	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T53	15		T207	16		T142	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	4		T120	6		T99	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T99	8		T43	15		T50	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T185	2		T46	5		T126	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T281	12		T204	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T207	14		T99	5		T260	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T170	1		T185	3		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T105	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T21	1		T83	6		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T89	4		T164	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	7		T52	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T106	6		T109	10		T96	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T170	1		T93	1		T110	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	1		T106	3		T100	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T20	10		T119	1		T147	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T106	9		T169	1		T108	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T13	1		T18	3		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T148	1		T90	12		T151	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	10		T205	12		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T21	1		T53	1		T206	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T10	12		T11	11		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	2		T137	1		T92	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T170	1		T89	26		T132	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T164	14		T121	1		T105	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T53	1		T120	5		T223	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T15	1		T52	1		T119	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T207	16		T99	8		T43	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T185	2		T111	12		T126	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T105	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T83	7		T102	1		T124	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T89	5		T140	8		T50	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	7		T103	6		T140	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T106	5		T96	5		T241	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T110	8		T124	4		T46	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T19	1		T106	8		T100	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	11		T135	4		T175	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T106	2		T169	1		T108	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T20	2		T219	12		T150	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T90	13		T103	11		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	2		T205	10		T135	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T53	11		T212	7		T108	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T10	7		T11	2		T207	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T92	10		T48	28		T176	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T89	14		T110	1		T209	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T164	10		T121	16		T105	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T53	15		T120	4		T142	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T15	4		T120	6		T99	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T21	1		T52	1		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T89	6		T164	1		T140	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	9		T115	1		T102	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T106	6		T109	1		T96	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T20	12		T170	1		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	2		T106	9		T100	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1479	1			T13	1		T18	3		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T106	3		T151	1		T169	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T20	3		T21	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T148	1		T90	14		T103	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	10		T12	7		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T21	1		T53	12		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T11	3		T205	15		T100	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	2		T92	11		T48	30
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T120	5		T170	1		T89	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T164	11		T248	1		T121	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T53	16		T207	17		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T15	5		T52	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T99	9		T260	1		T43	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T119	1		T185	4		T46	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15405	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T278	1		T279	1		T280	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T124	6		T233	2		T272	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T89	3		T140	1		T241	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	5		T103	7		T110	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T106	5		T109	9		T96	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T20	9		T124	2		T46	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T106	2		T100	6		T117	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T224	12		T147	2		T151	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T106	8		T151	11		T108	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T101	18		T110	1		T124	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T90	11		T103	10		T234	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T10	9		T12	5		T207	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T206	1		T212	8		T108	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	10		T205	11		T100	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T92	4		T48	10		T222	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T120	4		T89	24		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T164	13		T105	6		T140	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T207	13		T142	7		T233	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T120	7		T99	15		T208	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T99	4		T168	2		T282	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T185	1		T126	12		T275	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T83	2		T105	5		T283	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T279	2		T204	3		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T207	17		T99	9		T260	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T170	1		T185	4		T111	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T105	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T21	1		T83	11		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T89	6		T164	1		T140	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	9		T52	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T106	6		T109	1		T96	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T170	1		T93	1		T110	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T19	2		T106	9		T100	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T20	12		T119	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T106	3		T169	2		T108	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T13	1		T18	3		T20	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T148	1		T90	14		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	7		T205	11		T135	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T21	1		T53	12		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T10	10		T11	3		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	2		T137	1		T92	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T170	1		T89	16		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T164	11		T121	17		T105	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T53	16		T120	5		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T15	5		T52	1		T119	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T207	13		T99	4		T213	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T185	1		T126	12		T167	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T105	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T83	2		T124	6		T225	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T89	3		T140	1		T210	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T10	5		T103	7		T221	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T106	5		T109	9		T96	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T110	7		T124	2		T46	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T106	2		T100	6		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T20	9		T147	2		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T106	8		T108	11		T117	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T224	12		T174	30		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T90	11		T151	11		T103	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T12	5		T205	11		T101	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T206	1		T212	8		T108	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T10	9		T11	10		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T92	4		T48	10		T222	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T89	24		T132	8		T209	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T164	13		T105	6		T140	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T120	4		T223	12		T142	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T120	7		T99	15		T208	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5