Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20655

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3367

1

T10

14

T11

13

T19

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17963

1

T31

1

T32

1

T38

2

auto[1]

6059

1

T10

33

T12

12

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	403	1			T19	2		T33	4		T34	5
values[0]	70	1			T151	12		T212	16		T223	13
values[1]	548	1			T11	13		T20	3		T100	19
values[2]	2800	1			T13	1		T14	1		T18	3
values[3]	800	1			T83	13		T52	1		T106	11
values[4]	517	1			T10	14		T21	2		T89	9
values[5]	566	1			T118	2		T119	1		T120	14
values[6]	798	1			T10	19		T12	12		T20	21
values[7]	606	1			T14	1		T53	16		T207	30
values[8]	713	1			T52	1		T53	12		T119	1
values[9]	1258	1			T15	5		T19	2		T21	1
minimum	14943	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	709	1			T14	1		T20	3		T106	11
values[1]	2912	1			T11	13		T13	1		T18	3
values[2]	722	1			T21	1		T83	13		T99	31
values[3]	554	1			T10	14		T21	1		T120	14
values[4]	515	1			T20	21		T118	1		T119	1
values[5]	873	1			T10	19		T12	12		T118	1
values[6]	679	1			T14	1		T53	28		T89	29
values[7]	598	1			T52	1		T106	11		T119	1
values[8]	1012	1			T15	5		T19	2		T21	1
values[9]	102	1			T207	14		T103	6		T50	3
minimum	15346	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	1		T100	13		T115	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T20	1		T106	3		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T13	1		T18	3		T224	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	11		T52	1		T106	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T83	6		T99	16		T90	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T21	1		T107	1		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T21	1		T120	8		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	7		T89	4		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T118	1		T119	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	10		T116	1		T105	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T10	12		T12	10		T207	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T118	1		T170	1		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	1		T130	1		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T53	2		T89	15		T147	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T52	1		T135	1		T103	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T106	6		T119	1		T120	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T15	1		T170	1		T205	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T19	1		T21	1		T206	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T207	8		T221	3		T234	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T103	4		T50	1		T267	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15229	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T176	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T100	6		T212	7		T131	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T20	2		T106	8		T169	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T219	12		T150	29		T164	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	2		T106	2		T104	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T83	7		T99	15		T90	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T104	8		T185	2		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T120	6		T185	1		T124	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	7		T89	5		T105	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T99	8		T108	7		T97	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T20	11		T105	9		T124	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T10	7		T12	2		T207	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T169	1		T92	10		T110	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T130	3		T93	14		T110	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	26		T89	14		T108	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T135	13		T103	4		T117	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T106	5		T120	4		T100	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	4		T205	10		T169	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T19	1		T121	16		T140	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T207	6		T234	6		T266	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T103	2		T50	2		T267	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T176	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	388	1			T19	2		T33	4		T34	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T284	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T151	12		T212	9		T223	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T285	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T100	13		T208	3		T131	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	11		T20	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T13	1		T14	1		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T106	3		T115	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T83	6		T99	16		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T52	1		T106	9		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T21	1		T260	1		T185	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	7		T21	1		T89	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T118	1		T119	1		T120	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T118	1		T116	1		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	12		T12	10		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T20	10		T170	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T14	1		T207	14		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T53	1		T103	12		T130	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T52	1		T238	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T53	1		T119	1		T89	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T15	1		T170	1		T207	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T19	1		T21	1		T106	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14829	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T266	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T284	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T212	7		T270	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T285	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T100	6		T131	1		T125	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	2		T20	2		T169	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T219	12		T150	29		T271	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T106	8		T104	14		T241	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T83	7		T99	15		T90	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T106	2		T104	8		T185	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T185	1		T175	13		T46	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T10	7		T89	5		T105	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T120	6		T99	8		T108	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T142	5		T124	12		T50	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	7		T12	2		T205	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T20	11		T169	1		T92	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T207	16		T93	14		T125	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T53	15		T103	11		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T130	3		T117	5		T140	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T53	11		T89	14		T135	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T15	4		T207	6		T205	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T19	1		T106	5		T120	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	1		T100	7		T115	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T20	3		T106	9		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T13	1		T18	3		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	3		T52	1		T106	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T83	11		T99	16		T90	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T21	1		T107	1		T104	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T21	1		T120	7		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	9		T89	6		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T118	1		T119	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T20	12		T116	1		T105	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T10	10		T12	7		T207	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T118	1		T170	1		T169	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	1		T130	4		T93	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T53	28		T89	15		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T52	1		T135	14		T103	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T106	6		T119	1		T120	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T15	5		T170	1		T205	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T19	2		T21	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T207	7		T221	1		T234	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T103	6		T50	3		T267	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15331	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T176	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T100	12		T151	11		T212	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T106	2		T108	7		T105	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T224	12		T174	30		T164	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	10		T106	8		T241	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T83	2		T99	15		T90	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T109	9		T185	1		T123	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T120	7		T124	12		T46	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T10	5		T89	3		T105	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T99	4		T108	11		T272	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T20	9		T105	5		T124	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	9		T12	5		T207	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T92	4		T110	1		T126	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T226	9		T214	12		T286	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T89	14		T147	2		T108	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T103	7		T117	5		T132	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T106	5		T120	4		T100	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T205	11		T169	1		T101	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T206	1		T140	8		T110	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T207	7		T221	2		T234	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T287	2		T274	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T223	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	395	1			T19	2		T33	4		T34	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T284	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T151	1		T212	8		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T285	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T100	7		T208	1		T131	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	3		T20	3		T169	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T13	1		T14	1		T18	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T106	9		T115	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T83	11		T99	16		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T52	1		T106	3		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T21	1		T260	1		T185	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	9		T21	1		T89	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T118	1		T119	1		T120	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T118	1		T116	1		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	10		T12	7		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T20	12		T170	1		T169	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	1		T207	17		T93	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T53	16		T103	13		T130	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T52	1		T238	1		T130	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T53	12		T119	1		T89	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T15	5		T170	1		T207	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	451	1			T19	2		T21	1		T106	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14943	1			T31	1		T32	1		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T151	11		T212	8		T223	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T100	12		T208	2		T112	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	10		T108	7		T105	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T224	12		T174	30		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T106	2		T241	9		T222	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T83	2		T99	15		T90	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T106	8		T109	9		T185	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T46	13		T272	12		T288	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	5		T89	3		T105	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T120	7		T99	4		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T142	7		T124	12		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	9		T12	5		T205	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T20	9		T92	4		T105	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T207	13		T226	9		T214	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T103	10		T130	9		T126	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T117	5		T132	8		T140	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T89	14		T147	2		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T207	7		T205	11		T169	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T106	5		T120	4		T100	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5