Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20752

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3270

1

T14

2

T15

5

T19

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17897

1

T31

1

T32

1

T38

2

auto[1]

6125

1

T10

14

T12

12

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T119	1		T295	19		T282	3
values[0]	92	1			T89	9		T246	1		T296	14
values[1]	466	1			T21	1		T83	13		T118	1
values[2]	588	1			T10	14		T52	1		T106	11
values[3]	568	1			T19	2		T106	11		T170	1
values[4]	670	1			T20	21		T119	1		T147	3
values[5]	2810	1			T13	1		T18	3		T20	3
values[6]	654	1			T12	12		T21	2		T53	12
values[7]	977	1			T10	19		T11	13		T14	2
values[8]	694	1			T170	1		T89	40		T164	24
values[9]	1150	1			T15	5		T52	1		T53	16
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	686	1			T21	1		T83	13		T52	1
values[1]	609	1			T10	14		T106	11		T115	1
values[2]	536	1			T19	2		T20	21		T106	11
values[3]	2942	1			T13	1		T18	3		T106	11
values[4]	564	1			T20	3		T21	1		T115	1
values[5]	737	1			T10	19		T12	12		T21	1
values[6]	804	1			T11	13		T14	2		T170	1
values[7]	732	1			T120	9		T89	40		T223	13
values[8]	865	1			T15	5		T52	1		T53	16
values[9]	183	1			T119	1		T207	30		T99	13
minimum	15364	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T21	1		T83	6		T52	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T89	4		T164	1		T140	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	7		T115	1		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T106	6		T109	10		T96	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	10		T170	1		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	1		T106	3		T100	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T13	1		T18	3		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T106	9		T151	12		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T20	1		T21	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T148	1		T90	12		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	12		T12	10		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T21	1		T53	1		T206	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	11		T170	1		T205	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	2		T92	5		T48	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T120	5		T89	26		T223	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T164	14		T248	1		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T53	1		T91	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T15	1		T52	1		T120	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T207	14		T99	5		T260	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T119	1		T185	3		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15227	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T281	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T83	7		T124	4		T125	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T89	5		T140	8		T241	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	7		T102	1		T103	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T106	5		T96	5		T266	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T20	11		T124	4		T46	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	1		T106	8		T100	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T219	12		T150	29		T135	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T106	2		T169	1		T108	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T20	2		T104	8		T110	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T90	13		T111	3		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	7		T12	2		T207	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T53	11		T212	7		T108	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	2		T205	14		T100	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T92	10		T48	14		T261	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T120	4		T89	14		T209	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T164	10		T121	16		T105	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T53	15		T233	5		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T15	4		T120	6		T99	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T207	16		T99	8		T142	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T185	2		T46	5		T275	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T31	1		T32	1		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T281	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T295	10		T282	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T119	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T246	1		T297	13		T298	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T89	4		T296	8		T299	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T21	1		T83	6		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T164	1		T140	2		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	7		T52	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T106	6		T109	10		T241	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T170	1		T93	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	1		T106	3		T100	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T20	10		T119	1		T147	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T169	1		T108	12		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T13	1		T18	3		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T106	9		T148	1		T90	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	10		T21	1		T205	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	1		T53	1		T206	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T10	12		T11	11		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	2		T137	1		T92	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T170	1		T89	26		T132	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T164	14		T121	1		T105	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T53	1		T120	5		T207	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T15	1		T52	1		T120	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T295	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T297	11		T298	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T89	5		T296	6		T216	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T83	7		T105	5		T124	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T140	8		T50	2		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T10	7		T102	1		T103	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T106	5		T241	13		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T175	13		T46	4		T234	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T19	1		T106	8		T100	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T20	11		T135	4		T124	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T169	1		T108	7		T104	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T20	2		T219	12		T150	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T106	2		T90	13		T103	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	2		T205	10		T135	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T53	11		T212	7		T108	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T10	7		T11	2		T207	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T92	10		T117	5		T132	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T89	14		T209	2		T125	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T164	10		T121	16		T105	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T53	15		T120	4		T207	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T15	4		T120	6		T99	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T21	1		T83	11		T52	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T89	6		T164	1		T140	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	9		T115	1		T102	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T106	6		T109	1		T96	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T20	12		T170	1		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	2		T106	9		T100	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T13	1		T18	3		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T106	3		T151	1		T169	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T20	3		T21	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T148	1		T90	14		T111	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	10		T12	7		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T21	1		T53	12		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T11	3		T170	1		T205	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	2		T92	11		T48	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T120	5		T89	16		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T164	11		T248	1		T121	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T53	16		T91	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T15	5		T52	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T207	17		T99	9		T260	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T119	1		T185	4		T46	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15342	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T281	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T83	2		T124	6		T272	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T89	3		T140	1		T241	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	5		T103	7		T110	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T106	5		T109	9		T96	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T20	9		T124	2		T46	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T106	2		T100	6		T117	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T224	12		T147	2		T151	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T106	8		T151	11		T108	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T101	18		T110	1		T124	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T90	11		T234	10		T251	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T10	9		T12	5		T207	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T206	1		T212	8		T108	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	10		T205	11		T100	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T92	4		T48	10		T222	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T120	4		T89	24		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T164	13		T105	6		T140	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T221	9		T233	16		T113	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T120	7		T99	15		T208	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T207	13		T99	4		T142	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T185	1		T275	6		T276	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T105	5		T283	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T295	10		T282	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T119	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T246	1		T297	12		T298	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T89	6		T296	10		T299	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T21	1		T83	11		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T164	1		T140	9		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T10	9		T52	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T106	6		T109	1		T241	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T170	1		T93	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T19	2		T106	9		T100	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T20	12		T119	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T169	2		T108	8		T104	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T13	1		T18	3		T20	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T106	3		T148	1		T90	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	7		T21	1		T205	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T21	1		T53	12		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T10	10		T11	3		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T14	2		T137	1		T92	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T170	1		T89	16		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T164	11		T121	17		T105	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T53	16		T120	5		T207	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T15	5		T52	1		T120	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T295	9		T282	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T297	12		T298	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T89	3		T296	4		T204	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T83	2		T105	5		T124	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T140	1		T210	3		T214	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T10	5		T103	7		T110	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T106	5		T109	9		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T46	12		T234	9		T253	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T106	2		T100	6		T96	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	9		T147	2		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T108	11		T117	1		T300	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T224	12		T174	30		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T106	8		T90	11		T151	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	5		T205	11		T101	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T206	1		T212	8		T108	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	9		T11	10		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T92	4		T117	5		T132	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T89	24		T132	8		T209	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T164	13		T105	6		T117	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T120	4		T207	13		T99	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T120	7		T99	15		T208	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5