Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24022

1

T31

1

T32

1

T38

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20771

1

T31

1

T32

1

T38

2

auto[ADC_CTRL_FILTER_COND_OUT]

3251

1

T10

14

T14

2

T19

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18452

1

T31

1

T32

1

T38

2

auto[1]

5570

1

T10

33

T11

13

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19872

1

T9

11

T10

19

T11

31

auto[1]

4150

1

T31

1

T32

1

T38

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T125	5		T301	22		-	-
values[0]	120	1			T102	2		T103	6		T302	12
values[1]	555	1			T11	13		T15	5		T21	2
values[2]	770	1			T106	11		T119	1		T205	22
values[3]	726	1			T21	1		T148	1		T169	3
values[4]	543	1			T12	12		T52	1		T106	11
values[5]	2835	1			T13	1		T14	1		T18	3
values[6]	518	1			T10	19		T170	1		T205	26
values[7]	783	1			T118	1		T120	9		T170	1
values[8]	575	1			T106	11		T100	13		T151	12
values[9]	1240	1			T10	14		T14	1		T19	2
minimum	15330	1			T31	1		T32	1		T38	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	833	1			T11	13		T15	5		T21	2
values[1]	683	1			T21	1		T148	1		T116	1
values[2]	738	1			T12	12		T52	1		T106	11
values[3]	2665	1			T13	1		T18	3		T118	1
values[4]	706	1			T14	1		T207	30		T89	11
values[5]	671	1			T10	19		T170	2		T205	26
values[6]	643	1			T118	1		T120	9		T207	14
values[7]	616	1			T20	24		T106	11		T89	9
values[8]	899	1			T10	14		T14	1		T83	13
values[9]	188	1			T19	2		T53	12		T130	4
minimum	15380	1			T31	1		T32	1		T38	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

3582

1

T10

14

T11

10

T12

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T11	11		T15	1		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T21	1		T52	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T21	1		T148	1		T116	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T169	2		T105	7		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	10		T52	1		T106	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T100	13		T135	13		T101	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T13	1		T18	3		T224	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T118	1		T115	1		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T89	11		T135	1		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	1		T207	14		T131	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	12		T170	2		T205	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T89	15		T223	13		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T120	5		T100	7		T108	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T118	1		T207	8		T99	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T20	11		T89	4		T248	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T106	9		T151	12		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T83	6		T53	1		T120	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T10	7		T14	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T53	1		T241	10		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T19	1		T130	1		T303	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15243	1			T9	11		T11	20		T16	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T304	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	2		T15	4		T106	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T124	12		T46	5		T227	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T103	11		T130	10		T132	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T169	1		T105	7		T93	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	2		T106	8		T93	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T100	6		T135	4		T103	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T219	12		T150	29		T108	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T240	6		T210	13		T296	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T135	13		T104	8		T140	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T207	16		T131	1		T96	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	7		T205	14		T212	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T89	14		T104	14		T209	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T120	4		T100	6		T108	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T207	6		T99	8		T164	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T20	13		T89	5		T110	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T106	2		T169	1		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T83	7		T53	15		T120	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	7		T102	1		T117	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T53	11		T241	13		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T19	1		T130	3		T305	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T31	1		T32	1		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T125	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T301	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T102	2		T103	4		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T302	6		T307	1		T308	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	11		T15	1		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T21	1		T52	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T106	6		T119	1		T205	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T100	13		T135	13		T105	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T21	1		T148	1		T132	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T169	2		T101	19		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	10		T52	1		T106	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T115	1		T238	1		T103	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T13	1		T18	3		T224	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	1		T118	1		T207	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	12		T170	1		T205	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T223	13		T104	1		T96	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T120	5		T170	1		T212	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T118	1		T207	8		T99	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T100	7		T108	8		T248	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T106	9		T151	12		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T20	11		T83	6		T53	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T10	7		T14	1		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15216	1			T9	11		T11	20		T16	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T125	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T301	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T103	2		T243	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T302	6		T308	9		T309	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	2		T15	4		T99	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T124	12		T46	5		T310	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T106	5		T205	10		T108	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T100	6		T135	4		T105	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T132	16		T93	14		T185	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T169	1		T140	1		T311	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	2		T106	8		T108	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T103	4		T131	1		T240	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T219	12		T150	29		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T207	16		T112	6		T210	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T10	7		T205	14		T50	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T104	14		T96	5		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T120	4		T212	7		T169	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T207	6		T99	8		T89	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T100	6		T108	7		T110	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T106	2		T169	1		T164	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T20	13		T83	7		T53	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T10	7		T19	1		T102	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	1		T32	1		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	3		T15	5		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T21	1		T52	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T21	1		T148	1		T116	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T169	2		T105	8		T93	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	7		T52	1		T106	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T100	7		T135	5		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T13	1		T18	3		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T118	1		T115	1		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T89	1		T135	14		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T207	17		T131	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	10		T170	2		T205	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T89	15		T223	1		T104	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T120	5		T100	7		T108	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T118	1		T207	7		T99	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T20	15		T89	6		T248	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T106	3		T151	1		T169	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T83	11		T53	16		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T10	9		T14	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T53	12		T241	14		T229	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T19	2		T130	4		T303	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15344	1			T31	1		T32	1		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T304	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	10		T106	5		T99	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T147	2		T124	12		T222	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T103	10		T130	9		T132	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T169	1		T105	6		T215	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T12	5		T106	2		T222	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T100	12		T135	12		T101	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T224	12		T206	1		T151	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T210	14		T296	1		T261	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T89	10		T140	1		T124	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T207	13		T96	2		T112	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	9		T205	11		T212	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T89	14		T223	12		T209	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T120	4		T100	6		T108	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T207	7		T99	4		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T20	9		T89	3		T185	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T106	8		T151	11		T117	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T83	2		T120	7		T92	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	5		T117	13		T109	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T241	9		T312	14		T313	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T305	1		T314	5		T258	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T245	12		T262	10		T159	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T304	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T125	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T301	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T102	2		T103	6		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T302	7		T307	1		T308	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	3		T15	5		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T21	1		T52	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T106	6		T119	1		T205	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T100	7		T135	5		T105	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T21	1		T148	1		T132	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T169	2		T101	1		T140	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	7		T52	1		T106	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T115	1		T238	1		T103	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T13	1		T18	3		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	1		T118	1		T207	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	10		T170	1		T205	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T223	1		T104	15		T96	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T120	5		T170	1		T212	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T118	1		T207	7		T99	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T100	7		T108	8		T248	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T106	3		T151	1		T169	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	424	1			T20	15		T83	11		T53	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T10	9		T14	1		T19	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15330	1			T31	1		T32	1		T38	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T301	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T243	13		T291	10		T202	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T302	5		T308	11		T309	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	10		T99	15		T90	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T147	2		T124	12		T222	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T106	5		T205	11		T208	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T100	12		T135	12		T105	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T132	11		T234	9		T210	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T169	1		T101	18		T261	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	5		T106	2		T206	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T103	7		T142	3		T233	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T224	12		T89	10		T151	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T207	13		T112	6		T210	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	9		T205	11		T226	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T223	12		T96	2		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T120	4		T212	8		T105	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T207	7		T99	4		T89	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T100	6		T108	7		T185	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T106	8		T151	11		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T20	9		T83	2		T120	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	5		T117	13		T109	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20440

1

T31

1

T32

1

T38

2

auto[1]

auto[0]

3582

1

T10

14

T11

10

T12

5