Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 98.98 95.69 100.00 100.00 98.18 98.64 91.79


Total test records in report: 908
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T256 /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2633903066 Jan 21 03:58:16 PM PST 24 Jan 21 04:00:58 PM PST 24 322548043463 ps
T779 /workspace/coverage/default/24.adc_ctrl_filters_polled.4149520909 Jan 21 03:54:04 PM PST 24 Jan 21 04:00:26 PM PST 24 164177610327 ps
T780 /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2978172809 Jan 21 04:34:39 PM PST 24 Jan 21 04:44:54 PM PST 24 489347918812 ps
T781 /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3648815429 Jan 21 03:54:49 PM PST 24 Jan 21 03:58:00 PM PST 24 168298493712 ps
T202 /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3368610321 Jan 21 03:57:01 PM PST 24 Jan 21 04:03:27 PM PST 24 495801136063 ps
T782 /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2985243456 Jan 21 07:23:51 PM PST 24 Jan 21 07:44:57 PM PST 24 495889672772 ps
T287 /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3203792478 Jan 21 04:32:46 PM PST 24 Jan 21 04:39:38 PM PST 24 158835481702 ps
T783 /workspace/coverage/default/49.adc_ctrl_poweron_counter.1442703596 Jan 21 04:01:08 PM PST 24 Jan 21 04:01:21 PM PST 24 3980929875 ps
T784 /workspace/coverage/default/6.adc_ctrl_alert_test.1880478272 Jan 21 03:50:41 PM PST 24 Jan 21 03:50:43 PM PST 24 415716382 ps
T785 /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3484153633 Jan 21 03:55:26 PM PST 24 Jan 21 03:58:47 PM PST 24 225722851970 ps
T786 /workspace/coverage/default/0.adc_ctrl_poweron_counter.1725694066 Jan 21 04:13:19 PM PST 24 Jan 21 04:13:29 PM PST 24 2920958344 ps
T218 /workspace/coverage/default/7.adc_ctrl_clock_gating.2095401512 Jan 21 03:50:54 PM PST 24 Jan 21 03:54:05 PM PST 24 326531537366 ps
T787 /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.747000935 Jan 21 03:54:11 PM PST 24 Jan 21 04:07:07 PM PST 24 335027777841 ps
T788 /workspace/coverage/default/32.adc_ctrl_smoke.3908143339 Jan 21 03:56:20 PM PST 24 Jan 21 03:56:29 PM PST 24 6076904319 ps
T789 /workspace/coverage/default/4.adc_ctrl_fsm_reset.2317923495 Jan 21 03:50:34 PM PST 24 Jan 21 03:55:10 PM PST 24 97924463242 ps
T790 /workspace/coverage/default/8.adc_ctrl_clock_gating.1272961016 Jan 21 03:50:53 PM PST 24 Jan 21 04:03:25 PM PST 24 322109948761 ps
T217 /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2377088681 Jan 21 03:51:25 PM PST 24 Jan 21 03:54:48 PM PST 24 387221126701 ps
T791 /workspace/coverage/default/23.adc_ctrl_alert_test.259145598 Jan 21 03:54:04 PM PST 24 Jan 21 03:54:05 PM PST 24 314461488 ps
T268 /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.301534305 Jan 21 03:53:48 PM PST 24 Jan 21 03:55:38 PM PST 24 261563856327 ps
T792 /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3820522356 Jan 21 04:19:49 PM PST 24 Jan 21 04:23:58 PM PST 24 363841959305 ps
T793 /workspace/coverage/default/8.adc_ctrl_filters_polled.2226083253 Jan 21 03:50:52 PM PST 24 Jan 21 03:52:23 PM PST 24 163818349190 ps
T794 /workspace/coverage/default/36.adc_ctrl_stress_all.4082798813 Jan 21 03:57:40 PM PST 24 Jan 21 04:01:44 PM PST 24 373066189406 ps
T795 /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3928803920 Jan 21 03:58:26 PM PST 24 Jan 21 03:59:15 PM PST 24 29217541906 ps
T197 /workspace/coverage/default/12.adc_ctrl_stress_all.3672388368 Jan 21 03:51:04 PM PST 24 Jan 21 04:09:19 PM PST 24 195534678836 ps
T796 /workspace/coverage/default/2.adc_ctrl_filters_polled.1209121902 Jan 21 03:50:28 PM PST 24 Jan 21 03:56:25 PM PST 24 160141663551 ps
T797 /workspace/coverage/default/4.adc_ctrl_smoke.4057338661 Jan 21 03:50:24 PM PST 24 Jan 21 03:50:40 PM PST 24 5899210529 ps
T798 /workspace/coverage/default/25.adc_ctrl_poweron_counter.552133774 Jan 21 03:54:46 PM PST 24 Jan 21 03:54:52 PM PST 24 4759015373 ps
T799 /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1196353987 Jan 21 03:58:17 PM PST 24 Jan 21 04:02:52 PM PST 24 234164212129 ps
T800 /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2836566726 Jan 21 03:57:46 PM PST 24 Jan 21 04:01:22 PM PST 24 336271125497 ps
T801 /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.879325378 Jan 21 03:59:01 PM PST 24 Jan 21 04:02:10 PM PST 24 492511965182 ps
T167 /workspace/coverage/default/36.adc_ctrl_filters_wakeup.213165900 Jan 21 06:07:01 PM PST 24 Jan 21 06:10:10 PM PST 24 323769562675 ps
T802 /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1985206688 Jan 21 03:51:20 PM PST 24 Jan 21 03:54:36 PM PST 24 328156354813 ps
T803 /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1919952198 Jan 21 03:54:06 PM PST 24 Jan 21 03:54:17 PM PST 24 46999682358 ps
T284 /workspace/coverage/default/44.adc_ctrl_filters_interrupt.597446563 Jan 21 03:59:36 PM PST 24 Jan 21 04:03:59 PM PST 24 335682949155 ps
T804 /workspace/coverage/default/6.adc_ctrl_poweron_counter.1910717228 Jan 21 03:50:41 PM PST 24 Jan 21 03:50:49 PM PST 24 2759521998 ps
T805 /workspace/coverage/default/37.adc_ctrl_poweron_counter.1738860166 Jan 21 03:57:55 PM PST 24 Jan 21 03:58:01 PM PST 24 3616964281 ps
T806 /workspace/coverage/default/0.adc_ctrl_stress_all.1454188806 Jan 21 03:50:15 PM PST 24 Jan 21 04:04:39 PM PST 24 455799129843 ps
T807 /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2470283299 Jan 21 03:56:53 PM PST 24 Jan 21 04:16:29 PM PST 24 494571793789 ps
T808 /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.872930026 Jan 21 03:59:03 PM PST 24 Jan 21 04:09:05 PM PST 24 489566646491 ps
T809 /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2809342327 Jan 21 04:52:02 PM PST 24 Jan 21 04:58:44 PM PST 24 162081495915 ps
T810 /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.233522648 Jan 21 03:58:40 PM PST 24 Jan 21 04:01:25 PM PST 24 322743252068 ps
T811 /workspace/coverage/default/28.adc_ctrl_clock_gating.2639833355 Jan 21 03:55:24 PM PST 24 Jan 21 04:00:23 PM PST 24 337320165424 ps
T812 /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3084326114 Jan 21 03:53:56 PM PST 24 Jan 21 04:00:24 PM PST 24 161747302006 ps
T292 /workspace/coverage/default/16.adc_ctrl_stress_all.3524462069 Jan 21 03:52:02 PM PST 24 Jan 21 04:01:43 PM PST 24 566483647099 ps
T813 /workspace/coverage/default/41.adc_ctrl_stress_all.3672370964 Jan 21 03:58:54 PM PST 24 Jan 21 04:03:16 PM PST 24 382003663635 ps
T168 /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2325708586 Jan 21 03:50:39 PM PST 24 Jan 21 03:53:12 PM PST 24 490450795697 ps
T282 /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4111000953 Jan 21 04:43:46 PM PST 24 Jan 21 04:48:43 PM PST 24 329179178569 ps
T814 /workspace/coverage/default/23.adc_ctrl_fsm_reset.2767514797 Jan 21 03:54:05 PM PST 24 Jan 21 04:00:50 PM PST 24 99444087612 ps
T343 /workspace/coverage/default/31.adc_ctrl_fsm_reset.2084160829 Jan 21 03:56:12 PM PST 24 Jan 21 04:02:18 PM PST 24 113466588043 ps
T815 /workspace/coverage/default/27.adc_ctrl_smoke.1780362961 Jan 21 03:55:09 PM PST 24 Jan 21 03:55:20 PM PST 24 5870922494 ps
T320 /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1207548136 Jan 21 04:10:39 PM PST 24 Jan 21 04:29:51 PM PST 24 486443225857 ps
T816 /workspace/coverage/default/31.adc_ctrl_poweron_counter.2231522119 Jan 21 03:56:13 PM PST 24 Jan 21 03:56:23 PM PST 24 3795022420 ps
T817 /workspace/coverage/default/38.adc_ctrl_fsm_reset.1087017310 Jan 21 03:58:11 PM PST 24 Jan 21 04:05:36 PM PST 24 123458920410 ps
T818 /workspace/coverage/default/38.adc_ctrl_clock_gating.2519384686 Jan 21 03:58:15 PM PST 24 Jan 21 04:01:55 PM PST 24 333241884265 ps
T819 /workspace/coverage/default/26.adc_ctrl_poweron_counter.2611741067 Jan 21 03:54:52 PM PST 24 Jan 21 03:55:01 PM PST 24 4906833195 ps
T820 /workspace/coverage/default/41.adc_ctrl_poweron_counter.219463145 Jan 21 03:58:52 PM PST 24 Jan 21 03:59:01 PM PST 24 3737624500 ps
T308 /workspace/coverage/default/31.adc_ctrl_clock_gating.2119626607 Jan 21 03:56:13 PM PST 24 Jan 21 04:03:20 PM PST 24 332760590412 ps
T821 /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1010972809 Jan 21 03:56:49 PM PST 24 Jan 21 04:02:16 PM PST 24 495176498174 ps
T822 /workspace/coverage/default/35.adc_ctrl_clock_gating.497269817 Jan 21 03:57:22 PM PST 24 Jan 21 03:59:04 PM PST 24 163365637509 ps
T823 /workspace/coverage/default/40.adc_ctrl_clock_gating.2611749004 Jan 21 03:58:42 PM PST 24 Jan 21 04:02:32 PM PST 24 331206550410 ps
T824 /workspace/coverage/default/29.adc_ctrl_poweron_counter.1242656787 Jan 21 03:55:37 PM PST 24 Jan 21 03:55:41 PM PST 24 4073355034 ps
T825 /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3055179919 Jan 21 03:57:44 PM PST 24 Jan 21 04:16:39 PM PST 24 495436086844 ps
T826 /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2205815230 Jan 21 03:53:35 PM PST 24 Jan 21 03:59:40 PM PST 24 339284929374 ps
T827 /workspace/coverage/default/27.adc_ctrl_poweron_counter.2205706715 Jan 21 03:55:13 PM PST 24 Jan 21 03:55:18 PM PST 24 3939620489 ps
T274 /workspace/coverage/default/39.adc_ctrl_filters_both.2547792957 Jan 21 03:58:28 PM PST 24 Jan 21 04:17:21 PM PST 24 495534322634 ps
T331 /workspace/coverage/default/12.adc_ctrl_clock_gating.2368317245 Jan 21 03:51:03 PM PST 24 Jan 21 03:54:28 PM PST 24 324929970460 ps
T828 /workspace/coverage/default/47.adc_ctrl_alert_test.607374171 Jan 21 04:26:17 PM PST 24 Jan 21 04:26:20 PM PST 24 425118656 ps
T829 /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2720919734 Jan 21 03:58:47 PM PST 24 Jan 21 04:05:27 PM PST 24 331812933887 ps
T830 /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2797797248 Jan 21 03:52:12 PM PST 24 Jan 21 03:55:14 PM PST 24 158936704639 ps
T831 /workspace/coverage/default/22.adc_ctrl_alert_test.1168707445 Jan 21 03:53:52 PM PST 24 Jan 21 03:53:55 PM PST 24 474175970 ps
T832 /workspace/coverage/default/14.adc_ctrl_filters_polled.1912222858 Jan 21 03:51:19 PM PST 24 Jan 21 03:53:04 PM PST 24 162609881669 ps
T42 /workspace/coverage/default/4.adc_ctrl_sec_cm.3933666381 Jan 21 03:50:26 PM PST 24 Jan 21 03:50:30 PM PST 24 3803351858 ps
T309 /workspace/coverage/default/9.adc_ctrl_filters_both.4693228 Jan 21 03:50:55 PM PST 24 Jan 21 03:55:13 PM PST 24 162518215429 ps
T833 /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3645008599 Jan 21 03:51:19 PM PST 24 Jan 21 03:54:13 PM PST 24 328161146161 ps
T834 /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1837818545 Jan 21 04:33:21 PM PST 24 Jan 21 04:38:21 PM PST 24 330429642860 ps
T835 /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2217981208 Jan 21 03:52:23 PM PST 24 Jan 21 03:54:54 PM PST 24 63123660233 ps
T345 /workspace/coverage/default/42.adc_ctrl_fsm_reset.2638208090 Jan 21 03:59:16 PM PST 24 Jan 21 04:08:31 PM PST 24 107976374882 ps
T836 /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3457838554 Jan 21 03:57:24 PM PST 24 Jan 21 04:00:43 PM PST 24 164117894477 ps
T837 /workspace/coverage/default/48.adc_ctrl_clock_gating.4163831459 Jan 21 04:00:50 PM PST 24 Jan 21 04:05:05 PM PST 24 497954903287 ps
T239 /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3942032093 Jan 21 04:43:32 PM PST 24 Jan 21 04:50:24 PM PST 24 164878857231 ps
T838 /workspace/coverage/default/6.adc_ctrl_filters_polled.342044257 Jan 21 03:50:37 PM PST 24 Jan 21 03:57:00 PM PST 24 323812239913 ps
T839 /workspace/coverage/default/28.adc_ctrl_smoke.3989735712 Jan 21 03:55:12 PM PST 24 Jan 21 03:55:17 PM PST 24 5982171838 ps
T840 /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.718833971 Jan 21 03:57:13 PM PST 24 Jan 21 04:00:57 PM PST 24 434726503348 ps
T841 /workspace/coverage/default/46.adc_ctrl_smoke.2746502214 Jan 21 05:06:53 PM PST 24 Jan 21 05:07:02 PM PST 24 5767413010 ps
T842 /workspace/coverage/default/26.adc_ctrl_smoke.1959493509 Jan 21 03:54:44 PM PST 24 Jan 21 03:54:58 PM PST 24 5701598053 ps
T843 /workspace/coverage/default/5.adc_ctrl_clock_gating.3797363190 Jan 21 03:50:49 PM PST 24 Jan 21 03:53:50 PM PST 24 165770365459 ps
T844 /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1741008963 Jan 21 03:52:18 PM PST 24 Jan 21 04:02:25 PM PST 24 493532528638 ps
T845 /workspace/coverage/default/24.adc_ctrl_fsm_reset.3650273436 Jan 21 03:54:23 PM PST 24 Jan 21 04:03:01 PM PST 24 130015019871 ps
T846 /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3834126567 Jan 21 03:51:19 PM PST 24 Jan 21 03:53:12 PM PST 24 39775031436 ps
T173 /workspace/coverage/default/46.adc_ctrl_filters_both.592080910 Jan 21 04:28:10 PM PST 24 Jan 21 04:34:11 PM PST 24 327266275335 ps
T847 /workspace/coverage/default/10.adc_ctrl_lowpower_counter.582716001 Jan 21 03:51:01 PM PST 24 Jan 21 03:51:20 PM PST 24 24584373812 ps
T848 /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3039795142 Jan 21 03:56:31 PM PST 24 Jan 21 03:57:50 PM PST 24 38181538906 ps
T849 /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1405359271 Jan 21 05:45:23 PM PST 24 Jan 21 05:54:24 PM PST 24 497763689367 ps
T850 /workspace/coverage/default/15.adc_ctrl_poweron_counter.3220866481 Jan 21 04:13:15 PM PST 24 Jan 21 04:13:24 PM PST 24 3258955834 ps
T851 /workspace/coverage/default/13.adc_ctrl_poweron_counter.447772417 Jan 21 03:51:12 PM PST 24 Jan 21 03:51:21 PM PST 24 3201076106 ps
T852 /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.291010168 Jan 21 03:57:03 PM PST 24 Jan 21 04:02:30 PM PST 24 496190191675 ps
T853 /workspace/coverage/default/3.adc_ctrl_lowpower_counter.115714103 Jan 21 04:02:30 PM PST 24 Jan 21 04:03:39 PM PST 24 24851984997 ps
T854 /workspace/coverage/default/0.adc_ctrl_fsm_reset.1644615072 Jan 21 03:50:13 PM PST 24 Jan 21 03:56:54 PM PST 24 107032455020 ps
T855 /workspace/coverage/default/13.adc_ctrl_filters_both.4104560307 Jan 21 03:51:19 PM PST 24 Jan 21 03:57:53 PM PST 24 165272780549 ps
T856 /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1643473426 Jan 21 03:57:47 PM PST 24 Jan 21 04:04:16 PM PST 24 165216926743 ps
T857 /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3111613721 Jan 21 03:59:27 PM PST 24 Jan 21 04:00:56 PM PST 24 162748145682 ps
T858 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1810240573 Jan 21 07:41:43 PM PST 24 Jan 21 07:42:22 PM PST 24 717599044 ps
T859 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1358733348 Jan 21 07:42:55 PM PST 24 Jan 21 07:43:15 PM PST 24 9198940469 ps
T860 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3721833732 Jan 21 07:36:58 PM PST 24 Jan 21 07:37:21 PM PST 24 413505654 ps
T861 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2079351327 Jan 21 07:43:03 PM PST 24 Jan 21 07:43:07 PM PST 24 486546348 ps
T862 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3841555169 Jan 21 07:41:42 PM PST 24 Jan 21 07:42:25 PM PST 24 8750157964 ps
T863 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1283596592 Jan 21 07:41:59 PM PST 24 Jan 21 07:42:39 PM PST 24 2157265326 ps
T70 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1177087795 Jan 21 07:37:09 PM PST 24 Jan 21 07:37:50 PM PST 24 24823830487 ps
T864 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1803176816 Jan 21 07:42:48 PM PST 24 Jan 21 07:42:57 PM PST 24 583915630 ps
T865 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3768107046 Jan 21 07:42:10 PM PST 24 Jan 21 07:42:40 PM PST 24 4527515289 ps
T866 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.631408994 Jan 21 07:42:36 PM PST 24 Jan 21 07:42:49 PM PST 24 373048254 ps
T867 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.531228523 Jan 21 07:42:30 PM PST 24 Jan 21 07:42:46 PM PST 24 764247394 ps
T868 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2765886338 Jan 21 07:43:02 PM PST 24 Jan 21 07:43:07 PM PST 24 374975912 ps
T869 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2245318740 Jan 21 07:37:11 PM PST 24 Jan 21 07:37:27 PM PST 24 4283178139 ps
T870 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3649167582 Jan 21 07:42:36 PM PST 24 Jan 21 07:42:49 PM PST 24 405787854 ps
T871 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3162396558 Jan 21 07:42:10 PM PST 24 Jan 21 07:42:59 PM PST 24 8518178273 ps
T872 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.636714347 Jan 21 07:41:54 PM PST 24 Jan 21 07:42:27 PM PST 24 741434411 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2629247883 Jan 21 07:36:53 PM PST 24 Jan 21 07:37:22 PM PST 24 1386913273 ps
T874 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2995003370 Jan 21 07:41:56 PM PST 24 Jan 21 07:42:29 PM PST 24 587310142 ps
T875 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1122653148 Jan 21 07:36:57 PM PST 24 Jan 21 07:37:27 PM PST 24 1847716235 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1648659710 Jan 21 07:36:53 PM PST 24 Jan 21 07:37:30 PM PST 24 7765629884 ps
T877 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.473667893 Jan 21 07:42:57 PM PST 24 Jan 21 07:43:09 PM PST 24 3936612738 ps
T878 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.672385553 Jan 21 07:42:32 PM PST 24 Jan 21 07:42:47 PM PST 24 505052229 ps
T879 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3326841663 Jan 21 07:41:57 PM PST 24 Jan 21 07:42:29 PM PST 24 360712966 ps
T880 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2991112623 Jan 21 07:41:51 PM PST 24 Jan 21 07:42:24 PM PST 24 395718382 ps
T881 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2066602654 Jan 21 07:42:54 PM PST 24 Jan 21 07:43:02 PM PST 24 381313850 ps
T882 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.606268487 Jan 21 07:43:06 PM PST 24 Jan 21 07:43:11 PM PST 24 351694325 ps
T71 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.357664700 Jan 21 07:42:30 PM PST 24 Jan 21 07:42:45 PM PST 24 385794561 ps
T883 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2275663791 Jan 21 07:43:07 PM PST 24 Jan 21 07:43:13 PM PST 24 482699755 ps
T884 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3335835909 Jan 21 07:43:06 PM PST 24 Jan 21 07:43:11 PM PST 24 421856700 ps
T885 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1247198274 Jan 21 07:36:58 PM PST 24 Jan 21 07:37:23 PM PST 24 854584421 ps
T886 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2769669667 Jan 21 07:36:29 PM PST 24 Jan 21 07:37:13 PM PST 24 576827377 ps
T887 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3403939476 Jan 21 07:41:59 PM PST 24 Jan 21 07:42:31 PM PST 24 463845273 ps
T888 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4235853997 Jan 21 07:42:11 PM PST 24 Jan 21 07:42:38 PM PST 24 528398431 ps
T72 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.984777211 Jan 21 07:42:50 PM PST 24 Jan 21 07:43:00 PM PST 24 406921514 ps
T889 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3411784920 Jan 21 07:43:01 PM PST 24 Jan 21 07:43:07 PM PST 24 475796186 ps
T890 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3343610300 Jan 21 08:37:03 PM PST 24 Jan 21 08:37:07 PM PST 24 324670560 ps
T891 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2241757604 Jan 21 07:42:30 PM PST 24 Jan 21 07:42:45 PM PST 24 429339747 ps
T892 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2745911050 Jan 21 07:36:21 PM PST 24 Jan 21 07:37:54 PM PST 24 51699560282 ps
T893 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2353629227 Jan 21 07:41:39 PM PST 24 Jan 21 07:42:17 PM PST 24 592096597 ps
T73 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4069003813 Jan 21 07:36:56 PM PST 24 Jan 21 07:38:29 PM PST 24 16653888576 ps
T74 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3079416253 Jan 21 07:42:12 PM PST 24 Jan 21 07:42:39 PM PST 24 330313453 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1473397340 Jan 21 07:36:56 PM PST 24 Jan 21 07:37:24 PM PST 24 4397737166 ps
T895 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.149073786 Jan 21 07:42:48 PM PST 24 Jan 21 07:42:58 PM PST 24 568781443 ps
T896 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3679480110 Jan 21 07:41:49 PM PST 24 Jan 21 07:42:44 PM PST 24 8361021004 ps
T897 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4269498278 Jan 21 07:42:08 PM PST 24 Jan 21 07:42:39 PM PST 24 763275060 ps
T898 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3511173732 Jan 21 07:41:48 PM PST 24 Jan 21 07:42:21 PM PST 24 430548491 ps
T899 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1931183523 Jan 21 07:41:39 PM PST 24 Jan 21 07:42:17 PM PST 24 413296404 ps
T900 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3812644046 Jan 21 07:37:02 PM PST 24 Jan 21 07:37:23 PM PST 24 1232674694 ps
T901 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.312848948 Jan 21 07:43:06 PM PST 24 Jan 21 07:43:11 PM PST 24 431959728 ps
T902 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1026104721 Jan 21 07:43:06 PM PST 24 Jan 21 07:43:12 PM PST 24 516594937 ps
T903 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2133121258 Jan 21 07:42:30 PM PST 24 Jan 21 07:42:46 PM PST 24 4931760280 ps
T904 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.503778537 Jan 21 07:42:09 PM PST 24 Jan 21 07:42:39 PM PST 24 2284572629 ps
T75 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1985829192 Jan 21 07:42:31 PM PST 24 Jan 21 07:42:45 PM PST 24 424865713 ps
T905 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3442578356 Jan 21 07:37:02 PM PST 24 Jan 21 07:37:23 PM PST 24 906905888 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1286501197 Jan 21 07:36:09 PM PST 24 Jan 21 07:36:59 PM PST 24 407280807 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2010861099 Jan 21 07:37:02 PM PST 24 Jan 21 07:37:23 PM PST 24 636299446 ps
T908 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.784997976 Jan 21 07:36:50 PM PST 24 Jan 21 07:37:20 PM PST 24 551357910 ps

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3044100760
Short name T1
Test name
Test status
Simulation time 3018915048 ps
CPU time 4.13 seconds
Started Jan 21 08:29:44 PM PST 24
Finished Jan 21 08:29:49 PM PST 24
Peak memory 200956 kb
Host smart-eb4f1d45-1572-4699-b917-296c93a34f9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044100760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3044100760
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4041047296
Short name T10
Test name
Test status
Simulation time 334118863197 ps
CPU time 95.56 seconds
Started Jan 21 04:00:52 PM PST 24
Finished Jan 21 04:02:29 PM PST 24
Peak memory 201228 kb
Host smart-97a2289c-8f0c-43cf-8474-18b072222a81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041047296 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.4041047296
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.234009350
Short name T106
Test name
Test status
Simulation time 491960867121 ps
CPU time 1071.89 seconds
Started Jan 21 03:57:45 PM PST 24
Finished Jan 21 04:15:37 PM PST 24
Peak memory 201200 kb
Host smart-9470dd91-3f19-4ca0-9736-0d56d85605dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234009350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.234009350
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2653634478
Short name T124
Test name
Test status
Simulation time 942828455214 ps
CPU time 552.08 seconds
Started Jan 21 03:50:29 PM PST 24
Finished Jan 21 03:59:43 PM PST 24
Peak memory 209760 kb
Host smart-fd1f05e4-7e85-4dd9-a012-65143f9d55e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653634478 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2653634478
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2120300136
Short name T19
Test name
Test status
Simulation time 238975428385 ps
CPU time 412.74 seconds
Started Jan 21 03:51:56 PM PST 24
Finished Jan 21 03:58:49 PM PST 24
Peak memory 211172 kb
Host smart-d7450eff-8d82-4df9-9632-7c8043fcccc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120300136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2120300136
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1073213289
Short name T89
Test name
Test status
Simulation time 500605077533 ps
CPU time 260.68 seconds
Started Jan 21 03:51:08 PM PST 24
Finished Jan 21 03:55:31 PM PST 24
Peak memory 201164 kb
Host smart-0b241217-3415-49f9-9e24-284243620b09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073213289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1073213289
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2615830595
Short name T347
Test name
Test status
Simulation time 441239450 ps
CPU time 1.76 seconds
Started Jan 21 07:43:07 PM PST 24
Finished Jan 21 07:43:13 PM PST 24
Peak memory 200724 kb
Host smart-0013cb95-32fe-436a-ba5c-5afbd59b41a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615830595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2615830595
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4024637967
Short name T6
Test name
Test status
Simulation time 4512140437 ps
CPU time 4.01 seconds
Started Jan 21 07:42:32 PM PST 24
Finished Jan 21 07:42:49 PM PST 24
Peak memory 200960 kb
Host smart-f75948e1-acb6-46ea-8dcd-e601e0bbc3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024637967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4024637967
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2306364155
Short name T108
Test name
Test status
Simulation time 480671860542 ps
CPU time 578.09 seconds
Started Jan 21 03:53:02 PM PST 24
Finished Jan 21 04:02:44 PM PST 24
Peak memory 201288 kb
Host smart-3fb5cb66-dba4-4447-96b1-1dd0093f1abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306364155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2306364155
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3350615223
Short name T169
Test name
Test status
Simulation time 255756909404 ps
CPU time 56.93 seconds
Started Jan 21 03:51:09 PM PST 24
Finished Jan 21 03:52:08 PM PST 24
Peak memory 201312 kb
Host smart-635540d9-bc2c-4e68-80d1-0351ef28fd59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350615223 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3350615223
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3835164120
Short name T105
Test name
Test status
Simulation time 489004302081 ps
CPU time 1149.85 seconds
Started Jan 21 03:56:29 PM PST 24
Finished Jan 21 04:15:40 PM PST 24
Peak memory 201244 kb
Host smart-117d523c-311e-43ba-a995-c858aa4bfd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835164120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3835164120
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3721679673
Short name T103
Test name
Test status
Simulation time 1103443798521 ps
CPU time 193.02 seconds
Started Jan 21 03:52:41 PM PST 24
Finished Jan 21 03:55:55 PM PST 24
Peak memory 209516 kb
Host smart-071d8e22-af57-4095-a124-86a4948b4022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721679673 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3721679673
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2375659404
Short name T24
Test name
Test status
Simulation time 649830708 ps
CPU time 2 seconds
Started Jan 21 08:57:52 PM PST 24
Finished Jan 21 08:58:19 PM PST 24
Peak memory 201000 kb
Host smart-1c0fa7ef-7e61-4d57-8dc0-8a5dba81e6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375659404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2375659404
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2983707853
Short name T113
Test name
Test status
Simulation time 439128403300 ps
CPU time 332.01 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:56:40 PM PST 24
Peak memory 209332 kb
Host smart-49e0e06c-88be-4281-820c-3bcdc3bc2aa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983707853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2983707853
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2061466000
Short name T110
Test name
Test status
Simulation time 456720370379 ps
CPU time 180.85 seconds
Started Jan 21 04:49:47 PM PST 24
Finished Jan 21 04:52:55 PM PST 24
Peak memory 216584 kb
Host smart-c7da5b39-24d5-4d45-9109-0636548e4c4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061466000 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2061466000
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3730750339
Short name T99
Test name
Test status
Simulation time 341902133781 ps
CPU time 215.01 seconds
Started Jan 21 03:59:27 PM PST 24
Finished Jan 21 04:03:03 PM PST 24
Peak memory 201228 kb
Host smart-31288674-0478-4833-a337-9687fb2bff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730750339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3730750339
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2606510483
Short name T210
Test name
Test status
Simulation time 487858541779 ps
CPU time 284.71 seconds
Started Jan 21 03:59:30 PM PST 24
Finished Jan 21 04:04:16 PM PST 24
Peak memory 201200 kb
Host smart-0f0acccd-f84c-437f-bdaf-a70fe9d463cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606510483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2606510483
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.4025747510
Short name T219
Test name
Test status
Simulation time 164986883766 ps
CPU time 366.54 seconds
Started Jan 21 03:53:46 PM PST 24
Finished Jan 21 03:59:54 PM PST 24
Peak memory 201200 kb
Host smart-484b3059-4002-4109-aa26-b48fe5643505
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025747510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.4025747510
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3782027246
Short name T5
Test name
Test status
Simulation time 802060440 ps
CPU time 2.7 seconds
Started Jan 21 07:37:02 PM PST 24
Finished Jan 21 07:37:24 PM PST 24
Peak memory 200940 kb
Host smart-3bca23b3-8706-4a7f-8cbe-d08de5301749
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782027246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3782027246
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2862129614
Short name T227
Test name
Test status
Simulation time 501088220688 ps
CPU time 1161.01 seconds
Started Jan 21 03:50:21 PM PST 24
Finished Jan 21 04:09:43 PM PST 24
Peak memory 201168 kb
Host smart-e704f32c-99e3-4cca-b7cf-42bab95da057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862129614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2862129614
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2513607982
Short name T170
Test name
Test status
Simulation time 493051987936 ps
CPU time 1017.33 seconds
Started Jan 21 03:57:31 PM PST 24
Finished Jan 21 04:14:30 PM PST 24
Peak memory 201180 kb
Host smart-a79748df-ba5d-499b-97b7-fcfc1e1d18a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513607982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2513607982
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3126022705
Short name T142
Test name
Test status
Simulation time 489441116480 ps
CPU time 1124.51 seconds
Started Jan 21 03:56:11 PM PST 24
Finished Jan 21 04:14:59 PM PST 24
Peak memory 201260 kb
Host smart-2e150b35-183b-43a9-9e66-0eaeef49b03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126022705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3126022705
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3994188441
Short name T265
Test name
Test status
Simulation time 494552779987 ps
CPU time 203.32 seconds
Started Jan 21 04:07:26 PM PST 24
Finished Jan 21 04:10:51 PM PST 24
Peak memory 201144 kb
Host smart-a696ba2d-648d-4b2f-b6a2-d5ca4d3d2d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994188441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3994188441
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2126875425
Short name T39
Test name
Test status
Simulation time 7976993156 ps
CPU time 17.9 seconds
Started Jan 21 03:50:22 PM PST 24
Finished Jan 21 03:50:41 PM PST 24
Peak memory 217316 kb
Host smart-ab50f2d7-03ce-483e-b2a2-82a82f5d62f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126875425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2126875425
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2715719946
Short name T185
Test name
Test status
Simulation time 369620126250 ps
CPU time 222.24 seconds
Started Jan 21 06:26:27 PM PST 24
Finished Jan 21 06:30:10 PM PST 24
Peak memory 217888 kb
Host smart-6dc578a4-3e87-4f21-958f-029e188d4fe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715719946 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2715719946
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3834832225
Short name T244
Test name
Test status
Simulation time 462395427730 ps
CPU time 1445.67 seconds
Started Jan 21 03:57:12 PM PST 24
Finished Jan 21 04:21:19 PM PST 24
Peak memory 209684 kb
Host smart-1eab1491-0206-4cbb-8d4c-6f653d9064dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834832225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3834832225
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.673060621
Short name T151
Test name
Test status
Simulation time 326866957148 ps
CPU time 49.09 seconds
Started Jan 21 03:55:04 PM PST 24
Finished Jan 21 03:55:54 PM PST 24
Peak memory 201204 kb
Host smart-4b7be76e-cc7a-4ccc-836b-aafac7881e3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673060621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.673060621
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1623643009
Short name T207
Test name
Test status
Simulation time 323439847241 ps
CPU time 742.16 seconds
Started Jan 21 04:24:55 PM PST 24
Finished Jan 21 04:37:18 PM PST 24
Peak memory 201236 kb
Host smart-4f4a341e-ac70-48f9-81e5-bf2efd4e5329
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623643009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1623643009
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.467353442
Short name T236
Test name
Test status
Simulation time 503215106532 ps
CPU time 1240 seconds
Started Jan 21 03:52:02 PM PST 24
Finished Jan 21 04:12:44 PM PST 24
Peak memory 201256 kb
Host smart-294d4d0c-257d-4360-bb64-d73ca22d6567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467353442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.467353442
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1633078254
Short name T80
Test name
Test status
Simulation time 484555672 ps
CPU time 3.21 seconds
Started Jan 21 07:37:02 PM PST 24
Finished Jan 21 07:37:25 PM PST 24
Peak memory 200988 kb
Host smart-5064fc1c-8aca-412d-94d5-e00c3e446a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633078254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1633078254
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1132467304
Short name T112
Test name
Test status
Simulation time 312995861557 ps
CPU time 128.63 seconds
Started Jan 21 03:55:13 PM PST 24
Finished Jan 21 03:57:25 PM PST 24
Peak memory 211432 kb
Host smart-4f0ce95e-4e06-49b0-9f5b-cf3eea0d3915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132467304 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1132467304
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3368610321
Short name T202
Test name
Test status
Simulation time 495801136063 ps
CPU time 384.77 seconds
Started Jan 21 03:57:01 PM PST 24
Finished Jan 21 04:03:27 PM PST 24
Peak memory 201160 kb
Host smart-bcf5b70c-f8af-4814-991c-8c0d1cadb771
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368610321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3368610321
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.978335748
Short name T233
Test name
Test status
Simulation time 337237165500 ps
CPU time 810.52 seconds
Started Jan 21 03:52:18 PM PST 24
Finished Jan 21 04:05:52 PM PST 24
Peak memory 201260 kb
Host smart-536761fa-a498-4de1-b7e2-ed2d338e2065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978335748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.978335748
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.50622724
Short name T229
Test name
Test status
Simulation time 318011107190 ps
CPU time 376.35 seconds
Started Jan 21 03:59:02 PM PST 24
Finished Jan 21 04:05:24 PM PST 24
Peak memory 201196 kb
Host smart-60ed674f-b063-43d6-8b30-e265eed3f948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50622724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.50622724
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.673163031
Short name T154
Test name
Test status
Simulation time 495619080014 ps
CPU time 346.62 seconds
Started Jan 21 04:28:16 PM PST 24
Finished Jan 21 04:34:03 PM PST 24
Peak memory 201236 kb
Host smart-2e19c08d-40ea-4202-b81c-25511bde1dde
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673163031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.673163031
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2547792957
Short name T274
Test name
Test status
Simulation time 495534322634 ps
CPU time 1131.61 seconds
Started Jan 21 03:58:28 PM PST 24
Finished Jan 21 04:17:21 PM PST 24
Peak memory 201296 kb
Host smart-6d4694ed-571a-4348-851d-3fad30ec878b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547792957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2547792957
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2378159313
Short name T135
Test name
Test status
Simulation time 332474627632 ps
CPU time 194.58 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:54:24 PM PST 24
Peak memory 201208 kb
Host smart-6947dffc-840b-444f-9311-68d343fda275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378159313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2378159313
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2294247404
Short name T302
Test name
Test status
Simulation time 158449187353 ps
CPU time 250.55 seconds
Started Jan 21 03:56:49 PM PST 24
Finished Jan 21 04:01:01 PM PST 24
Peak memory 201248 kb
Host smart-855dc1ec-e173-4d15-a180-393ff668d4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294247404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2294247404
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.786825070
Short name T235
Test name
Test status
Simulation time 665445186463 ps
CPU time 1384.85 seconds
Started Jan 21 04:01:09 PM PST 24
Finished Jan 21 04:24:16 PM PST 24
Peak memory 201100 kb
Host smart-b28a1e64-cf36-4608-862e-a3d559082722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786825070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
786825070
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.304248766
Short name T212
Test name
Test status
Simulation time 162298919023 ps
CPU time 188.24 seconds
Started Jan 21 03:52:46 PM PST 24
Finished Jan 21 03:55:55 PM PST 24
Peak memory 201208 kb
Host smart-24ae2e65-5382-422f-a921-3e6c0b25cf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304248766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.304248766
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1511121179
Short name T119
Test name
Test status
Simulation time 335129165280 ps
CPU time 809.59 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 04:04:39 PM PST 24
Peak memory 201164 kb
Host smart-038889a0-ad80-49be-9689-c8ba39f13216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511121179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1511121179
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1336203484
Short name T134
Test name
Test status
Simulation time 162215608367 ps
CPU time 349.48 seconds
Started Jan 21 03:51:58 PM PST 24
Finished Jan 21 03:57:48 PM PST 24
Peak memory 201124 kb
Host smart-b5202a27-7959-45f7-8a51-0dddcee0a0c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336203484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1336203484
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.4000580038
Short name T314
Test name
Test status
Simulation time 500857167639 ps
CPU time 286.86 seconds
Started Jan 21 03:51:31 PM PST 24
Finished Jan 21 03:56:19 PM PST 24
Peak memory 201108 kb
Host smart-8d8bf259-0784-41c0-ab24-2c724e0db79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000580038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4000580038
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2377088681
Short name T217
Test name
Test status
Simulation time 387221126701 ps
CPU time 202.99 seconds
Started Jan 21 03:51:25 PM PST 24
Finished Jan 21 03:54:48 PM PST 24
Peak memory 201076 kb
Host smart-528859bf-6432-4e8a-b930-eddee7229fb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377088681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2377088681
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1214264717
Short name T251
Test name
Test status
Simulation time 351259685145 ps
CPU time 559.4 seconds
Started Jan 21 03:59:55 PM PST 24
Finished Jan 21 04:09:15 PM PST 24
Peak memory 209812 kb
Host smart-dc452b3b-6679-4da2-8b47-a40f6be27f5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214264717 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1214264717
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1274725956
Short name T266
Test name
Test status
Simulation time 327747286507 ps
CPU time 673.46 seconds
Started Jan 21 03:50:13 PM PST 24
Finished Jan 21 04:01:28 PM PST 24
Peak memory 201176 kb
Host smart-cf9bfdcb-d710-409f-987b-beebccfb7bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274725956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1274725956
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.4225983178
Short name T258
Test name
Test status
Simulation time 515444334508 ps
CPU time 282.12 seconds
Started Jan 21 03:58:18 PM PST 24
Finished Jan 21 04:03:06 PM PST 24
Peak memory 201196 kb
Host smart-dccdbaf1-d277-41d7-b028-de6164ec106b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225983178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.4225983178
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1733429320
Short name T281
Test name
Test status
Simulation time 492984219797 ps
CPU time 527.65 seconds
Started Jan 21 03:50:54 PM PST 24
Finished Jan 21 03:59:44 PM PST 24
Peak memory 201188 kb
Host smart-5deef554-e80a-470f-baa6-77646954fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733429320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1733429320
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2470422468
Short name T324
Test name
Test status
Simulation time 123659786173 ps
CPU time 142.42 seconds
Started Jan 21 03:50:14 PM PST 24
Finished Jan 21 03:52:39 PM PST 24
Peak memory 201228 kb
Host smart-e441be4d-3160-4a2d-8e7a-be2385546c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470422468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2470422468
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3355619241
Short name T301
Test name
Test status
Simulation time 162717383415 ps
CPU time 361.26 seconds
Started Jan 21 04:11:30 PM PST 24
Finished Jan 21 04:17:32 PM PST 24
Peak memory 201216 kb
Host smart-47b66a2d-747e-47db-9f7a-849ef8a3a2a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355619241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3355619241
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3668923183
Short name T228
Test name
Test status
Simulation time 323377787453 ps
CPU time 192.17 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:54:22 PM PST 24
Peak memory 201156 kb
Host smart-c7d5fc7d-adf9-496a-b1e8-3c218e48a3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668923183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3668923183
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.861294123
Short name T295
Test name
Test status
Simulation time 162155733816 ps
CPU time 350.71 seconds
Started Jan 21 03:52:28 PM PST 24
Finished Jan 21 03:58:20 PM PST 24
Peak memory 201256 kb
Host smart-eb7e360c-52dd-44a6-b50f-a8b6f4ff2c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861294123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.861294123
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2168971318
Short name T297
Test name
Test status
Simulation time 162831505892 ps
CPU time 368.4 seconds
Started Jan 21 03:57:37 PM PST 24
Finished Jan 21 04:03:46 PM PST 24
Peak memory 201272 kb
Host smart-f7e77869-a8da-4024-b4b9-51c20749ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168971318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2168971318
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.837677884
Short name T47
Test name
Test status
Simulation time 130191741915 ps
CPU time 472.26 seconds
Started Jan 21 04:01:08 PM PST 24
Finished Jan 21 04:09:03 PM PST 24
Peak memory 201384 kb
Host smart-eecbb37a-46f7-4544-a265-5d20127f68e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837677884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.837677884
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3713336650
Short name T409
Test name
Test status
Simulation time 370077088 ps
CPU time 0.75 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:51:09 PM PST 24
Peak memory 200932 kb
Host smart-f38dd1db-e939-4bc0-9b90-fdaed5f35aaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713336650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3713336650
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.188796407
Short name T354
Test name
Test status
Simulation time 370833954 ps
CPU time 1.19 seconds
Started Jan 21 07:42:30 PM PST 24
Finished Jan 21 07:42:45 PM PST 24
Peak memory 200896 kb
Host smart-9431e200-69fe-4c7f-ae5f-a22450d560a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188796407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.188796407
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3672388368
Short name T197
Test name
Test status
Simulation time 195534678836 ps
CPU time 1090.44 seconds
Started Jan 21 03:51:04 PM PST 24
Finished Jan 21 04:09:19 PM PST 24
Peak memory 201428 kb
Host smart-94f2faa5-fd1e-4dcd-9e57-1fd1755c6e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672388368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3672388368
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2867569290
Short name T285
Test name
Test status
Simulation time 325443540447 ps
CPU time 117.47 seconds
Started Jan 21 03:52:27 PM PST 24
Finished Jan 21 03:54:25 PM PST 24
Peak memory 201188 kb
Host smart-63e851ae-7054-49cf-8017-7f52a25fd656
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867569290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2867569290
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2678857904
Short name T176
Test name
Test status
Simulation time 480992957982 ps
CPU time 289.48 seconds
Started Jan 21 03:53:59 PM PST 24
Finished Jan 21 03:58:50 PM PST 24
Peak memory 201208 kb
Host smart-4b5804df-4be0-4c47-9ca2-646e6b11c0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678857904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2678857904
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2211732465
Short name T111
Test name
Test status
Simulation time 497652294297 ps
CPU time 1258.53 seconds
Started Jan 21 04:56:45 PM PST 24
Finished Jan 21 05:17:44 PM PST 24
Peak memory 201156 kb
Host smart-7eedbd30-5658-4d14-a44a-ecb7643b02e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211732465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2211732465
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3807353809
Short name T140
Test name
Test status
Simulation time 491894608416 ps
CPU time 109.02 seconds
Started Jan 21 03:50:25 PM PST 24
Finished Jan 21 03:52:15 PM PST 24
Peak memory 201192 kb
Host smart-581a778a-7dca-4182-ba7c-484f1aa45a60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807353809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3807353809
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1002647475
Short name T304
Test name
Test status
Simulation time 166825110305 ps
CPU time 364.02 seconds
Started Jan 21 03:56:09 PM PST 24
Finished Jan 21 04:02:17 PM PST 24
Peak memory 201264 kb
Host smart-a1a66ea6-cd02-4061-8657-c6d203979664
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002647475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1002647475
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.110575227
Short name T125
Test name
Test status
Simulation time 496650603558 ps
CPU time 293.88 seconds
Started Jan 21 03:56:07 PM PST 24
Finished Jan 21 04:01:07 PM PST 24
Peak memory 201244 kb
Host smart-b06916f4-81a4-47d5-a232-33cc34b45828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110575227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.110575227
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2412370980
Short name T262
Test name
Test status
Simulation time 422189640987 ps
CPU time 239.7 seconds
Started Jan 21 03:57:32 PM PST 24
Finished Jan 21 04:01:33 PM PST 24
Peak memory 209732 kb
Host smart-34e2c1df-9679-4c84-8fac-12ae61aeb4ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412370980 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2412370980
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2633903066
Short name T256
Test name
Test status
Simulation time 322548043463 ps
CPU time 158.08 seconds
Started Jan 21 03:58:16 PM PST 24
Finished Jan 21 04:00:58 PM PST 24
Peak memory 201180 kb
Host smart-df6562de-843e-41b4-8786-dbfc12b54be9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633903066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2633903066
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.54314468
Short name T255
Test name
Test status
Simulation time 398776553544 ps
CPU time 55.21 seconds
Started Jan 21 03:58:58 PM PST 24
Finished Jan 21 03:59:55 PM PST 24
Peak memory 201292 kb
Host smart-1159d9af-52d9-4762-bf73-33f2e70dcc36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54314468 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.54314468
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.597446563
Short name T284
Test name
Test status
Simulation time 335682949155 ps
CPU time 261.64 seconds
Started Jan 21 03:59:36 PM PST 24
Finished Jan 21 04:03:59 PM PST 24
Peak memory 201176 kb
Host smart-7bbb89c6-d086-40e5-8c63-e54e785c2094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597446563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.597446563
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.55975432
Short name T53
Test name
Test status
Simulation time 319756864345 ps
CPU time 368.66 seconds
Started Jan 21 03:50:28 PM PST 24
Finished Jan 21 03:56:38 PM PST 24
Peak memory 201256 kb
Host smart-de4b341c-58c1-4792-a397-eb5505df1460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55975432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.55975432
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3536200601
Short name T62
Test name
Test status
Simulation time 8145024609 ps
CPU time 7.5 seconds
Started Jan 21 07:42:46 PM PST 24
Finished Jan 21 07:43:01 PM PST 24
Peak memory 201064 kb
Host smart-099bdfad-8cc3-485f-8dec-8ac508a92ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536200601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3536200601
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2829948852
Short name T232
Test name
Test status
Simulation time 327012118786 ps
CPU time 482.85 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:59:11 PM PST 24
Peak memory 201188 kb
Host smart-2533beec-ed7c-439c-b8bd-3394b23e9bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829948852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2829948852
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2214883034
Short name T322
Test name
Test status
Simulation time 321855825372 ps
CPU time 666.34 seconds
Started Jan 21 03:50:20 PM PST 24
Finished Jan 21 04:01:29 PM PST 24
Peak memory 201168 kb
Host smart-0e7b6358-a17d-4f49-b4ef-df777737370b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214883034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2214883034
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1199045688
Short name T257
Test name
Test status
Simulation time 490861252015 ps
CPU time 278.74 seconds
Started Jan 21 03:54:50 PM PST 24
Finished Jan 21 03:59:29 PM PST 24
Peak memory 201124 kb
Host smart-9ac20d0b-ad72-4a65-9d44-2dd17476fd80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199045688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1199045688
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2947438047
Short name T253
Test name
Test status
Simulation time 491831703794 ps
CPU time 457.92 seconds
Started Jan 21 03:59:09 PM PST 24
Finished Jan 21 04:06:50 PM PST 24
Peak memory 201192 kb
Host smart-ff2ff032-65d9-4973-9e95-12c94e484b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947438047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2947438047
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2133925321
Short name T319
Test name
Test status
Simulation time 500021892900 ps
CPU time 1188.91 seconds
Started Jan 21 03:59:26 PM PST 24
Finished Jan 21 04:19:16 PM PST 24
Peak memory 201244 kb
Host smart-ed02b09d-c754-4e15-bc20-b3c7d8ebab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133925321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2133925321
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3372180565
Short name T230
Test name
Test status
Simulation time 492030278644 ps
CPU time 109.57 seconds
Started Jan 21 03:50:39 PM PST 24
Finished Jan 21 03:52:29 PM PST 24
Peak memory 201268 kb
Host smart-616aca7c-dff2-49a2-ada6-2e8f4effe8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372180565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3372180565
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1207548136
Short name T320
Test name
Test status
Simulation time 486443225857 ps
CPU time 1150.92 seconds
Started Jan 21 04:10:39 PM PST 24
Finished Jan 21 04:29:51 PM PST 24
Peak memory 201412 kb
Host smart-e89cea54-27ed-460c-873a-ddefacfa8dcb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207548136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1207548136
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1908320786
Short name T241
Test name
Test status
Simulation time 169960338344 ps
CPU time 103.42 seconds
Started Jan 21 03:50:28 PM PST 24
Finished Jan 21 03:52:12 PM PST 24
Peak memory 201044 kb
Host smart-3792dce7-4158-444f-89df-5bcc6bc9256d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908320786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1908320786
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2735074755
Short name T20
Test name
Test status
Simulation time 330201684553 ps
CPU time 222.4 seconds
Started Jan 21 03:50:59 PM PST 24
Finished Jan 21 03:54:47 PM PST 24
Peak memory 200780 kb
Host smart-d1c85dbb-0c0c-4277-bbd3-dbb1da55fdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735074755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2735074755
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.938711643
Short name T340
Test name
Test status
Simulation time 126499343447 ps
CPU time 443.62 seconds
Started Jan 21 03:51:09 PM PST 24
Finished Jan 21 03:58:35 PM PST 24
Peak memory 201436 kb
Host smart-209a34e7-9182-459e-995c-ff4d60e46a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938711643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.938711643
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1151053767
Short name T195
Test name
Test status
Simulation time 107126407802 ps
CPU time 331.02 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:56:41 PM PST 24
Peak memory 201352 kb
Host smart-8aa5a578-222d-421b-9a6d-0b3bae7f5f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151053767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1151053767
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.699161948
Short name T199
Test name
Test status
Simulation time 78080148664 ps
CPU time 163.84 seconds
Started Jan 21 03:51:21 PM PST 24
Finished Jan 21 03:54:06 PM PST 24
Peak memory 209808 kb
Host smart-0394c8c4-1c1f-4cbd-a666-0ade1897d07d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699161948 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.699161948
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.212223274
Short name T188
Test name
Test status
Simulation time 74295349425 ps
CPU time 264.07 seconds
Started Jan 21 04:06:49 PM PST 24
Finished Jan 21 04:11:22 PM PST 24
Peak memory 201392 kb
Host smart-8f234f50-d44e-49b2-8909-08c2b5d8dff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212223274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.212223274
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3386977991
Short name T279
Test name
Test status
Simulation time 329205425236 ps
CPU time 783.71 seconds
Started Jan 21 03:52:46 PM PST 24
Finished Jan 21 04:05:50 PM PST 24
Peak memory 201176 kb
Host smart-5e5209e3-0e19-48ad-a3fb-304b752a253b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386977991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3386977991
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1781903722
Short name T45
Test name
Test status
Simulation time 92564394288 ps
CPU time 484.43 seconds
Started Jan 21 03:56:29 PM PST 24
Finished Jan 21 04:04:35 PM PST 24
Peak memory 201504 kb
Host smart-1644eb3b-221a-4748-b2e4-99e375066760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781903722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1781903722
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2011711991
Short name T291
Test name
Test status
Simulation time 494913446021 ps
CPU time 1266.24 seconds
Started Jan 21 03:57:25 PM PST 24
Finished Jan 21 04:18:33 PM PST 24
Peak memory 201216 kb
Host smart-2072786c-4f51-42e8-8cbc-02b2a74e36d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011711991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2011711991
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2690562401
Short name T234
Test name
Test status
Simulation time 322915943467 ps
CPU time 704.83 seconds
Started Jan 21 03:57:40 PM PST 24
Finished Jan 21 04:09:25 PM PST 24
Peak memory 201112 kb
Host smart-d56ef551-2ea8-4fbe-9970-e7476048f407
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690562401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2690562401
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2489395686
Short name T223
Test name
Test status
Simulation time 163935346238 ps
CPU time 411.19 seconds
Started Jan 21 04:53:56 PM PST 24
Finished Jan 21 05:00:48 PM PST 24
Peak memory 201164 kb
Host smart-111efa61-93e7-41ff-8a1b-5f0bc8e85c30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489395686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2489395686
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2325708586
Short name T168
Test name
Test status
Simulation time 490450795697 ps
CPU time 151.71 seconds
Started Jan 21 03:50:39 PM PST 24
Finished Jan 21 03:53:12 PM PST 24
Peak memory 201108 kb
Host smart-cc045636-c377-4f81-893e-a5e1d84939a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325708586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2325708586
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2960650276
Short name T68
Test name
Test status
Simulation time 1174948198 ps
CPU time 5.43 seconds
Started Jan 21 07:36:18 PM PST 24
Finished Jan 21 07:37:13 PM PST 24
Peak memory 200988 kb
Host smart-5943e3c6-688a-4828-a1bd-a94ec43613eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960650276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2960650276
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2745911050
Short name T892
Test name
Test status
Simulation time 51699560282 ps
CPU time 46.07 seconds
Started Jan 21 07:36:21 PM PST 24
Finished Jan 21 07:37:54 PM PST 24
Peak memory 200984 kb
Host smart-fb93eec1-a43e-440f-a1b6-d147242752b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745911050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2745911050
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2381767243
Short name T66
Test name
Test status
Simulation time 1230218371 ps
CPU time 1.44 seconds
Started Jan 21 07:36:16 PM PST 24
Finished Jan 21 07:37:06 PM PST 24
Peak memory 201060 kb
Host smart-1abca2f7-9f86-4959-982a-8f282aaf8100
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381767243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2381767243
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2769669667
Short name T886
Test name
Test status
Simulation time 576827377 ps
CPU time 2.23 seconds
Started Jan 21 07:36:29 PM PST 24
Finished Jan 21 07:37:13 PM PST 24
Peak memory 200940 kb
Host smart-b57e1987-c2d2-4324-ad7a-ea947004c880
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769669667 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2769669667
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4156624279
Short name T69
Test name
Test status
Simulation time 541815976 ps
CPU time 1.33 seconds
Started Jan 21 07:36:22 PM PST 24
Finished Jan 21 07:37:10 PM PST 24
Peak memory 200808 kb
Host smart-556aeb53-3e90-42aa-b519-376eecb1658d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156624279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4156624279
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1286501197
Short name T906
Test name
Test status
Simulation time 407280807 ps
CPU time 0.76 seconds
Started Jan 21 07:36:09 PM PST 24
Finished Jan 21 07:36:59 PM PST 24
Peak memory 200700 kb
Host smart-5abde4b6-c16c-4878-8adc-8a2d895e22f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286501197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1286501197
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3410817003
Short name T79
Test name
Test status
Simulation time 4478269474 ps
CPU time 4.62 seconds
Started Jan 21 07:36:23 PM PST 24
Finished Jan 21 07:37:13 PM PST 24
Peak memory 200976 kb
Host smart-84506d5d-d0df-487c-86f8-98d1778c76ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410817003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3410817003
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4115741658
Short name T63
Test name
Test status
Simulation time 333659891 ps
CPU time 2.44 seconds
Started Jan 21 07:36:00 PM PST 24
Finished Jan 21 07:36:53 PM PST 24
Peak memory 200948 kb
Host smart-b9c5c89f-45bc-47e2-91a7-107f099da902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115741658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4115741658
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3686290947
Short name T388
Test name
Test status
Simulation time 4247708293 ps
CPU time 4.19 seconds
Started Jan 21 07:36:10 PM PST 24
Finished Jan 21 07:37:03 PM PST 24
Peak memory 201048 kb
Host smart-893b88ff-6688-45c1-8585-237574b7dd4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686290947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3686290947
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2629247883
Short name T873
Test name
Test status
Simulation time 1386913273 ps
CPU time 3.79 seconds
Started Jan 21 07:36:53 PM PST 24
Finished Jan 21 07:37:22 PM PST 24
Peak memory 201028 kb
Host smart-19a11ae9-701c-45a4-981d-2ee81942a2ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629247883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2629247883
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4069003813
Short name T73
Test name
Test status
Simulation time 16653888576 ps
CPU time 69.67 seconds
Started Jan 21 07:36:56 PM PST 24
Finished Jan 21 07:38:29 PM PST 24
Peak memory 201068 kb
Host smart-0be3c439-996b-4f96-bf29-d6182720535b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069003813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4069003813
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3205091875
Short name T29
Test name
Test status
Simulation time 659364364 ps
CPU time 2.33 seconds
Started Jan 21 07:36:56 PM PST 24
Finished Jan 21 07:37:22 PM PST 24
Peak memory 200852 kb
Host smart-35cf5c28-333a-4513-82bd-8954d98fc948
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205091875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3205091875
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3170466021
Short name T376
Test name
Test status
Simulation time 385469076 ps
CPU time 1.8 seconds
Started Jan 21 07:36:56 PM PST 24
Finished Jan 21 07:37:22 PM PST 24
Peak memory 200912 kb
Host smart-2c9a05a3-4a9c-4abf-92ec-ca56066d586c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170466021 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3170466021
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.784997976
Short name T908
Test name
Test status
Simulation time 551357910 ps
CPU time 2.12 seconds
Started Jan 21 07:36:50 PM PST 24
Finished Jan 21 07:37:20 PM PST 24
Peak memory 200812 kb
Host smart-c619c328-2c8d-4a32-86b4-271b66aea588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784997976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.784997976
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.546488998
Short name T365
Test name
Test status
Simulation time 359836747 ps
CPU time 1.09 seconds
Started Jan 21 07:36:40 PM PST 24
Finished Jan 21 07:37:16 PM PST 24
Peak memory 200788 kb
Host smart-81778832-1ee0-4339-91cf-62e24f03281b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546488998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.546488998
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1473397340
Short name T894
Test name
Test status
Simulation time 4397737166 ps
CPU time 3.99 seconds
Started Jan 21 07:36:56 PM PST 24
Finished Jan 21 07:37:24 PM PST 24
Peak memory 201068 kb
Host smart-176dc695-e24d-40be-aa4a-debae3e484b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473397340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1473397340
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1156427317
Short name T22
Test name
Test status
Simulation time 1418900596 ps
CPU time 2.17 seconds
Started Jan 21 07:36:33 PM PST 24
Finished Jan 21 07:37:15 PM PST 24
Peak memory 201084 kb
Host smart-2a1338ea-82fa-4ce4-a21d-2bec73755bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156427317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1156427317
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2933014072
Short name T366
Test name
Test status
Simulation time 8659401805 ps
CPU time 6.93 seconds
Started Jan 21 07:36:33 PM PST 24
Finished Jan 21 07:37:20 PM PST 24
Peak memory 200980 kb
Host smart-89126c9b-8426-4f91-b335-369c1c0ec1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933014072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2933014072
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2905558279
Short name T362
Test name
Test status
Simulation time 587232419 ps
CPU time 1.24 seconds
Started Jan 21 07:41:59 PM PST 24
Finished Jan 21 07:42:31 PM PST 24
Peak memory 200880 kb
Host smart-3bf28670-fca4-4d6e-b8f4-bb190f01ac84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905558279 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2905558279
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3403939476
Short name T887
Test name
Test status
Simulation time 463845273 ps
CPU time 1.27 seconds
Started Jan 21 07:41:59 PM PST 24
Finished Jan 21 07:42:31 PM PST 24
Peak memory 200808 kb
Host smart-22e5729c-c522-4048-9d08-316caf1a9f9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403939476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3403939476
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3622188311
Short name T398
Test name
Test status
Simulation time 361796951 ps
CPU time 0.86 seconds
Started Jan 21 07:41:59 PM PST 24
Finished Jan 21 07:42:30 PM PST 24
Peak memory 200528 kb
Host smart-c301797d-006f-431a-8521-fe23b142e5f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622188311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3622188311
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1283596592
Short name T863
Test name
Test status
Simulation time 2157265326 ps
CPU time 8.15 seconds
Started Jan 21 07:41:59 PM PST 24
Finished Jan 21 07:42:39 PM PST 24
Peak memory 201116 kb
Host smart-36fe2904-430a-4015-8d92-3d2b06341ca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283596592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1283596592
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2995003370
Short name T874
Test name
Test status
Simulation time 587310142 ps
CPU time 2.06 seconds
Started Jan 21 07:41:56 PM PST 24
Finished Jan 21 07:42:29 PM PST 24
Peak memory 200992 kb
Host smart-5d83cdc4-2e59-45af-9118-879fab734791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995003370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2995003370
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3746361245
Short name T30
Test name
Test status
Simulation time 4656287273 ps
CPU time 12 seconds
Started Jan 21 07:41:56 PM PST 24
Finished Jan 21 07:42:38 PM PST 24
Peak memory 200932 kb
Host smart-0b831030-bd84-4dcf-97d4-ac68a72a2d29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746361245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3746361245
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1753234807
Short name T349
Test name
Test status
Simulation time 480229572 ps
CPU time 1.09 seconds
Started Jan 21 07:42:09 PM PST 24
Finished Jan 21 07:42:38 PM PST 24
Peak memory 200884 kb
Host smart-46eaf161-60c1-4ac9-bb66-27b662def328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753234807 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1753234807
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1009806327
Short name T386
Test name
Test status
Simulation time 630422723 ps
CPU time 1.01 seconds
Started Jan 21 07:41:56 PM PST 24
Finished Jan 21 07:42:27 PM PST 24
Peak memory 200844 kb
Host smart-9ca580a9-c205-436f-b728-2564d1785a3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009806327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1009806327
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3636914409
Short name T385
Test name
Test status
Simulation time 464418205 ps
CPU time 1.18 seconds
Started Jan 21 07:41:59 PM PST 24
Finished Jan 21 07:42:30 PM PST 24
Peak memory 200716 kb
Host smart-0d9ad399-a3ca-4f26-8cb7-46401eb3e39b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636914409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3636914409
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2558185642
Short name T405
Test name
Test status
Simulation time 1869146198 ps
CPU time 2.57 seconds
Started Jan 21 07:42:14 PM PST 24
Finished Jan 21 07:42:42 PM PST 24
Peak memory 200816 kb
Host smart-fb6a4741-7e2d-4a77-bd09-1d3a686d2ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558185642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2558185642
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2532878698
Short name T369
Test name
Test status
Simulation time 548828026 ps
CPU time 1.84 seconds
Started Jan 21 07:42:00 PM PST 24
Finished Jan 21 07:42:32 PM PST 24
Peak memory 201000 kb
Host smart-1d2da271-668b-4f79-95f5-dd39c916e789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532878698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2532878698
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.908943849
Short name T180
Test name
Test status
Simulation time 4431209911 ps
CPU time 4 seconds
Started Jan 21 07:41:57 PM PST 24
Finished Jan 21 07:42:31 PM PST 24
Peak memory 201024 kb
Host smart-6bb69959-f652-44fd-8c42-34d81d66f900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908943849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.908943849
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4235853997
Short name T888
Test name
Test status
Simulation time 528398431 ps
CPU time 1.08 seconds
Started Jan 21 07:42:11 PM PST 24
Finished Jan 21 07:42:38 PM PST 24
Peak memory 200884 kb
Host smart-1991d5e4-32a7-4b58-b646-7f0c11d9d96b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235853997 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4235853997
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3079416253
Short name T74
Test name
Test status
Simulation time 330313453 ps
CPU time 1.32 seconds
Started Jan 21 07:42:12 PM PST 24
Finished Jan 21 07:42:39 PM PST 24
Peak memory 200836 kb
Host smart-aa8f06af-c225-408d-8201-251fb54b124e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079416253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3079416253
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3111208128
Short name T363
Test name
Test status
Simulation time 354296047 ps
CPU time 0.72 seconds
Started Jan 21 07:42:15 PM PST 24
Finished Jan 21 07:42:40 PM PST 24
Peak memory 200780 kb
Host smart-88dbd4c2-a733-45e3-a93d-d106fa0977e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111208128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3111208128
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.503778537
Short name T904
Test name
Test status
Simulation time 2284572629 ps
CPU time 1.93 seconds
Started Jan 21 07:42:09 PM PST 24
Finished Jan 21 07:42:39 PM PST 24
Peak memory 200948 kb
Host smart-08912b1a-12da-4813-aab0-afe68084fe7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503778537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.503778537
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3863508991
Short name T55
Test name
Test status
Simulation time 450044890 ps
CPU time 2.39 seconds
Started Jan 21 07:42:08 PM PST 24
Finished Jan 21 07:42:39 PM PST 24
Peak memory 200992 kb
Host smart-748fe962-f4e0-49ce-ab36-3fcfde963b56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863508991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3863508991
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3162396558
Short name T871
Test name
Test status
Simulation time 8518178273 ps
CPU time 21.85 seconds
Started Jan 21 07:42:10 PM PST 24
Finished Jan 21 07:42:59 PM PST 24
Peak memory 200984 kb
Host smart-3a24f7f0-e976-4f18-9825-40edd2c3c8e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162396558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3162396558
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.672385553
Short name T878
Test name
Test status
Simulation time 505052229 ps
CPU time 1.12 seconds
Started Jan 21 07:42:32 PM PST 24
Finished Jan 21 07:42:47 PM PST 24
Peak memory 200824 kb
Host smart-0f5f2eec-4d7e-4613-ad23-933ea2c552c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672385553 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.672385553
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1985829192
Short name T75
Test name
Test status
Simulation time 424865713 ps
CPU time 0.93 seconds
Started Jan 21 07:42:31 PM PST 24
Finished Jan 21 07:42:45 PM PST 24
Peak memory 200820 kb
Host smart-bfd8be89-8fb6-4a00-bea3-66a75745c3f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985829192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1985829192
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2223071870
Short name T32
Test name
Test status
Simulation time 442383251 ps
CPU time 0.7 seconds
Started Jan 21 07:42:35 PM PST 24
Finished Jan 21 07:42:47 PM PST 24
Peak memory 200764 kb
Host smart-b99d697e-e4dd-47e5-a764-9adb8383eeb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223071870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2223071870
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2133121258
Short name T903
Test name
Test status
Simulation time 4931760280 ps
CPU time 1.99 seconds
Started Jan 21 07:42:30 PM PST 24
Finished Jan 21 07:42:46 PM PST 24
Peak memory 201008 kb
Host smart-2f8fe930-8007-47e5-8845-c3f84abb2dfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133121258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2133121258
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4269498278
Short name T897
Test name
Test status
Simulation time 763275060 ps
CPU time 2.48 seconds
Started Jan 21 07:42:08 PM PST 24
Finished Jan 21 07:42:39 PM PST 24
Peak memory 209288 kb
Host smart-f2286f7a-b7dd-4044-a9fd-13b39238a45d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269498278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.4269498278
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3768107046
Short name T865
Test name
Test status
Simulation time 4527515289 ps
CPU time 2.69 seconds
Started Jan 21 07:42:10 PM PST 24
Finished Jan 21 07:42:40 PM PST 24
Peak memory 201048 kb
Host smart-d0d518e3-130e-4e4f-aab0-59bfa8cf8ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768107046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3768107046
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3649167582
Short name T870
Test name
Test status
Simulation time 405787854 ps
CPU time 1.88 seconds
Started Jan 21 07:42:36 PM PST 24
Finished Jan 21 07:42:49 PM PST 24
Peak memory 200900 kb
Host smart-2545e0c9-aeb5-468c-87e2-0f67fca1737b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649167582 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3649167582
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.357664700
Short name T71
Test name
Test status
Simulation time 385794561 ps
CPU time 0.97 seconds
Started Jan 21 07:42:30 PM PST 24
Finished Jan 21 07:42:45 PM PST 24
Peak memory 200876 kb
Host smart-c05c34af-2926-4c37-ab89-8f85dd153345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357664700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.357664700
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1591371666
Short name T77
Test name
Test status
Simulation time 2303161851 ps
CPU time 4.62 seconds
Started Jan 21 07:42:37 PM PST 24
Finished Jan 21 07:42:52 PM PST 24
Peak memory 200956 kb
Host smart-a3f56809-cd8c-4fd1-9302-92c6e2580a72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591371666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1591371666
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1570413217
Short name T57
Test name
Test status
Simulation time 757134196 ps
CPU time 1.73 seconds
Started Jan 21 07:42:30 PM PST 24
Finished Jan 21 07:42:46 PM PST 24
Peak memory 201072 kb
Host smart-bd057485-8888-40c0-a6b1-9f70422891ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570413217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1570413217
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.631408994
Short name T866
Test name
Test status
Simulation time 373048254 ps
CPU time 1.75 seconds
Started Jan 21 07:42:36 PM PST 24
Finished Jan 21 07:42:49 PM PST 24
Peak memory 200896 kb
Host smart-307bf7af-cb81-4e1e-a15e-8f569901ee22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631408994 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.631408994
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.257007540
Short name T374
Test name
Test status
Simulation time 570485987 ps
CPU time 1.19 seconds
Started Jan 21 07:42:30 PM PST 24
Finished Jan 21 07:42:45 PM PST 24
Peak memory 200812 kb
Host smart-13eabca0-b603-42f4-adcd-d1cf6ceb40a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257007540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.257007540
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2241757604
Short name T891
Test name
Test status
Simulation time 429339747 ps
CPU time 0.75 seconds
Started Jan 21 07:42:30 PM PST 24
Finished Jan 21 07:42:45 PM PST 24
Peak memory 200760 kb
Host smart-841a12d8-d5de-468f-9982-6deac81f3351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241757604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2241757604
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1663737898
Short name T8
Test name
Test status
Simulation time 2590723842 ps
CPU time 6.32 seconds
Started Jan 21 07:42:30 PM PST 24
Finished Jan 21 07:42:51 PM PST 24
Peak memory 200888 kb
Host smart-4407710b-9acd-4b65-af8d-7a8e7b11ca91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663737898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1663737898
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1957743032
Short name T35
Test name
Test status
Simulation time 893601318 ps
CPU time 1.41 seconds
Started Jan 21 07:42:32 PM PST 24
Finished Jan 21 07:42:46 PM PST 24
Peak memory 200956 kb
Host smart-b18859d7-8a88-48ac-b83f-4db9a98761f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957743032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1957743032
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.126423466
Short name T59
Test name
Test status
Simulation time 7900986926 ps
CPU time 20.01 seconds
Started Jan 21 07:42:30 PM PST 24
Finished Jan 21 07:43:04 PM PST 24
Peak memory 201024 kb
Host smart-13cdbc93-212e-4e99-8875-f719273aa038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126423466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.126423466
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3184982753
Short name T355
Test name
Test status
Simulation time 559212909 ps
CPU time 1.03 seconds
Started Jan 21 07:42:48 PM PST 24
Finished Jan 21 07:42:56 PM PST 24
Peak memory 200912 kb
Host smart-1a44dfe6-6c56-48a6-af81-ff70c7de0fd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184982753 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3184982753
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.984777211
Short name T72
Test name
Test status
Simulation time 406921514 ps
CPU time 1.72 seconds
Started Jan 21 07:42:50 PM PST 24
Finished Jan 21 07:43:00 PM PST 24
Peak memory 200760 kb
Host smart-f96653b2-8fd4-4363-91b5-04ca93c9c002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984777211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.984777211
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.871778856
Short name T359
Test name
Test status
Simulation time 544085253 ps
CPU time 0.98 seconds
Started Jan 21 07:42:49 PM PST 24
Finished Jan 21 07:42:59 PM PST 24
Peak memory 200280 kb
Host smart-3110badf-4368-435a-af27-e72904e8c090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871778856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.871778856
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2648192902
Short name T384
Test name
Test status
Simulation time 2309376492 ps
CPU time 3.54 seconds
Started Jan 21 07:42:45 PM PST 24
Finished Jan 21 07:42:57 PM PST 24
Peak memory 200880 kb
Host smart-90cdfcf2-cb70-4996-9948-67f4f2677b19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648192902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2648192902
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.531228523
Short name T867
Test name
Test status
Simulation time 764247394 ps
CPU time 1.49 seconds
Started Jan 21 07:42:30 PM PST 24
Finished Jan 21 07:42:46 PM PST 24
Peak memory 200980 kb
Host smart-429a6733-6006-464d-9ecd-7d3396f22f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531228523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.531228523
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1358733348
Short name T859
Test name
Test status
Simulation time 9198940469 ps
CPU time 12.66 seconds
Started Jan 21 07:42:55 PM PST 24
Finished Jan 21 07:43:15 PM PST 24
Peak memory 200780 kb
Host smart-5fb81b6a-f4f1-47fd-b0e4-2d5bb56c8379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358733348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1358733348
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1803176816
Short name T864
Test name
Test status
Simulation time 583915630 ps
CPU time 1.49 seconds
Started Jan 21 07:42:48 PM PST 24
Finished Jan 21 07:42:57 PM PST 24
Peak memory 200952 kb
Host smart-97f4d042-4430-4a2a-a0b9-82eb46d142b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803176816 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1803176816
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1031134114
Short name T377
Test name
Test status
Simulation time 636103287 ps
CPU time 0.97 seconds
Started Jan 21 07:42:50 PM PST 24
Finished Jan 21 07:42:59 PM PST 24
Peak memory 200828 kb
Host smart-0dc73bf3-c7fa-4d4a-8cb7-29679e6ac164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031134114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1031134114
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3262137095
Short name T351
Test name
Test status
Simulation time 444076077 ps
CPU time 0.77 seconds
Started Jan 21 07:42:50 PM PST 24
Finished Jan 21 07:42:58 PM PST 24
Peak memory 200780 kb
Host smart-e85d8184-5b3f-4042-823d-52a07b465f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262137095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3262137095
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2136418787
Short name T401
Test name
Test status
Simulation time 5367807346 ps
CPU time 12.45 seconds
Started Jan 21 07:42:43 PM PST 24
Finished Jan 21 07:43:05 PM PST 24
Peak memory 201008 kb
Host smart-f176771b-f860-4dff-beec-38120c896920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136418787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2136418787
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.459390571
Short name T58
Test name
Test status
Simulation time 351784738 ps
CPU time 2.17 seconds
Started Jan 21 07:42:49 PM PST 24
Finished Jan 21 07:43:00 PM PST 24
Peak memory 201080 kb
Host smart-3abe0e0c-91a0-40fd-9e7c-186f4ceae8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459390571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.459390571
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.521176932
Short name T395
Test name
Test status
Simulation time 575923976 ps
CPU time 1.15 seconds
Started Jan 21 07:42:55 PM PST 24
Finished Jan 21 07:43:03 PM PST 24
Peak memory 200924 kb
Host smart-88d02f84-18ff-454c-b5ba-4fd3c1901db0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521176932 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.521176932
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2399922040
Short name T379
Test name
Test status
Simulation time 635389769 ps
CPU time 0.95 seconds
Started Jan 21 07:42:49 PM PST 24
Finished Jan 21 07:42:58 PM PST 24
Peak memory 200848 kb
Host smart-6cba9c54-c2a3-44bb-8171-e4383de47f7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399922040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2399922040
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2490119135
Short name T402
Test name
Test status
Simulation time 389301227 ps
CPU time 1.07 seconds
Started Jan 21 07:42:46 PM PST 24
Finished Jan 21 07:42:55 PM PST 24
Peak memory 200288 kb
Host smart-13e016f1-1f98-461a-90f5-8ffc7f8f3be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490119135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2490119135
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2513037206
Short name T4
Test name
Test status
Simulation time 5306049598 ps
CPU time 2.34 seconds
Started Jan 21 07:42:55 PM PST 24
Finished Jan 21 07:43:05 PM PST 24
Peak memory 200672 kb
Host smart-6fc9aa62-cc93-4f45-9a4b-4c5a2bccc6a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513037206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2513037206
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.149073786
Short name T895
Test name
Test status
Simulation time 568781443 ps
CPU time 3.39 seconds
Started Jan 21 07:42:48 PM PST 24
Finished Jan 21 07:42:58 PM PST 24
Peak memory 201004 kb
Host smart-a978be76-b850-4891-b596-bd86c84e2fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149073786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.149073786
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3511663917
Short name T82
Test name
Test status
Simulation time 7807769213 ps
CPU time 20.37 seconds
Started Jan 21 07:42:46 PM PST 24
Finished Jan 21 07:43:15 PM PST 24
Peak memory 201024 kb
Host smart-f9692864-fb9a-4864-bd34-65df2e416228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511663917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3511663917
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1705883379
Short name T179
Test name
Test status
Simulation time 579235090 ps
CPU time 2.13 seconds
Started Jan 21 07:42:57 PM PST 24
Finished Jan 21 07:43:05 PM PST 24
Peak memory 200908 kb
Host smart-ef7b0725-41e0-499a-9ba2-bb8078b15508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705883379 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1705883379
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1191686716
Short name T371
Test name
Test status
Simulation time 464909467 ps
CPU time 1.7 seconds
Started Jan 21 07:42:50 PM PST 24
Finished Jan 21 07:43:00 PM PST 24
Peak memory 200824 kb
Host smart-4506fcfb-3e8c-4c49-a120-f502d575a816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191686716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1191686716
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2590197391
Short name T393
Test name
Test status
Simulation time 367371062 ps
CPU time 0.84 seconds
Started Jan 21 07:42:45 PM PST 24
Finished Jan 21 07:42:55 PM PST 24
Peak memory 200756 kb
Host smart-e8132e19-fafa-4a86-b142-6b4f41ca061e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590197391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2590197391
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.473667893
Short name T877
Test name
Test status
Simulation time 3936612738 ps
CPU time 5.89 seconds
Started Jan 21 07:42:57 PM PST 24
Finished Jan 21 07:43:09 PM PST 24
Peak memory 201064 kb
Host smart-ffaa9f33-e08f-431e-8858-17109f498d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473667893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.473667893
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2478120449
Short name T56
Test name
Test status
Simulation time 393890979 ps
CPU time 1.61 seconds
Started Jan 21 07:42:46 PM PST 24
Finished Jan 21 07:42:56 PM PST 24
Peak memory 201252 kb
Host smart-37e257c2-77a8-462e-9062-54e6f2411e17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478120449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2478120449
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3571524782
Short name T54
Test name
Test status
Simulation time 8644389479 ps
CPU time 12.46 seconds
Started Jan 21 07:42:48 PM PST 24
Finished Jan 21 07:43:07 PM PST 24
Peak memory 201048 kb
Host smart-688c3d29-4e70-4bb9-b7e6-875b5e57ff0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571524782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3571524782
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1247198274
Short name T885
Test name
Test status
Simulation time 854584421 ps
CPU time 2.02 seconds
Started Jan 21 07:36:58 PM PST 24
Finished Jan 21 07:37:23 PM PST 24
Peak memory 200936 kb
Host smart-cc04b5e7-b8fa-4c13-92ff-925281926a01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247198274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1247198274
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2050067083
Short name T357
Test name
Test status
Simulation time 25993434152 ps
CPU time 111.11 seconds
Started Jan 21 07:36:56 PM PST 24
Finished Jan 21 07:39:11 PM PST 24
Peak memory 201012 kb
Host smart-3b5cbdc4-c601-48fb-9169-c02b9ef15a37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050067083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2050067083
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1754580004
Short name T23
Test name
Test status
Simulation time 1389485472 ps
CPU time 1.62 seconds
Started Jan 21 07:37:00 PM PST 24
Finished Jan 21 07:37:23 PM PST 24
Peak memory 201068 kb
Host smart-3d29fbc9-cd4b-417e-b969-7745855f2486
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754580004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1754580004
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.63155179
Short name T2
Test name
Test status
Simulation time 443440573 ps
CPU time 0.93 seconds
Started Jan 21 07:36:57 PM PST 24
Finished Jan 21 07:37:21 PM PST 24
Peak memory 200840 kb
Host smart-863f1b35-b3e4-4318-a531-f3e17d29bf63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63155179 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.63155179
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2886928014
Short name T67
Test name
Test status
Simulation time 471400917 ps
CPU time 0.9 seconds
Started Jan 21 08:56:04 PM PST 24
Finished Jan 21 08:56:37 PM PST 24
Peak memory 200820 kb
Host smart-f8d7cc39-86d1-405a-97a3-c66aaf9ba486
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886928014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2886928014
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3197982498
Short name T394
Test name
Test status
Simulation time 374369281 ps
CPU time 1.35 seconds
Started Jan 21 07:36:58 PM PST 24
Finished Jan 21 07:37:22 PM PST 24
Peak memory 200744 kb
Host smart-5e237547-6dc3-4279-a3a2-600dc6613454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197982498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3197982498
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1122653148
Short name T875
Test name
Test status
Simulation time 1847716235 ps
CPU time 7.46 seconds
Started Jan 21 07:36:57 PM PST 24
Finished Jan 21 07:37:27 PM PST 24
Peak memory 200800 kb
Host smart-cbbec4c3-49c9-4ffb-86cf-1b1234a4b780
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122653148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1122653148
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3846144535
Short name T381
Test name
Test status
Simulation time 483720090 ps
CPU time 2.81 seconds
Started Jan 21 07:36:59 PM PST 24
Finished Jan 21 07:37:24 PM PST 24
Peak memory 201068 kb
Host smart-43bcf164-1aee-4c76-9dc5-4590594c7c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846144535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3846144535
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2992360982
Short name T403
Test name
Test status
Simulation time 8349825502 ps
CPU time 6.6 seconds
Started Jan 21 07:36:59 PM PST 24
Finished Jan 21 07:37:27 PM PST 24
Peak memory 201084 kb
Host smart-8a8c509c-4a18-47ec-b86c-2078ff9f3e93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992360982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2992360982
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1328270508
Short name T353
Test name
Test status
Simulation time 489939035 ps
CPU time 0.78 seconds
Started Jan 21 07:43:04 PM PST 24
Finished Jan 21 07:43:07 PM PST 24
Peak memory 200260 kb
Host smart-f852ce66-f6c1-4bd8-9ad5-b06bdcb3f8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328270508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1328270508
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1472923804
Short name T391
Test name
Test status
Simulation time 510952452 ps
CPU time 0.82 seconds
Started Jan 21 07:42:55 PM PST 24
Finished Jan 21 07:43:03 PM PST 24
Peak memory 200272 kb
Host smart-8baf9762-6173-4422-a6d4-a572d63d5131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472923804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1472923804
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3164270415
Short name T364
Test name
Test status
Simulation time 443648515 ps
CPU time 1.61 seconds
Started Jan 21 07:42:57 PM PST 24
Finished Jan 21 07:43:05 PM PST 24
Peak memory 200756 kb
Host smart-c8f6154a-886d-4fbb-b0c8-6b48e6eb2360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164270415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3164270415
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1943286615
Short name T392
Test name
Test status
Simulation time 469021695 ps
CPU time 1.72 seconds
Started Jan 21 08:53:39 PM PST 24
Finished Jan 21 08:53:58 PM PST 24
Peak memory 200664 kb
Host smart-b6507d14-5933-4247-acd5-cbbf7136cb40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943286615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1943286615
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3656078423
Short name T38
Test name
Test status
Simulation time 371949816 ps
CPU time 1.55 seconds
Started Jan 21 07:42:56 PM PST 24
Finished Jan 21 07:43:04 PM PST 24
Peak memory 200780 kb
Host smart-036a0c41-c84c-4029-aa58-645be012a13a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656078423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3656078423
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1026104721
Short name T902
Test name
Test status
Simulation time 516594937 ps
CPU time 1.76 seconds
Started Jan 21 07:43:06 PM PST 24
Finished Jan 21 07:43:12 PM PST 24
Peak memory 200732 kb
Host smart-a5177b25-f213-4e50-be0e-16fcc9a6a5ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026104721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1026104721
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2555328069
Short name T25
Test name
Test status
Simulation time 365079482 ps
CPU time 0.79 seconds
Started Jan 21 08:07:34 PM PST 24
Finished Jan 21 08:07:39 PM PST 24
Peak memory 200276 kb
Host smart-fb6dc24b-c3fa-4fe9-9454-03b001ba9f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555328069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2555328069
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.312848948
Short name T901
Test name
Test status
Simulation time 431959728 ps
CPU time 1.08 seconds
Started Jan 21 07:43:06 PM PST 24
Finished Jan 21 07:43:11 PM PST 24
Peak memory 200780 kb
Host smart-b2e93cf5-9b6a-4419-8ee3-62b856dfb810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312848948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.312848948
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1058257125
Short name T375
Test name
Test status
Simulation time 325801809 ps
CPU time 0.89 seconds
Started Jan 21 07:43:07 PM PST 24
Finished Jan 21 07:43:12 PM PST 24
Peak memory 200720 kb
Host smart-f8d9e284-cd3a-4542-98ed-012302d063c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058257125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1058257125
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2275663791
Short name T883
Test name
Test status
Simulation time 482699755 ps
CPU time 1.81 seconds
Started Jan 21 07:43:07 PM PST 24
Finished Jan 21 07:43:13 PM PST 24
Peak memory 200724 kb
Host smart-9497546f-02d7-43cd-82bc-237769407fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275663791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2275663791
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2275101282
Short name T352
Test name
Test status
Simulation time 25720912251 ps
CPU time 30.02 seconds
Started Jan 21 07:37:01 PM PST 24
Finished Jan 21 07:37:52 PM PST 24
Peak memory 201024 kb
Host smart-e37a830b-efbb-4b34-9f13-e5eb28a03310
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275101282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2275101282
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3442578356
Short name T905
Test name
Test status
Simulation time 906905888 ps
CPU time 1.73 seconds
Started Jan 21 07:37:02 PM PST 24
Finished Jan 21 07:37:23 PM PST 24
Peak memory 200716 kb
Host smart-ec8a77cc-e39b-4359-bff6-6b5878eb1622
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442578356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3442578356
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2010861099
Short name T907
Test name
Test status
Simulation time 636299446 ps
CPU time 1.38 seconds
Started Jan 21 07:37:02 PM PST 24
Finished Jan 21 07:37:23 PM PST 24
Peak memory 200768 kb
Host smart-4e7ff2e8-95c3-4e8e-90cb-7b4ed9c7382e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010861099 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2010861099
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2713973217
Short name T178
Test name
Test status
Simulation time 583137636 ps
CPU time 1.06 seconds
Started Jan 21 07:37:03 PM PST 24
Finished Jan 21 07:37:23 PM PST 24
Peak memory 200872 kb
Host smart-b7b23aa7-14a5-4456-91c0-645e7b24722c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713973217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2713973217
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3721833732
Short name T860
Test name
Test status
Simulation time 413505654 ps
CPU time 0.89 seconds
Started Jan 21 07:36:58 PM PST 24
Finished Jan 21 07:37:21 PM PST 24
Peak memory 200764 kb
Host smart-0cee2fa0-4d6a-48b1-8755-631817f55969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721833732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3721833732
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2245318740
Short name T869
Test name
Test status
Simulation time 4283178139 ps
CPU time 2.13 seconds
Started Jan 21 07:37:11 PM PST 24
Finished Jan 21 07:37:27 PM PST 24
Peak memory 201016 kb
Host smart-992c4aa7-e53d-44ca-8a4a-f71c90a82fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245318740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2245318740
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1648659710
Short name T876
Test name
Test status
Simulation time 7765629884 ps
CPU time 11.56 seconds
Started Jan 21 07:36:53 PM PST 24
Finished Jan 21 07:37:30 PM PST 24
Peak memory 201096 kb
Host smart-d6ca74b8-8729-43f7-ac9e-d3be8300f88c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648659710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1648659710
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3576442410
Short name T389
Test name
Test status
Simulation time 497896755 ps
CPU time 0.97 seconds
Started Jan 21 07:43:01 PM PST 24
Finished Jan 21 07:43:06 PM PST 24
Peak memory 200172 kb
Host smart-9d6c9aeb-9276-4f5d-a002-f7e1cf627bdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576442410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3576442410
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.4125440865
Short name T31
Test name
Test status
Simulation time 348158787 ps
CPU time 1.46 seconds
Started Jan 21 07:43:07 PM PST 24
Finished Jan 21 07:43:13 PM PST 24
Peak memory 200724 kb
Host smart-7cf88040-f46e-48a3-ae43-bf4877bf1812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125440865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.4125440865
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.767015138
Short name T370
Test name
Test status
Simulation time 349975946 ps
CPU time 0.75 seconds
Started Jan 21 07:42:57 PM PST 24
Finished Jan 21 07:43:04 PM PST 24
Peak memory 200320 kb
Host smart-5028a112-1071-4da3-93bb-104482c766ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767015138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.767015138
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2765886338
Short name T868
Test name
Test status
Simulation time 374975912 ps
CPU time 1.64 seconds
Started Jan 21 07:43:02 PM PST 24
Finished Jan 21 07:43:07 PM PST 24
Peak memory 200764 kb
Host smart-d34033a8-8511-4e69-967f-06d23c4392a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765886338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2765886338
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1378169570
Short name T356
Test name
Test status
Simulation time 388025943 ps
CPU time 1.61 seconds
Started Jan 21 07:42:57 PM PST 24
Finished Jan 21 07:43:05 PM PST 24
Peak memory 200756 kb
Host smart-7a913101-022d-453c-9770-ec4b19d3161f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378169570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1378169570
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2354886076
Short name T400
Test name
Test status
Simulation time 343479591 ps
CPU time 1.51 seconds
Started Jan 21 07:42:54 PM PST 24
Finished Jan 21 07:43:03 PM PST 24
Peak memory 200784 kb
Host smart-0c13eee9-1852-4214-8aae-2545439c273a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354886076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2354886076
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3411784920
Short name T889
Test name
Test status
Simulation time 475796186 ps
CPU time 1.81 seconds
Started Jan 21 07:43:01 PM PST 24
Finished Jan 21 07:43:07 PM PST 24
Peak memory 200676 kb
Host smart-18dd96d0-3ebd-4087-8f73-11c8a0d210ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411784920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3411784920
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3335835909
Short name T884
Test name
Test status
Simulation time 421856700 ps
CPU time 0.91 seconds
Started Jan 21 07:43:06 PM PST 24
Finished Jan 21 07:43:11 PM PST 24
Peak memory 200776 kb
Host smart-6c0a5235-8491-4339-99fa-262e53b86a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335835909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3335835909
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.58681605
Short name T368
Test name
Test status
Simulation time 543238040 ps
CPU time 0.94 seconds
Started Jan 21 08:45:08 PM PST 24
Finished Jan 21 08:45:12 PM PST 24
Peak memory 200792 kb
Host smart-037716de-16ee-4b5d-abec-abc9c2780943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58681605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.58681605
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2890520022
Short name T372
Test name
Test status
Simulation time 429934566 ps
CPU time 1.59 seconds
Started Jan 21 09:01:39 PM PST 24
Finished Jan 21 09:01:59 PM PST 24
Peak memory 200756 kb
Host smart-6402e490-a5ed-404b-9e2b-401319271396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890520022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2890520022
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1890765510
Short name T27
Test name
Test status
Simulation time 764624598 ps
CPU time 4 seconds
Started Jan 21 07:37:03 PM PST 24
Finished Jan 21 07:37:26 PM PST 24
Peak memory 200964 kb
Host smart-f5aa19aa-0a00-4720-9c89-4c40b982a135
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890765510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1890765510
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1177087795
Short name T70
Test name
Test status
Simulation time 24823830487 ps
CPU time 25.52 seconds
Started Jan 21 07:37:09 PM PST 24
Finished Jan 21 07:37:50 PM PST 24
Peak memory 201092 kb
Host smart-d9500eb0-de2d-4d72-a2a0-a00ed54b8d05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177087795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1177087795
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3812644046
Short name T900
Test name
Test status
Simulation time 1232674694 ps
CPU time 1.41 seconds
Started Jan 21 07:37:02 PM PST 24
Finished Jan 21 07:37:23 PM PST 24
Peak memory 200888 kb
Host smart-784dc90e-ca0b-4e96-b4ce-b269adfd2655
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812644046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3812644046
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.148424436
Short name T348
Test name
Test status
Simulation time 581548995 ps
CPU time 2.26 seconds
Started Jan 21 07:37:09 PM PST 24
Finished Jan 21 07:37:27 PM PST 24
Peak memory 200936 kb
Host smart-6c33afa6-2dd8-4a66-add2-dbe7ebac8c91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148424436 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.148424436
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3673816675
Short name T76
Test name
Test status
Simulation time 514230079 ps
CPU time 2.09 seconds
Started Jan 21 07:37:11 PM PST 24
Finished Jan 21 07:37:27 PM PST 24
Peak memory 200860 kb
Host smart-e49282b2-a9e1-4c83-9e41-f9241f940425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673816675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3673816675
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3939269849
Short name T382
Test name
Test status
Simulation time 363832292 ps
CPU time 1.41 seconds
Started Jan 21 07:37:02 PM PST 24
Finished Jan 21 07:37:23 PM PST 24
Peak memory 200756 kb
Host smart-786bd620-0f69-4e9e-bb9a-612a91ae22dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939269849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3939269849
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3841397916
Short name T60
Test name
Test status
Simulation time 4140222633 ps
CPU time 3.85 seconds
Started Jan 21 07:37:02 PM PST 24
Finished Jan 21 07:37:26 PM PST 24
Peak memory 201064 kb
Host smart-595e8880-f686-48c2-9d9a-748b4db899f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841397916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3841397916
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3343610300
Short name T890
Test name
Test status
Simulation time 324670560 ps
CPU time 0.85 seconds
Started Jan 21 08:37:03 PM PST 24
Finished Jan 21 08:37:07 PM PST 24
Peak memory 200736 kb
Host smart-c36ecab6-ec0d-4c19-b86a-3961270d8103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343610300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3343610300
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3428397683
Short name T361
Test name
Test status
Simulation time 380432349 ps
CPU time 0.87 seconds
Started Jan 21 07:43:03 PM PST 24
Finished Jan 21 07:43:07 PM PST 24
Peak memory 200692 kb
Host smart-8c91c8ce-502c-47a0-8cf9-2251976695a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428397683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3428397683
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.606268487
Short name T882
Test name
Test status
Simulation time 351694325 ps
CPU time 0.81 seconds
Started Jan 21 07:43:06 PM PST 24
Finished Jan 21 07:43:11 PM PST 24
Peak memory 200368 kb
Host smart-e415eb69-0dbe-4ebf-9a0a-387cdd7e74e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606268487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.606268487
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1234749973
Short name T380
Test name
Test status
Simulation time 468764217 ps
CPU time 1.17 seconds
Started Jan 21 07:42:56 PM PST 24
Finished Jan 21 07:43:04 PM PST 24
Peak memory 200664 kb
Host smart-257dabcc-b8ee-492c-aacb-9bde5eeb02c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234749973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1234749973
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1321024155
Short name T399
Test name
Test status
Simulation time 407577647 ps
CPU time 1.43 seconds
Started Jan 21 07:42:57 PM PST 24
Finished Jan 21 07:43:05 PM PST 24
Peak memory 200740 kb
Host smart-556ea9bc-f2dd-49f3-a390-072dcd857450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321024155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1321024155
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2066602654
Short name T881
Test name
Test status
Simulation time 381313850 ps
CPU time 0.88 seconds
Started Jan 21 07:42:54 PM PST 24
Finished Jan 21 07:43:02 PM PST 24
Peak memory 200764 kb
Host smart-b4b9cb07-8e4f-408a-80a6-1c8456ad169c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066602654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2066602654
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2079351327
Short name T861
Test name
Test status
Simulation time 486546348 ps
CPU time 0.93 seconds
Started Jan 21 07:43:03 PM PST 24
Finished Jan 21 07:43:07 PM PST 24
Peak memory 200760 kb
Host smart-58393b32-a670-4e51-9aaa-694e67162ebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079351327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2079351327
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3775949356
Short name T397
Test name
Test status
Simulation time 441036847 ps
CPU time 1.07 seconds
Started Jan 21 08:27:40 PM PST 24
Finished Jan 21 08:27:46 PM PST 24
Peak memory 200756 kb
Host smart-c9cce0ae-f81c-4f76-adf1-67c9c9fc941c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775949356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3775949356
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.937617883
Short name T367
Test name
Test status
Simulation time 434190088 ps
CPU time 0.74 seconds
Started Jan 21 07:43:07 PM PST 24
Finished Jan 21 07:43:12 PM PST 24
Peak memory 200720 kb
Host smart-d671b64e-b90b-44be-8a93-9075aa501b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937617883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.937617883
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3608869758
Short name T396
Test name
Test status
Simulation time 625222327 ps
CPU time 1.15 seconds
Started Jan 21 07:41:39 PM PST 24
Finished Jan 21 07:42:17 PM PST 24
Peak memory 200896 kb
Host smart-8a073382-ee95-43de-ba97-58f1e940e020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608869758 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3608869758
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3323518396
Short name T64
Test name
Test status
Simulation time 453540564 ps
CPU time 1.43 seconds
Started Jan 21 07:41:36 PM PST 24
Finished Jan 21 07:42:16 PM PST 24
Peak memory 200888 kb
Host smart-b9bb3c8c-25ee-4d17-88f3-2221aa5d8534
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323518396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3323518396
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1931183523
Short name T899
Test name
Test status
Simulation time 413296404 ps
CPU time 1.58 seconds
Started Jan 21 07:41:39 PM PST 24
Finished Jan 21 07:42:17 PM PST 24
Peak memory 200744 kb
Host smart-d968a63d-6aa4-4f60-97f0-8ed10568d3c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931183523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1931183523
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.729611936
Short name T406
Test name
Test status
Simulation time 4336196647 ps
CPU time 2.51 seconds
Started Jan 21 07:41:40 PM PST 24
Finished Jan 21 07:42:20 PM PST 24
Peak memory 201004 kb
Host smart-7a8fe3af-0fa0-402d-8e0d-7b74de12899d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729611936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.729611936
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.24552527
Short name T373
Test name
Test status
Simulation time 544838073 ps
CPU time 3.05 seconds
Started Jan 21 08:04:34 PM PST 24
Finished Jan 21 08:04:39 PM PST 24
Peak memory 209284 kb
Host smart-f4d57c52-f199-450e-90e0-250c06e18138
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24552527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.24552527
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4187392607
Short name T358
Test name
Test status
Simulation time 4169337906 ps
CPU time 3.11 seconds
Started Jan 21 07:41:37 PM PST 24
Finished Jan 21 07:42:18 PM PST 24
Peak memory 201092 kb
Host smart-7a8e4f5c-fe34-46f4-9595-dc5604f8aabd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187392607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4187392607
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2353629227
Short name T893
Test name
Test status
Simulation time 592096597 ps
CPU time 1.35 seconds
Started Jan 21 07:41:39 PM PST 24
Finished Jan 21 07:42:17 PM PST 24
Peak memory 200844 kb
Host smart-903e2046-63af-46be-911d-5e0c7a4371f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353629227 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2353629227
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.153768014
Short name T7
Test name
Test status
Simulation time 659795613 ps
CPU time 0.95 seconds
Started Jan 21 07:41:36 PM PST 24
Finished Jan 21 07:42:15 PM PST 24
Peak memory 200904 kb
Host smart-54e9dad4-7a40-4ce8-bdeb-935037506f7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153768014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.153768014
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.194925404
Short name T378
Test name
Test status
Simulation time 434397493 ps
CPU time 1.17 seconds
Started Jan 21 07:41:43 PM PST 24
Finished Jan 21 07:42:19 PM PST 24
Peak memory 200208 kb
Host smart-531eaa8d-0b63-4394-ba70-c1aefa0dc2ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194925404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.194925404
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4094479108
Short name T3
Test name
Test status
Simulation time 2610183846 ps
CPU time 3.29 seconds
Started Jan 21 07:41:38 PM PST 24
Finished Jan 21 07:42:19 PM PST 24
Peak memory 200896 kb
Host smart-40221a9e-3e13-49f5-96b9-28c6b7399308
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094479108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.4094479108
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1810240573
Short name T858
Test name
Test status
Simulation time 717599044 ps
CPU time 3.53 seconds
Started Jan 21 07:41:43 PM PST 24
Finished Jan 21 07:42:22 PM PST 24
Peak memory 209180 kb
Host smart-2e4c6b7e-7b30-47a2-98d9-3d14d3587dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810240573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1810240573
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2408634806
Short name T61
Test name
Test status
Simulation time 8095865954 ps
CPU time 21.12 seconds
Started Jan 21 07:41:38 PM PST 24
Finished Jan 21 07:42:37 PM PST 24
Peak memory 201004 kb
Host smart-17004f1e-5562-4f76-8de0-39cb85ba0a04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408634806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2408634806
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2640007461
Short name T390
Test name
Test status
Simulation time 474279296 ps
CPU time 1.96 seconds
Started Jan 21 07:41:46 PM PST 24
Finished Jan 21 07:42:21 PM PST 24
Peak memory 200952 kb
Host smart-216d098b-3657-4ccd-b178-7af3725718f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640007461 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2640007461
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3511173732
Short name T898
Test name
Test status
Simulation time 430548491 ps
CPU time 0.97 seconds
Started Jan 21 07:41:48 PM PST 24
Finished Jan 21 07:42:21 PM PST 24
Peak memory 200856 kb
Host smart-f64e6e8c-d26b-465b-a153-a765ae781bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511173732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3511173732
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2991112623
Short name T880
Test name
Test status
Simulation time 395718382 ps
CPU time 0.82 seconds
Started Jan 21 07:41:51 PM PST 24
Finished Jan 21 07:42:24 PM PST 24
Peak memory 200252 kb
Host smart-7b5459b6-462a-4500-83cc-5c2ca2980b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991112623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2991112623
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2056629877
Short name T404
Test name
Test status
Simulation time 5667174741 ps
CPU time 3.72 seconds
Started Jan 21 07:42:00 PM PST 24
Finished Jan 21 07:42:34 PM PST 24
Peak memory 201020 kb
Host smart-9e9cc3eb-b239-411d-8656-a264ae12bab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056629877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2056629877
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2888356253
Short name T383
Test name
Test status
Simulation time 540869648 ps
CPU time 2.59 seconds
Started Jan 21 07:41:41 PM PST 24
Finished Jan 21 07:42:21 PM PST 24
Peak memory 201004 kb
Host smart-abf7fe56-dcc5-483e-9699-b622cf3de778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888356253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2888356253
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3841555169
Short name T862
Test name
Test status
Simulation time 8750157964 ps
CPU time 7.37 seconds
Started Jan 21 07:41:42 PM PST 24
Finished Jan 21 07:42:25 PM PST 24
Peak memory 200980 kb
Host smart-4d343815-8fa6-4ee9-a23b-72919aa915be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841555169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3841555169
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1104939203
Short name T407
Test name
Test status
Simulation time 399418477 ps
CPU time 1.38 seconds
Started Jan 21 07:41:52 PM PST 24
Finished Jan 21 07:42:26 PM PST 24
Peak memory 200840 kb
Host smart-50fd1723-4c3d-4008-a7d5-5a4dc97e802e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104939203 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1104939203
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3333017856
Short name T65
Test name
Test status
Simulation time 405677707 ps
CPU time 1.7 seconds
Started Jan 21 07:41:48 PM PST 24
Finished Jan 21 07:42:22 PM PST 24
Peak memory 200788 kb
Host smart-6df00832-07da-4f6d-a4c0-1d8c3b002129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333017856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3333017856
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2721813472
Short name T350
Test name
Test status
Simulation time 338747502 ps
CPU time 0.8 seconds
Started Jan 21 07:41:46 PM PST 24
Finished Jan 21 07:42:20 PM PST 24
Peak memory 200784 kb
Host smart-bb85426f-12bf-441b-8043-4850235ec7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721813472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2721813472
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2978497825
Short name T28
Test name
Test status
Simulation time 4966019514 ps
CPU time 4.08 seconds
Started Jan 21 07:41:57 PM PST 24
Finished Jan 21 07:42:31 PM PST 24
Peak memory 201088 kb
Host smart-2af5efb4-2c62-4a8d-8dec-102f712fee10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978497825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2978497825
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4029559036
Short name T81
Test name
Test status
Simulation time 471830300 ps
CPU time 3.81 seconds
Started Jan 21 07:41:53 PM PST 24
Finished Jan 21 07:42:29 PM PST 24
Peak memory 209132 kb
Host smart-ce3dd4a6-5457-412d-9158-7a4f64b1af84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029559036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.4029559036
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2342842875
Short name T181
Test name
Test status
Simulation time 4349713042 ps
CPU time 6.71 seconds
Started Jan 21 07:41:45 PM PST 24
Finished Jan 21 07:42:25 PM PST 24
Peak memory 201080 kb
Host smart-36570572-82a7-4cde-9795-ae33e01d2668
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342842875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2342842875
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3326841663
Short name T879
Test name
Test status
Simulation time 360712966 ps
CPU time 1.54 seconds
Started Jan 21 07:41:57 PM PST 24
Finished Jan 21 07:42:29 PM PST 24
Peak memory 200912 kb
Host smart-fb808470-ec0b-4961-ac02-acd464659a3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326841663 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3326841663
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1568595186
Short name T78
Test name
Test status
Simulation time 412930483 ps
CPU time 1.8 seconds
Started Jan 21 07:42:00 PM PST 24
Finished Jan 21 07:42:32 PM PST 24
Peak memory 200796 kb
Host smart-3b8f99ee-59b3-4258-8015-10a20ca838f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568595186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1568595186
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4248128360
Short name T360
Test name
Test status
Simulation time 414450744 ps
CPU time 0.87 seconds
Started Jan 21 07:41:53 PM PST 24
Finished Jan 21 07:42:25 PM PST 24
Peak memory 200744 kb
Host smart-b74e5626-a48f-4f27-b400-9810eb7461bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248128360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4248128360
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3434895927
Short name T387
Test name
Test status
Simulation time 1900413010 ps
CPU time 5.11 seconds
Started Jan 21 07:41:54 PM PST 24
Finished Jan 21 07:42:30 PM PST 24
Peak memory 200788 kb
Host smart-2b5377c5-f26b-475f-997c-f617cd532380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434895927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3434895927
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.636714347
Short name T872
Test name
Test status
Simulation time 741434411 ps
CPU time 2.5 seconds
Started Jan 21 07:41:54 PM PST 24
Finished Jan 21 07:42:27 PM PST 24
Peak memory 209204 kb
Host smart-33b8b3b4-1242-4025-9fae-537359879430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636714347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.636714347
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3679480110
Short name T896
Test name
Test status
Simulation time 8361021004 ps
CPU time 22.56 seconds
Started Jan 21 07:41:49 PM PST 24
Finished Jan 21 07:42:44 PM PST 24
Peak memory 201036 kb
Host smart-7a9f9d76-5e00-4f0f-bd8a-3187e897d248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679480110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3679480110
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.352226421
Short name T595
Test name
Test status
Simulation time 354965135 ps
CPU time 0.98 seconds
Started Jan 21 03:50:16 PM PST 24
Finished Jan 21 03:50:19 PM PST 24
Peak memory 200884 kb
Host smart-65c3f551-dd03-413d-955e-53a24ae2d79d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352226421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.352226421
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2536627424
Short name T663
Test name
Test status
Simulation time 167541914759 ps
CPU time 355.62 seconds
Started Jan 21 03:50:14 PM PST 24
Finished Jan 21 03:56:11 PM PST 24
Peak memory 201076 kb
Host smart-fb6bb606-bc15-4067-94c8-e1b534c024f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536627424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2536627424
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.687880112
Short name T120
Test name
Test status
Simulation time 357603156102 ps
CPU time 220.51 seconds
Started Jan 21 03:50:01 PM PST 24
Finished Jan 21 03:53:44 PM PST 24
Peak memory 201204 kb
Host smart-5e6fa749-d468-43e0-8fa9-95b12ea6ae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687880112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.687880112
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.216631378
Short name T127
Test name
Test status
Simulation time 160882707933 ps
CPU time 377.49 seconds
Started Jan 21 04:00:07 PM PST 24
Finished Jan 21 04:06:26 PM PST 24
Peak memory 201180 kb
Host smart-cb2e01ed-9cee-4203-9cd5-95f26646ed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216631378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.216631378
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.113561290
Short name T527
Test name
Test status
Simulation time 323327876544 ps
CPU time 199.89 seconds
Started Jan 21 03:50:14 PM PST 24
Finished Jan 21 03:53:36 PM PST 24
Peak memory 201156 kb
Host smart-5a3eefc6-db27-4359-ae32-fef54c621b7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=113561290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.113561290
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1382603007
Short name T107
Test name
Test status
Simulation time 328456285284 ps
CPU time 758.05 seconds
Started Jan 21 03:50:09 PM PST 24
Finished Jan 21 04:02:49 PM PST 24
Peak memory 201224 kb
Host smart-15e61537-0175-4cd5-acb1-88f74ed1856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382603007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1382603007
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1934352771
Short name T685
Test name
Test status
Simulation time 161762840787 ps
CPU time 182.29 seconds
Started Jan 21 04:00:29 PM PST 24
Finished Jan 21 04:03:32 PM PST 24
Peak memory 201224 kb
Host smart-fb8ebcfd-ae5f-454c-87e9-0f6ede895593
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934352771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1934352771
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.526705867
Short name T662
Test name
Test status
Simulation time 481968299061 ps
CPU time 162.53 seconds
Started Jan 21 03:50:09 PM PST 24
Finished Jan 21 03:52:53 PM PST 24
Peak memory 201236 kb
Host smart-9cd817b0-3a23-41d1-a2b8-19cf5119ed59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526705867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.526705867
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1644615072
Short name T854
Test name
Test status
Simulation time 107032455020 ps
CPU time 399.93 seconds
Started Jan 21 03:50:13 PM PST 24
Finished Jan 21 03:56:54 PM PST 24
Peak memory 201676 kb
Host smart-4a30608f-09b5-46c9-9872-9741550754e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644615072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1644615072
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.438719215
Short name T660
Test name
Test status
Simulation time 22531266295 ps
CPU time 50.57 seconds
Started Jan 21 04:02:38 PM PST 24
Finished Jan 21 04:03:36 PM PST 24
Peak memory 201020 kb
Host smart-d3062a6a-e942-4b27-8f68-a2842a53282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438719215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.438719215
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1725694066
Short name T786
Test name
Test status
Simulation time 2920958344 ps
CPU time 6.85 seconds
Started Jan 21 04:13:19 PM PST 24
Finished Jan 21 04:13:29 PM PST 24
Peak memory 201028 kb
Host smart-7d7f747b-c9cc-497e-b2cd-62ebe315d9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725694066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1725694066
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2966269398
Short name T40
Test name
Test status
Simulation time 8355943923 ps
CPU time 17.12 seconds
Started Jan 21 03:50:14 PM PST 24
Finished Jan 21 03:50:33 PM PST 24
Peak memory 217292 kb
Host smart-93822f3a-7a58-43d4-b4dc-b86e7b20b902
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966269398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2966269398
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1381208755
Short name T489
Test name
Test status
Simulation time 5635456099 ps
CPU time 4.12 seconds
Started Jan 21 03:50:14 PM PST 24
Finished Jan 21 03:50:19 PM PST 24
Peak memory 200960 kb
Host smart-286acf5b-59a2-407f-a464-f2ccb7364852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381208755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1381208755
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1454188806
Short name T806
Test name
Test status
Simulation time 455799129843 ps
CPU time 862.54 seconds
Started Jan 21 03:50:15 PM PST 24
Finished Jan 21 04:04:39 PM PST 24
Peak memory 217748 kb
Host smart-5f99454d-2946-4539-bc94-68f425342957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454188806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1454188806
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3047529253
Short name T303
Test name
Test status
Simulation time 47866163690 ps
CPU time 128.97 seconds
Started Jan 21 03:50:15 PM PST 24
Finished Jan 21 03:52:26 PM PST 24
Peak memory 201588 kb
Host smart-987da287-164e-4c2c-8da9-8cd9fea015e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047529253 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3047529253
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1230254617
Short name T546
Test name
Test status
Simulation time 411987420 ps
CPU time 0.93 seconds
Started Jan 21 04:34:09 PM PST 24
Finished Jan 21 04:34:12 PM PST 24
Peak memory 200908 kb
Host smart-4c2ea9e9-03ea-417a-bdcd-4101a929afc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230254617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1230254617
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.462868572
Short name T289
Test name
Test status
Simulation time 320103455152 ps
CPU time 355.18 seconds
Started Jan 21 03:50:16 PM PST 24
Finished Jan 21 03:56:13 PM PST 24
Peak memory 201236 kb
Host smart-90cab057-ffec-449a-a09a-23eddb83c677
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462868572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.462868572
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.286449914
Short name T623
Test name
Test status
Simulation time 355673134502 ps
CPU time 201.47 seconds
Started Jan 21 03:50:13 PM PST 24
Finished Jan 21 03:53:36 PM PST 24
Peak memory 201224 kb
Host smart-ecc081da-5c46-453b-98ac-c9b142688e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286449914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.286449914
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1807741087
Short name T518
Test name
Test status
Simulation time 165331979192 ps
CPU time 76.32 seconds
Started Jan 21 03:50:17 PM PST 24
Finished Jan 21 03:51:36 PM PST 24
Peak memory 201112 kb
Host smart-eb5c9846-fb19-4ba9-99f1-1a5fbe9f9d90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807741087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1807741087
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2486314729
Short name T470
Test name
Test status
Simulation time 319883863676 ps
CPU time 785.68 seconds
Started Jan 21 03:50:12 PM PST 24
Finished Jan 21 04:03:19 PM PST 24
Peak memory 201204 kb
Host smart-5bfc8989-d0ea-46fc-83f1-c43c010ab5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486314729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2486314729
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1498908660
Short name T445
Test name
Test status
Simulation time 484929884983 ps
CPU time 1115.43 seconds
Started Jan 21 03:50:15 PM PST 24
Finished Jan 21 04:08:52 PM PST 24
Peak memory 201084 kb
Host smart-beb55027-cc8d-441f-9a52-2655ce4f3a82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498908660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1498908660
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1680153008
Short name T248
Test name
Test status
Simulation time 329648334442 ps
CPU time 711.22 seconds
Started Jan 21 03:50:17 PM PST 24
Finished Jan 21 04:02:11 PM PST 24
Peak memory 201060 kb
Host smart-60c8c306-297c-4188-a93d-3cb5d4c9ecec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680153008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1680153008
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.846118183
Short name T494
Test name
Test status
Simulation time 328703518232 ps
CPU time 791.93 seconds
Started Jan 21 03:50:15 PM PST 24
Finished Jan 21 04:03:29 PM PST 24
Peak memory 201088 kb
Host smart-ef20d02f-8f25-4a08-86e4-ab5fb7558c53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846118183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.846118183
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1306822348
Short name T738
Test name
Test status
Simulation time 104408773415 ps
CPU time 577.5 seconds
Started Jan 21 03:50:19 PM PST 24
Finished Jan 21 03:59:59 PM PST 24
Peak memory 201444 kb
Host smart-6a14d17b-d70a-4446-97f7-0eb70af2998a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306822348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1306822348
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1707062133
Short name T526
Test name
Test status
Simulation time 39444300762 ps
CPU time 24.71 seconds
Started Jan 21 03:50:13 PM PST 24
Finished Jan 21 03:50:39 PM PST 24
Peak memory 201040 kb
Host smart-9bca4fc2-07d9-4c39-b27c-aca97ecf32ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707062133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1707062133
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2506438339
Short name T532
Test name
Test status
Simulation time 3182985933 ps
CPU time 8.05 seconds
Started Jan 21 03:50:19 PM PST 24
Finished Jan 21 03:50:28 PM PST 24
Peak memory 201008 kb
Host smart-1f8b8a7f-82b3-4d41-8926-87b4cca91c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506438339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2506438339
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.689595538
Short name T41
Test name
Test status
Simulation time 8000816313 ps
CPU time 18.48 seconds
Started Jan 21 03:50:28 PM PST 24
Finished Jan 21 03:50:48 PM PST 24
Peak memory 217340 kb
Host smart-2670a004-9459-4242-8b14-762255f43339
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689595538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.689595538
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2616946337
Short name T476
Test name
Test status
Simulation time 6039685404 ps
CPU time 3.96 seconds
Started Jan 21 03:50:19 PM PST 24
Finished Jan 21 03:50:25 PM PST 24
Peak memory 200984 kb
Host smart-1900b244-b167-4f6e-8585-7936d925c46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616946337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2616946337
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3585340206
Short name T647
Test name
Test status
Simulation time 290685994 ps
CPU time 1.27 seconds
Started Jan 21 03:51:04 PM PST 24
Finished Jan 21 03:51:10 PM PST 24
Peak memory 200908 kb
Host smart-6219831e-7a2f-4708-b755-255eae40a3b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585340206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3585340206
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1927884559
Short name T505
Test name
Test status
Simulation time 324414283522 ps
CPU time 98.4 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:52:48 PM PST 24
Peak memory 201228 kb
Host smart-c050d7af-ce35-4097-acc6-cdf76b00f68c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927884559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1927884559
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3944844289
Short name T43
Test name
Test status
Simulation time 315466383775 ps
CPU time 380.41 seconds
Started Jan 21 03:51:04 PM PST 24
Finished Jan 21 03:57:29 PM PST 24
Peak memory 201080 kb
Host smart-0503dc5e-eadd-4b97-9d06-4b9b708ea6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944844289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3944844289
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1948859863
Short name T542
Test name
Test status
Simulation time 160902138086 ps
CPU time 50.58 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:51:59 PM PST 24
Peak memory 201148 kb
Host smart-f9b4b44f-41fc-4a83-8aa7-18d600482470
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948859863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1948859863
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.494501297
Short name T484
Test name
Test status
Simulation time 492527273590 ps
CPU time 337.06 seconds
Started Jan 21 03:50:59 PM PST 24
Finished Jan 21 03:56:42 PM PST 24
Peak memory 201208 kb
Host smart-45d2af05-5f2c-450e-a663-e4d8a1bbb1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494501297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.494501297
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2798794040
Short name T677
Test name
Test status
Simulation time 489559766016 ps
CPU time 928.18 seconds
Started Jan 21 03:51:04 PM PST 24
Finished Jan 21 04:06:37 PM PST 24
Peak memory 201136 kb
Host smart-2ef6211c-9a16-4efc-a77d-8bdf2b739d67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798794040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2798794040
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3286010456
Short name T538
Test name
Test status
Simulation time 336743673950 ps
CPU time 198.34 seconds
Started Jan 21 03:51:00 PM PST 24
Finished Jan 21 03:54:23 PM PST 24
Peak memory 201172 kb
Host smart-1753045e-b462-4fcd-b649-ca8b8ad1398f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286010456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3286010456
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.298241708
Short name T454
Test name
Test status
Simulation time 333577826620 ps
CPU time 180.27 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:54:10 PM PST 24
Peak memory 201120 kb
Host smart-7a690735-fe43-4f89-9b11-05533459f7c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298241708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.298241708
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3461332856
Short name T515
Test name
Test status
Simulation time 116336867547 ps
CPU time 611.44 seconds
Started Jan 21 03:51:00 PM PST 24
Finished Jan 21 04:01:16 PM PST 24
Peak memory 201380 kb
Host smart-7e40f362-65dd-49ee-aee2-b5b7f7dadcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461332856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3461332856
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.582716001
Short name T847
Test name
Test status
Simulation time 24584373812 ps
CPU time 15.77 seconds
Started Jan 21 03:51:01 PM PST 24
Finished Jan 21 03:51:20 PM PST 24
Peak memory 200992 kb
Host smart-1542d597-bc1a-4dc3-aa5b-9d8ab05dd7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582716001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.582716001
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3411819175
Short name T485
Test name
Test status
Simulation time 2669768835 ps
CPU time 2.18 seconds
Started Jan 21 03:51:20 PM PST 24
Finished Jan 21 03:51:24 PM PST 24
Peak memory 200836 kb
Host smart-e0bd8d1d-ab89-456b-b2d1-12e562620cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411819175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3411819175
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.411391868
Short name T763
Test name
Test status
Simulation time 5866169153 ps
CPU time 3.39 seconds
Started Jan 21 03:50:59 PM PST 24
Finished Jan 21 03:51:08 PM PST 24
Peak memory 200956 kb
Host smart-8970c200-a79a-4a64-9ffa-38b1673ac025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411391868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.411391868
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.457173859
Short name T752
Test name
Test status
Simulation time 10252770741 ps
CPU time 33.98 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:51:42 PM PST 24
Peak memory 209692 kb
Host smart-758fe0da-b2ab-452e-9ee1-9c24e38b3325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457173859 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.457173859
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3549336053
Short name T566
Test name
Test status
Simulation time 413758082 ps
CPU time 0.87 seconds
Started Jan 21 03:50:59 PM PST 24
Finished Jan 21 03:51:05 PM PST 24
Peak memory 200988 kb
Host smart-746c58ee-0d1f-4369-8c49-500da24cf1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549336053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3549336053
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1972315948
Short name T92
Test name
Test status
Simulation time 168889195374 ps
CPU time 176.72 seconds
Started Jan 21 03:51:09 PM PST 24
Finished Jan 21 03:54:08 PM PST 24
Peak memory 201360 kb
Host smart-d46535f1-a52f-4cdb-b3fb-1de3620ce203
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972315948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1972315948
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2314194782
Short name T261
Test name
Test status
Simulation time 332401705807 ps
CPU time 191.38 seconds
Started Jan 21 03:51:09 PM PST 24
Finished Jan 21 03:54:22 PM PST 24
Peak memory 201472 kb
Host smart-67cc0fdf-b785-4a45-a80e-672971781d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314194782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2314194782
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3018036146
Short name T269
Test name
Test status
Simulation time 329117747410 ps
CPU time 198.67 seconds
Started Jan 21 03:51:20 PM PST 24
Finished Jan 21 03:54:40 PM PST 24
Peak memory 201228 kb
Host smart-50cb0b61-5590-429a-bf90-da26c082e354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018036146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3018036146
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3095402188
Short name T599
Test name
Test status
Simulation time 492092034539 ps
CPU time 309.56 seconds
Started Jan 21 03:51:04 PM PST 24
Finished Jan 21 03:56:18 PM PST 24
Peak memory 201100 kb
Host smart-f95de2f5-13e3-4422-941d-32ed68a1b91e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095402188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3095402188
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2376218154
Short name T672
Test name
Test status
Simulation time 167951591217 ps
CPU time 101.33 seconds
Started Jan 21 03:51:08 PM PST 24
Finished Jan 21 03:52:52 PM PST 24
Peak memory 201268 kb
Host smart-17de2413-1e2f-4cf4-9b01-e539959cb97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376218154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2376218154
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1469714321
Short name T433
Test name
Test status
Simulation time 160385719912 ps
CPU time 330.9 seconds
Started Jan 21 03:51:19 PM PST 24
Finished Jan 21 03:56:50 PM PST 24
Peak memory 201128 kb
Host smart-f87bdb33-94ba-4af9-9338-c217502e0a24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469714321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1469714321
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.588582082
Short name T337
Test name
Test status
Simulation time 169753259112 ps
CPU time 214.77 seconds
Started Jan 21 03:51:20 PM PST 24
Finished Jan 21 03:54:57 PM PST 24
Peak memory 200956 kb
Host smart-8c2f7ae8-0ae8-40b1-ad06-b3e6858e1bfb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588582082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.588582082
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.705447483
Short name T605
Test name
Test status
Simulation time 169169324652 ps
CPU time 170.7 seconds
Started Jan 21 03:51:02 PM PST 24
Finished Jan 21 03:53:58 PM PST 24
Peak memory 201092 kb
Host smart-4b2996fa-4e09-434e-aff1-c3c8f3a8a199
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705447483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.705447483
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.106741083
Short name T776
Test name
Test status
Simulation time 45706143318 ps
CPU time 27.63 seconds
Started Jan 21 03:51:09 PM PST 24
Finished Jan 21 03:51:38 PM PST 24
Peak memory 201236 kb
Host smart-3950bb4b-8f97-4098-ab02-8794f50ae83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106741083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.106741083
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2570548096
Short name T676
Test name
Test status
Simulation time 4587261305 ps
CPU time 7.95 seconds
Started Jan 21 03:51:19 PM PST 24
Finished Jan 21 03:51:27 PM PST 24
Peak memory 201008 kb
Host smart-3950bf1c-dd90-4c7d-b225-a439b0a8ef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570548096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2570548096
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3459029430
Short name T443
Test name
Test status
Simulation time 6151324170 ps
CPU time 7.76 seconds
Started Jan 21 03:51:08 PM PST 24
Finished Jan 21 03:51:18 PM PST 24
Peak memory 201016 kb
Host smart-b86308bf-c970-4447-89c4-1ae8f3659002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459029430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3459029430
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2368317245
Short name T331
Test name
Test status
Simulation time 324929970460 ps
CPU time 200.16 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:54:28 PM PST 24
Peak memory 201172 kb
Host smart-2c0ae6ce-9f37-4832-b987-e066dcbea0c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368317245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2368317245
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1799679084
Short name T682
Test name
Test status
Simulation time 334182743299 ps
CPU time 227.34 seconds
Started Jan 21 03:51:19 PM PST 24
Finished Jan 21 03:55:07 PM PST 24
Peak memory 201164 kb
Host smart-c3ee0534-3af8-4688-9d65-69dd30715494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799679084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1799679084
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.671464428
Short name T97
Test name
Test status
Simulation time 163568855025 ps
CPU time 98.32 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:52:48 PM PST 24
Peak memory 201248 kb
Host smart-f8aa366e-c66e-4ccb-8c69-2d46beba8c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671464428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.671464428
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2982156077
Short name T480
Test name
Test status
Simulation time 327073068242 ps
CPU time 400.46 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:57:50 PM PST 24
Peak memory 201100 kb
Host smart-16ba5d69-33c4-4229-9a67-7b0bdf4e79cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982156077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2982156077
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.4052415725
Short name T578
Test name
Test status
Simulation time 491825653540 ps
CPU time 1109.96 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 04:09:38 PM PST 24
Peak memory 201152 kb
Host smart-49a371a4-a51c-4089-ac3a-a2101c26d4f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052415725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.4052415725
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1436855682
Short name T226
Test name
Test status
Simulation time 162926755301 ps
CPU time 141.5 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:53:31 PM PST 24
Peak memory 201148 kb
Host smart-46dafe37-2941-4480-ade0-a2b46822e976
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436855682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1436855682
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1673738390
Short name T740
Test name
Test status
Simulation time 158104100504 ps
CPU time 88.51 seconds
Started Jan 21 03:51:20 PM PST 24
Finished Jan 21 03:52:50 PM PST 24
Peak memory 200900 kb
Host smart-a79b8e00-088f-45bd-8ccd-3c284cd93891
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673738390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1673738390
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2346890256
Short name T680
Test name
Test status
Simulation time 41581576023 ps
CPU time 24.52 seconds
Started Jan 21 03:51:07 PM PST 24
Finished Jan 21 03:51:34 PM PST 24
Peak memory 201040 kb
Host smart-4b3a5f27-84bb-405e-83b7-55815f90087f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346890256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2346890256
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.338011719
Short name T416
Test name
Test status
Simulation time 4763407901 ps
CPU time 11.39 seconds
Started Jan 21 03:51:20 PM PST 24
Finished Jan 21 03:51:33 PM PST 24
Peak memory 201024 kb
Host smart-549992c1-2177-495d-a361-b554bdaa64ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338011719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.338011719
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2458861153
Short name T537
Test name
Test status
Simulation time 5760005908 ps
CPU time 3.49 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:51:13 PM PST 24
Peak memory 200988 kb
Host smart-d1e9d763-cbb6-4ef1-b263-e3e41b673409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458861153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2458861153
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3834126567
Short name T846
Test name
Test status
Simulation time 39775031436 ps
CPU time 112.48 seconds
Started Jan 21 03:51:19 PM PST 24
Finished Jan 21 03:53:12 PM PST 24
Peak memory 209748 kb
Host smart-29410f97-3496-4902-8212-16cec944492a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834126567 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3834126567
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2953672834
Short name T635
Test name
Test status
Simulation time 518523105 ps
CPU time 0.75 seconds
Started Jan 21 03:51:24 PM PST 24
Finished Jan 21 03:51:26 PM PST 24
Peak memory 200868 kb
Host smart-aaace5a2-6dc0-42ed-9961-3745790e02e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953672834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2953672834
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4104560307
Short name T855
Test name
Test status
Simulation time 165272780549 ps
CPU time 393.14 seconds
Started Jan 21 03:51:19 PM PST 24
Finished Jan 21 03:57:53 PM PST 24
Peak memory 201224 kb
Host smart-c899e5fe-e12b-4c2f-aba8-866a3cc82148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104560307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4104560307
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1480308408
Short name T674
Test name
Test status
Simulation time 164297488482 ps
CPU time 244.17 seconds
Started Jan 21 03:51:20 PM PST 24
Finished Jan 21 03:55:26 PM PST 24
Peak memory 201052 kb
Host smart-b8a543a0-d78b-4510-a0d9-5cd67336aa8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480308408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1480308408
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1985206688
Short name T802
Test name
Test status
Simulation time 328156354813 ps
CPU time 194.67 seconds
Started Jan 21 03:51:20 PM PST 24
Finished Jan 21 03:54:36 PM PST 24
Peak memory 201224 kb
Host smart-a8aaa76e-8bf7-4b9f-9dd0-6b44353823e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985206688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1985206688
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2355642175
Short name T208
Test name
Test status
Simulation time 169665923995 ps
CPU time 208.88 seconds
Started Jan 21 03:51:06 PM PST 24
Finished Jan 21 03:54:38 PM PST 24
Peak memory 201168 kb
Host smart-4f00731e-15ec-40a3-a91a-7479e1360243
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355642175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2355642175
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.4286587979
Short name T618
Test name
Test status
Simulation time 490074870657 ps
CPU time 1184.93 seconds
Started Jan 21 03:51:04 PM PST 24
Finished Jan 21 04:10:54 PM PST 24
Peak memory 201156 kb
Host smart-40d80ea2-7680-418b-a4ff-40a9469ef28b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286587979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.4286587979
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2791073138
Short name T501
Test name
Test status
Simulation time 88481641420 ps
CPU time 455.58 seconds
Started Jan 21 03:51:22 PM PST 24
Finished Jan 21 03:58:59 PM PST 24
Peak memory 201412 kb
Host smart-0c3e79e5-727b-40d9-a461-0fe6812bd6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791073138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2791073138
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.708474731
Short name T568
Test name
Test status
Simulation time 31747545748 ps
CPU time 7.85 seconds
Started Jan 21 03:51:12 PM PST 24
Finished Jan 21 03:51:20 PM PST 24
Peak memory 201012 kb
Host smart-0ed0b190-9bd0-4e11-b7d4-40c6d00d7afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708474731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.708474731
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.447772417
Short name T851
Test name
Test status
Simulation time 3201076106 ps
CPU time 8.14 seconds
Started Jan 21 03:51:12 PM PST 24
Finished Jan 21 03:51:21 PM PST 24
Peak memory 201240 kb
Host smart-adb3feeb-a2b4-41d8-a61a-3d0f68cd95e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447772417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.447772417
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1352813927
Short name T675
Test name
Test status
Simulation time 6005656536 ps
CPU time 7.77 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:51:15 PM PST 24
Peak memory 201008 kb
Host smart-b879c9e2-3724-409a-a269-5e1e1c26cf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352813927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1352813927
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3554873280
Short name T488
Test name
Test status
Simulation time 46671683427 ps
CPU time 28.34 seconds
Started Jan 21 03:51:28 PM PST 24
Finished Jan 21 03:51:57 PM PST 24
Peak memory 201024 kb
Host smart-ad4ec0f4-cf47-40bc-aa09-dfc7f417d425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554873280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3554873280
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3915920939
Short name T749
Test name
Test status
Simulation time 570917327 ps
CPU time 0.82 seconds
Started Jan 21 03:51:33 PM PST 24
Finished Jan 21 03:51:34 PM PST 24
Peak memory 200968 kb
Host smart-a34ebd63-2632-4531-b94b-f715e91ba170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915920939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3915920939
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2364054157
Short name T273
Test name
Test status
Simulation time 161579785751 ps
CPU time 387.12 seconds
Started Jan 21 03:51:32 PM PST 24
Finished Jan 21 03:58:00 PM PST 24
Peak memory 201172 kb
Host smart-c9860c44-7386-4dc9-a883-b6ca5d3fb8c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364054157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2364054157
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.435166237
Short name T335
Test name
Test status
Simulation time 322228475993 ps
CPU time 719.8 seconds
Started Jan 21 03:51:23 PM PST 24
Finished Jan 21 04:03:24 PM PST 24
Peak memory 201188 kb
Host smart-e9188f83-edfb-4e02-896a-bc5bbd7e407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435166237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.435166237
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1126859093
Short name T759
Test name
Test status
Simulation time 325909811187 ps
CPU time 393.03 seconds
Started Jan 21 03:51:25 PM PST 24
Finished Jan 21 03:57:58 PM PST 24
Peak memory 201156 kb
Host smart-5f8ac576-f63d-4b48-8d0f-5ca9630bd28b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126859093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1126859093
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1912222858
Short name T832
Test name
Test status
Simulation time 162609881669 ps
CPU time 102.61 seconds
Started Jan 21 03:51:19 PM PST 24
Finished Jan 21 03:53:04 PM PST 24
Peak memory 201152 kb
Host smart-f6eb31bb-06e6-4b8f-8bca-67560b4da7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912222858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1912222858
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3645008599
Short name T833
Test name
Test status
Simulation time 328161146161 ps
CPU time 172.05 seconds
Started Jan 21 03:51:19 PM PST 24
Finished Jan 21 03:54:13 PM PST 24
Peak memory 201172 kb
Host smart-df6fdc1d-8b40-4e84-902c-352e17377faf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645008599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3645008599
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1912930310
Short name T584
Test name
Test status
Simulation time 338905626931 ps
CPU time 179.73 seconds
Started Jan 21 03:51:20 PM PST 24
Finished Jan 21 03:54:22 PM PST 24
Peak memory 201244 kb
Host smart-54cae7e1-f4ea-45cd-bb0e-b05714703142
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912930310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1912930310
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1794083422
Short name T539
Test name
Test status
Simulation time 108169491619 ps
CPU time 355.46 seconds
Started Jan 21 03:51:40 PM PST 24
Finished Jan 21 03:57:37 PM PST 24
Peak memory 201424 kb
Host smart-fec22ea2-e5b7-41af-84aa-d19cc6eb7e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794083422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1794083422
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1565656875
Short name T581
Test name
Test status
Simulation time 32698704170 ps
CPU time 18.28 seconds
Started Jan 21 03:51:31 PM PST 24
Finished Jan 21 03:51:50 PM PST 24
Peak memory 201032 kb
Host smart-dc9e6ff2-5104-4a02-94a9-1d05dbe551b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565656875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1565656875
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3269445854
Short name T519
Test name
Test status
Simulation time 3836727903 ps
CPU time 2.79 seconds
Started Jan 21 03:51:32 PM PST 24
Finished Jan 21 03:51:35 PM PST 24
Peak memory 201036 kb
Host smart-06c91b1b-b767-47fe-bee6-14031fa66ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269445854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3269445854
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1254532242
Short name T464
Test name
Test status
Simulation time 5975196804 ps
CPU time 11.93 seconds
Started Jan 21 03:51:27 PM PST 24
Finished Jan 21 03:51:40 PM PST 24
Peak memory 200976 kb
Host smart-05f7c39a-4eee-47c3-8850-d5dad32f348d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254532242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1254532242
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3980160934
Short name T615
Test name
Test status
Simulation time 240889200592 ps
CPU time 794.51 seconds
Started Jan 21 03:51:29 PM PST 24
Finished Jan 21 04:04:45 PM PST 24
Peak memory 201568 kb
Host smart-50f1a3f7-5e5b-42e7-80dd-85f0e5b64d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980160934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3980160934
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.656155550
Short name T158
Test name
Test status
Simulation time 32302494745 ps
CPU time 103.11 seconds
Started Jan 21 03:51:31 PM PST 24
Finished Jan 21 03:53:15 PM PST 24
Peak memory 209800 kb
Host smart-58777827-8f23-49c9-b58f-cc1d0ef24dc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656155550 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.656155550
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1817977092
Short name T593
Test name
Test status
Simulation time 467311603 ps
CPU time 1.47 seconds
Started Jan 21 03:51:57 PM PST 24
Finished Jan 21 03:51:59 PM PST 24
Peak memory 200916 kb
Host smart-859a216e-cb18-49ee-be0c-4e589f053ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817977092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1817977092
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2473067765
Short name T48
Test name
Test status
Simulation time 335414923573 ps
CPU time 848.24 seconds
Started Jan 21 04:30:48 PM PST 24
Finished Jan 21 04:44:57 PM PST 24
Peak memory 201244 kb
Host smart-e8c95e68-68ed-4d74-b902-50fec06e4f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473067765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2473067765
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1239886704
Short name T658
Test name
Test status
Simulation time 487007938117 ps
CPU time 1155.26 seconds
Started Jan 21 03:51:39 PM PST 24
Finished Jan 21 04:10:55 PM PST 24
Peak memory 201196 kb
Host smart-80225b98-dbe2-40dc-9c7b-36a78ab4a5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239886704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1239886704
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1622603457
Short name T606
Test name
Test status
Simulation time 496798592420 ps
CPU time 1199.69 seconds
Started Jan 21 04:08:21 PM PST 24
Finished Jan 21 04:28:24 PM PST 24
Peak memory 201168 kb
Host smart-6269e54b-e5a0-41b4-8547-42fa1453f946
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622603457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1622603457
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3624362836
Short name T116
Test name
Test status
Simulation time 163895350274 ps
CPU time 80.11 seconds
Started Jan 21 03:51:34 PM PST 24
Finished Jan 21 03:52:55 PM PST 24
Peak memory 201216 kb
Host smart-44dc9ba3-4d11-4453-bfef-c597413731b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624362836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3624362836
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.886958065
Short name T483
Test name
Test status
Simulation time 498163134204 ps
CPU time 614.45 seconds
Started Jan 21 03:51:42 PM PST 24
Finished Jan 21 04:01:57 PM PST 24
Peak memory 201148 kb
Host smart-a9892544-ae2c-419e-9e34-e1129d594755
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=886958065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.886958065
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.4137148901
Short name T156
Test name
Test status
Simulation time 166256031006 ps
CPU time 144.7 seconds
Started Jan 21 03:51:40 PM PST 24
Finished Jan 21 03:54:05 PM PST 24
Peak memory 201140 kb
Host smart-8329e903-7a17-4be3-a40f-b9a885332883
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137148901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.4137148901
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.922288227
Short name T545
Test name
Test status
Simulation time 167336770996 ps
CPU time 187.16 seconds
Started Jan 21 05:34:47 PM PST 24
Finished Jan 21 05:37:55 PM PST 24
Peak memory 201168 kb
Host smart-fbff156a-eb9c-4b69-bc08-6aa7405a0c76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922288227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.922288227
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1417045886
Short name T192
Test name
Test status
Simulation time 98648890686 ps
CPU time 350.16 seconds
Started Jan 21 03:51:45 PM PST 24
Finished Jan 21 03:57:36 PM PST 24
Peak memory 201432 kb
Host smart-584546b7-05c4-4111-aa17-38f31e9d7c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417045886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1417045886
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.275675855
Short name T558
Test name
Test status
Simulation time 26641798171 ps
CPU time 17.82 seconds
Started Jan 21 04:01:05 PM PST 24
Finished Jan 21 04:01:24 PM PST 24
Peak memory 200956 kb
Host smart-2b003e6a-da3b-4912-9dd1-820b9298f7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275675855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.275675855
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3220866481
Short name T850
Test name
Test status
Simulation time 3258955834 ps
CPU time 7.76 seconds
Started Jan 21 04:13:15 PM PST 24
Finished Jan 21 04:13:24 PM PST 24
Peak memory 201036 kb
Host smart-f52fa72f-9d59-4119-9dba-8549fb8b3229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220866481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3220866481
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2309429889
Short name T486
Test name
Test status
Simulation time 5918746421 ps
CPU time 15.54 seconds
Started Jan 21 03:51:35 PM PST 24
Finished Jan 21 03:51:51 PM PST 24
Peak memory 201020 kb
Host smart-68eb061c-02bf-4fa7-bc2c-1a6de1cc03d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309429889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2309429889
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1886628358
Short name T250
Test name
Test status
Simulation time 105166594700 ps
CPU time 65.48 seconds
Started Jan 21 03:51:57 PM PST 24
Finished Jan 21 03:53:03 PM PST 24
Peak memory 209536 kb
Host smart-3a5b898c-d555-45d3-a1e0-d09e024aaa22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886628358 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1886628358
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3763496640
Short name T583
Test name
Test status
Simulation time 375457860 ps
CPU time 0.79 seconds
Started Jan 21 03:59:31 PM PST 24
Finished Jan 21 03:59:34 PM PST 24
Peak memory 200924 kb
Host smart-28b5deb6-b07e-4cf8-943d-cf52605e81ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763496640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3763496640
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1540998744
Short name T132
Test name
Test status
Simulation time 329624950294 ps
CPU time 342.83 seconds
Started Jan 21 03:51:56 PM PST 24
Finished Jan 21 03:57:39 PM PST 24
Peak memory 201056 kb
Host smart-b950b9c2-bc2b-4ac3-a07f-9b2976f06bfc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540998744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1540998744
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3495775309
Short name T93
Test name
Test status
Simulation time 496148285943 ps
CPU time 222.52 seconds
Started Jan 21 03:51:54 PM PST 24
Finished Jan 21 03:55:37 PM PST 24
Peak memory 201200 kb
Host smart-1a07c05a-815f-4b52-85ba-47fb98e3061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495775309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3495775309
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.222723423
Short name T652
Test name
Test status
Simulation time 332769316068 ps
CPU time 295.69 seconds
Started Jan 21 03:51:57 PM PST 24
Finished Jan 21 03:56:54 PM PST 24
Peak memory 201160 kb
Host smart-1c83c0c0-eb23-4dc3-9405-0fc02223a3ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=222723423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.222723423
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1983639158
Short name T330
Test name
Test status
Simulation time 329247370836 ps
CPU time 772.6 seconds
Started Jan 21 03:51:56 PM PST 24
Finished Jan 21 04:04:49 PM PST 24
Peak memory 201204 kb
Host smart-0de350f4-ec3d-4009-86de-bd93e8eb3c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983639158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1983639158
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2620318206
Short name T422
Test name
Test status
Simulation time 493954024352 ps
CPU time 289.97 seconds
Started Jan 21 03:51:57 PM PST 24
Finished Jan 21 03:56:48 PM PST 24
Peak memory 201224 kb
Host smart-43ad9fc5-0eae-4577-9c7f-9ff9a144698e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620318206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2620318206
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2353247211
Short name T534
Test name
Test status
Simulation time 164426270448 ps
CPU time 99.84 seconds
Started Jan 21 04:06:51 PM PST 24
Finished Jan 21 04:08:45 PM PST 24
Peak memory 201156 kb
Host smart-9cbcbe45-0934-410b-9f98-59a1bffac64e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353247211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2353247211
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.4058060925
Short name T475
Test name
Test status
Simulation time 34757170467 ps
CPU time 78.25 seconds
Started Jan 21 04:39:30 PM PST 24
Finished Jan 21 04:40:49 PM PST 24
Peak memory 201036 kb
Host smart-1765b5af-caa8-4307-bebe-302bbfa24573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058060925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.4058060925
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.17764178
Short name T732
Test name
Test status
Simulation time 5330661907 ps
CPU time 4.56 seconds
Started Jan 21 03:52:01 PM PST 24
Finished Jan 21 03:52:06 PM PST 24
Peak memory 201000 kb
Host smart-5b5c7f37-12cc-4837-a349-1b904431efad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17764178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.17764178
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.562562755
Short name T576
Test name
Test status
Simulation time 5901432428 ps
CPU time 1.82 seconds
Started Jan 21 03:51:56 PM PST 24
Finished Jan 21 03:51:58 PM PST 24
Peak memory 200944 kb
Host smart-2a1c848e-58d6-4496-aad5-f87f7fd1e656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562562755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.562562755
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3524462069
Short name T292
Test name
Test status
Simulation time 566483647099 ps
CPU time 579.99 seconds
Started Jan 21 03:52:02 PM PST 24
Finished Jan 21 04:01:43 PM PST 24
Peak memory 201568 kb
Host smart-102990d0-0784-4353-a86f-3bd9f2696ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524462069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3524462069
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.4055275498
Short name T83
Test name
Test status
Simulation time 107237564180 ps
CPU time 169.69 seconds
Started Jan 21 03:52:02 PM PST 24
Finished Jan 21 03:54:53 PM PST 24
Peak memory 209380 kb
Host smart-2343f036-da9e-457f-a01e-29c8b1943ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055275498 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.4055275498
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.420467255
Short name T659
Test name
Test status
Simulation time 591269020 ps
CPU time 0.67 seconds
Started Jan 21 03:52:22 PM PST 24
Finished Jan 21 03:52:23 PM PST 24
Peak memory 200968 kb
Host smart-9ee2c7c9-ab3a-495a-a8b3-b7b55e200e7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420467255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.420467255
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2248201621
Short name T596
Test name
Test status
Simulation time 507331028534 ps
CPU time 586.08 seconds
Started Jan 21 03:52:12 PM PST 24
Finished Jan 21 04:02:02 PM PST 24
Peak memory 201228 kb
Host smart-5acbb2e6-5d5f-4330-84e9-b0ea0e25523e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248201621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2248201621
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3775109837
Short name T50
Test name
Test status
Simulation time 334271054738 ps
CPU time 793.81 seconds
Started Jan 21 03:52:15 PM PST 24
Finished Jan 21 04:05:32 PM PST 24
Peak memory 201240 kb
Host smart-c40bcd96-8cfa-4f39-a0bc-87cb3ef6b7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775109837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3775109837
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1741008963
Short name T844
Test name
Test status
Simulation time 493532528638 ps
CPU time 604.16 seconds
Started Jan 21 03:52:18 PM PST 24
Finished Jan 21 04:02:25 PM PST 24
Peak memory 201160 kb
Host smart-e9ffe849-f132-4b63-8c1f-686e52e5ea00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741008963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1741008963
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1526471700
Short name T727
Test name
Test status
Simulation time 165958172839 ps
CPU time 92.47 seconds
Started Jan 21 03:52:02 PM PST 24
Finished Jan 21 03:53:36 PM PST 24
Peak memory 201268 kb
Host smart-72916b12-5711-4a39-afe6-099ed015ff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526471700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1526471700
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2510040168
Short name T656
Test name
Test status
Simulation time 494432731183 ps
CPU time 1110.41 seconds
Started Jan 21 03:52:15 PM PST 24
Finished Jan 21 04:10:48 PM PST 24
Peak memory 201232 kb
Host smart-10c6ab88-049c-41a8-9b2f-7c1902b4af74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510040168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2510040168
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2797797248
Short name T830
Test name
Test status
Simulation time 158936704639 ps
CPU time 177.27 seconds
Started Jan 21 03:52:12 PM PST 24
Finished Jan 21 03:55:14 PM PST 24
Peak memory 201056 kb
Host smart-058036b0-d760-459d-819b-3eed81ffc2a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797797248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2797797248
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2367335579
Short name T459
Test name
Test status
Simulation time 485510808818 ps
CPU time 401.35 seconds
Started Jan 21 03:52:11 PM PST 24
Finished Jan 21 03:58:58 PM PST 24
Peak memory 201152 kb
Host smart-eb4dfa9e-651f-4b8a-9995-b367ab66b546
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367335579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2367335579
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.502952223
Short name T342
Test name
Test status
Simulation time 109461171049 ps
CPU time 477.88 seconds
Started Jan 21 03:52:21 PM PST 24
Finished Jan 21 04:00:20 PM PST 24
Peak memory 201476 kb
Host smart-90c5f673-1417-4cb9-bf07-a3a2e136b797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502952223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.502952223
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3840173442
Short name T411
Test name
Test status
Simulation time 37280992095 ps
CPU time 40.03 seconds
Started Jan 21 03:52:21 PM PST 24
Finished Jan 21 03:53:02 PM PST 24
Peak memory 201028 kb
Host smart-ed114f22-ab85-4407-ac80-f7a58f5d418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840173442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3840173442
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4022193530
Short name T425
Test name
Test status
Simulation time 4804808079 ps
CPU time 4.55 seconds
Started Jan 21 03:52:19 PM PST 24
Finished Jan 21 03:52:26 PM PST 24
Peak memory 201020 kb
Host smart-2e2fe674-1a00-4e35-903b-cfb491b12358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022193530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4022193530
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2388759622
Short name T608
Test name
Test status
Simulation time 5911505052 ps
CPU time 14.46 seconds
Started Jan 21 04:00:29 PM PST 24
Finished Jan 21 04:00:45 PM PST 24
Peak memory 201028 kb
Host smart-21eb5205-5194-446d-9cfa-b97032f1ce84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388759622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2388759622
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2217981208
Short name T835
Test name
Test status
Simulation time 63123660233 ps
CPU time 150.57 seconds
Started Jan 21 03:52:23 PM PST 24
Finished Jan 21 03:54:54 PM PST 24
Peak memory 209828 kb
Host smart-ff578b53-1066-4679-b6ca-bc1ba30ca114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217981208 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2217981208
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.881008418
Short name T408
Test name
Test status
Simulation time 480993071 ps
CPU time 1.77 seconds
Started Jan 21 03:52:41 PM PST 24
Finished Jan 21 03:52:44 PM PST 24
Peak memory 200972 kb
Host smart-859bc836-8b7f-4816-9def-74d1198e08d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881008418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.881008418
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4181238739
Short name T315
Test name
Test status
Simulation time 164317171543 ps
CPU time 32.71 seconds
Started Jan 21 03:52:21 PM PST 24
Finished Jan 21 03:52:55 PM PST 24
Peak memory 201192 kb
Host smart-1f6639ae-3161-4770-8877-42760ce21bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181238739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.4181238739
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3733080359
Short name T723
Test name
Test status
Simulation time 332680188328 ps
CPU time 730.81 seconds
Started Jan 21 03:52:29 PM PST 24
Finished Jan 21 04:04:41 PM PST 24
Peak memory 201344 kb
Host smart-199a2113-351c-40a7-838f-170281d061ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733080359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3733080359
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.619148892
Short name T758
Test name
Test status
Simulation time 496843621631 ps
CPU time 636.64 seconds
Started Jan 21 03:52:21 PM PST 24
Finished Jan 21 04:02:59 PM PST 24
Peak memory 201260 kb
Host smart-aa61b599-4866-420f-b7ea-08d18b8d73cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619148892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.619148892
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3340648678
Short name T457
Test name
Test status
Simulation time 160713876026 ps
CPU time 98.21 seconds
Started Jan 21 03:52:22 PM PST 24
Finished Jan 21 03:54:01 PM PST 24
Peak memory 201132 kb
Host smart-19bbe21e-7a1d-472c-b6f9-5fdb7baec966
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340648678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3340648678
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2124273505
Short name T741
Test name
Test status
Simulation time 380394653165 ps
CPU time 872.01 seconds
Started Jan 21 03:52:36 PM PST 24
Finished Jan 21 04:07:09 PM PST 24
Peak memory 201160 kb
Host smart-eff3931e-7f3a-448b-8690-abfd20822e1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124273505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2124273505
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2528502350
Short name T447
Test name
Test status
Simulation time 328332402091 ps
CPU time 72.76 seconds
Started Jan 21 03:52:36 PM PST 24
Finished Jan 21 03:53:50 PM PST 24
Peak memory 201216 kb
Host smart-31201d5a-e78a-49a4-944b-a74bac503bca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528502350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2528502350
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.4019541321
Short name T198
Test name
Test status
Simulation time 107321792769 ps
CPU time 378.73 seconds
Started Jan 21 03:52:41 PM PST 24
Finished Jan 21 03:59:00 PM PST 24
Peak memory 201540 kb
Host smart-c6694b76-f24c-4158-ab2a-17b409fe0a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019541321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.4019541321
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3425425927
Short name T616
Test name
Test status
Simulation time 28286932281 ps
CPU time 16.09 seconds
Started Jan 21 03:52:36 PM PST 24
Finished Jan 21 03:52:53 PM PST 24
Peak memory 200996 kb
Host smart-8b1e5fb4-0a1a-49bb-9507-55720d6b8b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425425927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3425425927
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.126609312
Short name T666
Test name
Test status
Simulation time 4202022436 ps
CPU time 3.34 seconds
Started Jan 21 03:52:36 PM PST 24
Finished Jan 21 03:52:40 PM PST 24
Peak memory 201012 kb
Host smart-18fffb67-0162-4174-ad0a-85e62cd660c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126609312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.126609312
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2439240594
Short name T591
Test name
Test status
Simulation time 5889345315 ps
CPU time 4.21 seconds
Started Jan 21 03:52:19 PM PST 24
Finished Jan 21 03:52:26 PM PST 24
Peak memory 200928 kb
Host smart-e1572308-0c1a-4181-b7ce-153d11deb2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439240594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2439240594
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2776037236
Short name T535
Test name
Test status
Simulation time 428377036 ps
CPU time 1.55 seconds
Started Jan 21 03:52:52 PM PST 24
Finished Jan 21 03:52:54 PM PST 24
Peak memory 200940 kb
Host smart-e041a76d-17cb-4321-bf38-6e6b10178913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776037236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2776037236
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1831888450
Short name T592
Test name
Test status
Simulation time 337559545751 ps
CPU time 370.49 seconds
Started Jan 21 03:52:46 PM PST 24
Finished Jan 21 03:58:58 PM PST 24
Peak memory 201148 kb
Host smart-7007b2bf-108f-4dcc-bfe8-42c021122ff7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831888450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1831888450
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.4188777217
Short name T175
Test name
Test status
Simulation time 491246792897 ps
CPU time 303.33 seconds
Started Jan 21 03:52:57 PM PST 24
Finished Jan 21 03:58:02 PM PST 24
Peak memory 201184 kb
Host smart-47ec9e4e-a106-45fd-a703-91e4286550c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188777217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.4188777217
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1331357722
Short name T497
Test name
Test status
Simulation time 488478238578 ps
CPU time 1081.95 seconds
Started Jan 21 03:52:56 PM PST 24
Finished Jan 21 04:10:59 PM PST 24
Peak memory 201180 kb
Host smart-a2c78eb3-2b38-423b-b2aa-c9be14a5173e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331357722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1331357722
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2381971436
Short name T604
Test name
Test status
Simulation time 328776688061 ps
CPU time 363.97 seconds
Started Jan 21 03:52:37 PM PST 24
Finished Jan 21 03:58:42 PM PST 24
Peak memory 201212 kb
Host smart-4d5dd5e5-218e-4a1a-a108-51baa884f214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381971436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2381971436
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.251945919
Short name T769
Test name
Test status
Simulation time 166900139528 ps
CPU time 106.31 seconds
Started Jan 21 03:52:56 PM PST 24
Finished Jan 21 03:54:43 PM PST 24
Peak memory 201240 kb
Host smart-122599a4-9fa3-4e8a-9751-0b6ef605e002
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=251945919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.251945919
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2537981612
Short name T157
Test name
Test status
Simulation time 320219389349 ps
CPU time 141 seconds
Started Jan 21 03:52:49 PM PST 24
Finished Jan 21 03:55:10 PM PST 24
Peak memory 201240 kb
Host smart-138a3703-3431-4e5d-b035-e08d333de2bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537981612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2537981612
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2400796893
Short name T183
Test name
Test status
Simulation time 121872584450 ps
CPU time 658.19 seconds
Started Jan 21 03:52:51 PM PST 24
Finished Jan 21 04:03:50 PM PST 24
Peak memory 201472 kb
Host smart-114f8409-72c1-4429-b26d-2d31e059fc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400796893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2400796893
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.395521703
Short name T724
Test name
Test status
Simulation time 39283743868 ps
CPU time 86.5 seconds
Started Jan 21 03:52:56 PM PST 24
Finished Jan 21 03:54:24 PM PST 24
Peak memory 201232 kb
Host smart-0cef7b68-d50c-416c-b78d-19e040a5fcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395521703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.395521703
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3991963390
Short name T757
Test name
Test status
Simulation time 4200878223 ps
CPU time 10.11 seconds
Started Jan 21 03:52:45 PM PST 24
Finished Jan 21 03:52:56 PM PST 24
Peak memory 200980 kb
Host smart-587983fc-aa03-420e-9aba-a809a2bd5425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991963390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3991963390
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1719227728
Short name T573
Test name
Test status
Simulation time 5868338318 ps
CPU time 14.48 seconds
Started Jan 21 03:52:36 PM PST 24
Finished Jan 21 03:52:52 PM PST 24
Peak memory 200956 kb
Host smart-1f8bc5c6-93da-4f9c-8c6d-b712d5636984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719227728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1719227728
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.389698113
Short name T123
Test name
Test status
Simulation time 333956438016 ps
CPU time 328.24 seconds
Started Jan 21 03:52:54 PM PST 24
Finished Jan 21 03:58:24 PM PST 24
Peak memory 201184 kb
Host smart-04e6744d-6bd1-4323-883c-fd1d4bdecd89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389698113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
389698113
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.91096236
Short name T305
Test name
Test status
Simulation time 141846630716 ps
CPU time 110.77 seconds
Started Jan 21 03:52:54 PM PST 24
Finished Jan 21 03:54:46 PM PST 24
Peak memory 209688 kb
Host smart-4ed582b9-e6bb-4a37-827f-726f266ee22b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91096236 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.91096236
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.684962313
Short name T536
Test name
Test status
Simulation time 526651247 ps
CPU time 1.9 seconds
Started Jan 21 03:50:24 PM PST 24
Finished Jan 21 03:50:27 PM PST 24
Peak memory 200948 kb
Host smart-77d924d8-723d-4173-b9b7-be2cdb57258c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684962313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.684962313
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3336412192
Short name T267
Test name
Test status
Simulation time 325877606940 ps
CPU time 737.1 seconds
Started Jan 21 03:50:28 PM PST 24
Finished Jan 21 04:02:46 PM PST 24
Peak memory 200996 kb
Host smart-3c3b9317-8afd-4552-b103-733ac8046800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336412192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3336412192
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3050306327
Short name T493
Test name
Test status
Simulation time 499805316143 ps
CPU time 132.1 seconds
Started Jan 21 03:50:28 PM PST 24
Finished Jan 21 03:52:41 PM PST 24
Peak memory 201180 kb
Host smart-56c83dab-b921-4292-8009-62d4302a3b00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050306327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3050306327
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1209121902
Short name T796
Test name
Test status
Simulation time 160141663551 ps
CPU time 356.26 seconds
Started Jan 21 03:50:28 PM PST 24
Finished Jan 21 03:56:25 PM PST 24
Peak memory 201272 kb
Host smart-f9168ff1-e6eb-4a12-b182-b51769c9669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209121902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1209121902
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.4027728711
Short name T774
Test name
Test status
Simulation time 498189098648 ps
CPU time 288.95 seconds
Started Jan 21 03:50:26 PM PST 24
Finished Jan 21 03:55:16 PM PST 24
Peak memory 201176 kb
Host smart-75408fcf-4925-40fa-97d7-bf0a62f88d96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027728711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.4027728711
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1068599186
Short name T321
Test name
Test status
Simulation time 493223673688 ps
CPU time 262.96 seconds
Started Jan 21 03:50:13 PM PST 24
Finished Jan 21 03:54:37 PM PST 24
Peak memory 201180 kb
Host smart-1640ef4f-da83-42cb-8ba5-ff1d76e82411
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068599186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1068599186
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.495755180
Short name T739
Test name
Test status
Simulation time 166925142930 ps
CPU time 392.15 seconds
Started Jan 21 03:50:28 PM PST 24
Finished Jan 21 03:57:01 PM PST 24
Peak memory 201224 kb
Host smart-c9bb195a-3431-4360-80f9-204764724bd8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495755180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.495755180
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1029400211
Short name T637
Test name
Test status
Simulation time 118540505960 ps
CPU time 446.14 seconds
Started Jan 21 03:50:27 PM PST 24
Finished Jan 21 03:57:54 PM PST 24
Peak memory 201424 kb
Host smart-57afb686-4bbd-4e82-aec2-0f2526c8a990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029400211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1029400211
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1666758077
Short name T590
Test name
Test status
Simulation time 38862013816 ps
CPU time 68.79 seconds
Started Jan 21 03:50:25 PM PST 24
Finished Jan 21 03:51:35 PM PST 24
Peak memory 201032 kb
Host smart-133c7e12-ad74-4155-bc22-68b081c1aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666758077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1666758077
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3568422877
Short name T602
Test name
Test status
Simulation time 4234153159 ps
CPU time 3.87 seconds
Started Jan 21 03:50:21 PM PST 24
Finished Jan 21 03:50:26 PM PST 24
Peak memory 200996 kb
Host smart-e96a5316-dec2-474c-b223-da5a78535236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568422877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3568422877
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3266269910
Short name T86
Test name
Test status
Simulation time 5910430535 ps
CPU time 4.29 seconds
Started Jan 21 03:50:13 PM PST 24
Finished Jan 21 03:50:19 PM PST 24
Peak memory 201016 kb
Host smart-5c83d60d-1043-4431-93a9-fbcbb31882b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266269910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3266269910
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.588043654
Short name T756
Test name
Test status
Simulation time 202174453053 ps
CPU time 465.25 seconds
Started Jan 21 03:50:21 PM PST 24
Finished Jan 21 03:58:07 PM PST 24
Peak memory 201172 kb
Host smart-f08d39de-9c5d-485b-aa90-5909f71d16ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588043654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.588043654
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.4153929853
Short name T700
Test name
Test status
Simulation time 116004222200 ps
CPU time 163.67 seconds
Started Jan 21 03:50:22 PM PST 24
Finished Jan 21 03:53:07 PM PST 24
Peak memory 215600 kb
Host smart-688b2d52-fb5c-4818-8c9e-63138b094e54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153929853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.4153929853
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2966089821
Short name T498
Test name
Test status
Simulation time 287206173 ps
CPU time 1.27 seconds
Started Jan 21 03:53:08 PM PST 24
Finished Jan 21 03:53:12 PM PST 24
Peak memory 200852 kb
Host smart-fa3b5a7e-e7cc-4655-8252-11c8f9a42f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966089821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2966089821
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1681112212
Short name T211
Test name
Test status
Simulation time 493777256639 ps
CPU time 334.3 seconds
Started Jan 21 03:52:59 PM PST 24
Finished Jan 21 03:58:34 PM PST 24
Peak memory 201272 kb
Host smart-0afc7492-91e3-457e-8201-df09540a266f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681112212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1681112212
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.4290168977
Short name T639
Test name
Test status
Simulation time 493364543731 ps
CPU time 1165.96 seconds
Started Jan 21 03:53:02 PM PST 24
Finished Jan 21 04:12:32 PM PST 24
Peak memory 201144 kb
Host smart-1fbdbe67-b2f0-4b00-a4d6-095f90298c82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290168977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.4290168977
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3783295365
Short name T629
Test name
Test status
Simulation time 328895228912 ps
CPU time 789.3 seconds
Started Jan 21 03:52:58 PM PST 24
Finished Jan 21 04:06:09 PM PST 24
Peak memory 201208 kb
Host smart-c0d4bc65-39c5-490f-8259-cd77b8d8b507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783295365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3783295365
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1096216423
Short name T551
Test name
Test status
Simulation time 492070423405 ps
CPU time 295.27 seconds
Started Jan 21 03:52:57 PM PST 24
Finished Jan 21 03:57:54 PM PST 24
Peak memory 201284 kb
Host smart-97bdf4fc-b849-4893-aac0-4aa56cd9e0a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096216423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1096216423
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2388753866
Short name T286
Test name
Test status
Simulation time 163006625588 ps
CPU time 37.31 seconds
Started Jan 21 04:28:44 PM PST 24
Finished Jan 21 04:29:22 PM PST 24
Peak memory 201196 kb
Host smart-e0bda8e5-aac8-4de6-aa15-4c669a55ed7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388753866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2388753866
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2985243456
Short name T782
Test name
Test status
Simulation time 495889672772 ps
CPU time 1264.97 seconds
Started Jan 21 07:23:51 PM PST 24
Finished Jan 21 07:44:57 PM PST 24
Peak memory 201200 kb
Host smart-65ae8eb8-36a4-493b-91e5-1fbba6fc7849
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985243456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2985243456
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1337030387
Short name T33
Test name
Test status
Simulation time 114568133333 ps
CPU time 574.61 seconds
Started Jan 21 03:53:07 PM PST 24
Finished Jan 21 04:02:44 PM PST 24
Peak memory 201476 kb
Host smart-2234362a-8046-40ca-b8a4-4504a243192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337030387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1337030387
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3606556846
Short name T721
Test name
Test status
Simulation time 29672360480 ps
CPU time 65.79 seconds
Started Jan 21 03:53:08 PM PST 24
Finished Jan 21 03:54:16 PM PST 24
Peak memory 200936 kb
Host smart-7abf0d39-3d51-436d-bcfa-41f1eb92ba28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606556846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3606556846
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1111003735
Short name T567
Test name
Test status
Simulation time 5314364044 ps
CPU time 6.55 seconds
Started Jan 21 03:53:08 PM PST 24
Finished Jan 21 03:53:17 PM PST 24
Peak memory 200952 kb
Host smart-ca964c0f-a353-4f3e-bddb-2051dc9c6221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111003735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1111003735
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1842606923
Short name T589
Test name
Test status
Simulation time 5705232863 ps
CPU time 4.02 seconds
Started Jan 21 03:52:54 PM PST 24
Finished Jan 21 03:52:59 PM PST 24
Peak memory 201064 kb
Host smart-3416c726-2b38-486e-8d42-aca318fb0ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842606923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1842606923
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1190994603
Short name T712
Test name
Test status
Simulation time 1015674991 ps
CPU time 3 seconds
Started Jan 21 03:53:08 PM PST 24
Finished Jan 21 03:53:13 PM PST 24
Peak memory 200936 kb
Host smart-4692da28-4ce6-4a73-8ce5-9c79427df9c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190994603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1190994603
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.201963415
Short name T130
Test name
Test status
Simulation time 479907119660 ps
CPU time 346.02 seconds
Started Jan 21 03:53:10 PM PST 24
Finished Jan 21 03:58:57 PM PST 24
Peak memory 209808 kb
Host smart-e5a77425-df05-4922-bde9-1df80a318031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201963415 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.201963415
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.176096459
Short name T716
Test name
Test status
Simulation time 590767774 ps
CPU time 0.72 seconds
Started Jan 21 03:53:35 PM PST 24
Finished Jan 21 03:53:39 PM PST 24
Peak memory 200968 kb
Host smart-19e6265b-de67-4b48-921d-102c2484f785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176096459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.176096459
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1587194226
Short name T243
Test name
Test status
Simulation time 325268867253 ps
CPU time 698.58 seconds
Started Jan 21 03:53:26 PM PST 24
Finished Jan 21 04:05:06 PM PST 24
Peak memory 201120 kb
Host smart-9f39ce57-f13f-40f5-951d-fcb0af7209fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587194226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1587194226
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.705405770
Short name T117
Test name
Test status
Simulation time 491174747107 ps
CPU time 271.22 seconds
Started Jan 21 03:53:29 PM PST 24
Finished Jan 21 03:58:01 PM PST 24
Peak memory 200156 kb
Host smart-4143d89a-c26a-42fe-8c6b-f0266acc9fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705405770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.705405770
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1148255615
Short name T104
Test name
Test status
Simulation time 328196310156 ps
CPU time 106.92 seconds
Started Jan 21 03:53:09 PM PST 24
Finished Jan 21 03:54:57 PM PST 24
Peak memory 201120 kb
Host smart-ba9a451c-9bf0-426a-817e-6daba3c8343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148255615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1148255615
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3398083751
Short name T446
Test name
Test status
Simulation time 327677069753 ps
CPU time 382.28 seconds
Started Jan 21 03:53:16 PM PST 24
Finished Jan 21 03:59:40 PM PST 24
Peak memory 201124 kb
Host smart-73fb8baf-94a9-4f7d-870d-18a33e4d6bdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398083751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3398083751
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1004578062
Short name T247
Test name
Test status
Simulation time 327687850781 ps
CPU time 770.57 seconds
Started Jan 21 03:53:07 PM PST 24
Finished Jan 21 04:06:00 PM PST 24
Peak memory 201220 kb
Host smart-ea9e3cd9-3ada-45f0-9780-04a83140a954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004578062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1004578062
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2964230311
Short name T136
Test name
Test status
Simulation time 165157481744 ps
CPU time 99.12 seconds
Started Jan 21 03:53:07 PM PST 24
Finished Jan 21 03:54:49 PM PST 24
Peak memory 201184 kb
Host smart-b555454b-813c-4ddc-b548-4eaa8934dc78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964230311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2964230311
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.331224191
Short name T306
Test name
Test status
Simulation time 329045666702 ps
CPU time 356.05 seconds
Started Jan 21 03:53:19 PM PST 24
Finished Jan 21 03:59:16 PM PST 24
Peak memory 201240 kb
Host smart-79a66bfc-18c7-4e10-a7f5-51a4de22a6ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331224191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.331224191
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2254611381
Short name T507
Test name
Test status
Simulation time 327002622487 ps
CPU time 195.91 seconds
Started Jan 21 03:53:18 PM PST 24
Finished Jan 21 03:56:35 PM PST 24
Peak memory 201212 kb
Host smart-b08dbc4c-e880-481b-866e-3bbb0e9f7762
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254611381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2254611381
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.95151334
Short name T34
Test name
Test status
Simulation time 63015260871 ps
CPU time 290.77 seconds
Started Jan 21 03:53:33 PM PST 24
Finished Jan 21 03:58:29 PM PST 24
Peak memory 201428 kb
Host smart-b115bd9a-8b4d-4dd9-b2e6-b2b1fe66a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95151334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.95151334
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.813862615
Short name T17
Test name
Test status
Simulation time 28212440816 ps
CPU time 65.39 seconds
Started Jan 21 03:53:29 PM PST 24
Finished Jan 21 03:54:35 PM PST 24
Peak memory 199800 kb
Host smart-1a893b2a-5223-4aea-bf25-082048e1124a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813862615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.813862615
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1746521150
Short name T771
Test name
Test status
Simulation time 4672966976 ps
CPU time 3.41 seconds
Started Jan 21 03:53:27 PM PST 24
Finished Jan 21 03:53:32 PM PST 24
Peak memory 201036 kb
Host smart-516e91bc-302c-4225-80f2-f0e76a55017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746521150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1746521150
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3766327973
Short name T693
Test name
Test status
Simulation time 5717886864 ps
CPU time 13.92 seconds
Started Jan 21 03:53:10 PM PST 24
Finished Jan 21 03:53:25 PM PST 24
Peak memory 200968 kb
Host smart-03e93c28-4da8-4d6a-a90f-921988b0c47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766327973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3766327973
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2741089587
Short name T728
Test name
Test status
Simulation time 257779672762 ps
CPU time 582.05 seconds
Started Jan 21 03:53:33 PM PST 24
Finished Jan 21 04:03:21 PM PST 24
Peak memory 201196 kb
Host smart-ad1f6076-ecc9-454d-be04-228094a1aab6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741089587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2741089587
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1940359696
Short name T187
Test name
Test status
Simulation time 296766019449 ps
CPU time 258.73 seconds
Started Jan 21 03:53:33 PM PST 24
Finished Jan 21 03:57:57 PM PST 24
Peak memory 209720 kb
Host smart-2ba0166a-fa41-44b1-ae88-9d8903ec3fec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940359696 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1940359696
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1168707445
Short name T831
Test name
Test status
Simulation time 474175970 ps
CPU time 1.65 seconds
Started Jan 21 03:53:52 PM PST 24
Finished Jan 21 03:53:55 PM PST 24
Peak memory 200908 kb
Host smart-90a404a9-31ae-457b-9f2a-261687681c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168707445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1168707445
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2455043930
Short name T736
Test name
Test status
Simulation time 164514689304 ps
CPU time 119.8 seconds
Started Jan 21 03:53:46 PM PST 24
Finished Jan 21 03:55:46 PM PST 24
Peak memory 201088 kb
Host smart-b0bd15d7-0c2b-4989-bc70-d3d14e8650ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455043930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2455043930
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.646441696
Short name T252
Test name
Test status
Simulation time 167481938926 ps
CPU time 383.31 seconds
Started Jan 21 03:53:49 PM PST 24
Finished Jan 21 04:00:13 PM PST 24
Peak memory 201220 kb
Host smart-9b788e9d-e7e6-41c5-a327-dab443ada8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646441696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.646441696
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2205815230
Short name T826
Test name
Test status
Simulation time 339284929374 ps
CPU time 361.52 seconds
Started Jan 21 03:53:35 PM PST 24
Finished Jan 21 03:59:40 PM PST 24
Peak memory 201172 kb
Host smart-12515f16-59fe-421e-8d07-d59433073f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205815230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2205815230
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3014208154
Short name T572
Test name
Test status
Simulation time 320372832395 ps
CPU time 770.22 seconds
Started Jan 21 03:53:35 PM PST 24
Finished Jan 21 04:06:29 PM PST 24
Peak memory 201168 kb
Host smart-e60ee31f-3453-4d83-9c45-51d0a269ef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014208154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3014208154
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.761593156
Short name T448
Test name
Test status
Simulation time 160024396681 ps
CPU time 115.52 seconds
Started Jan 21 03:53:32 PM PST 24
Finished Jan 21 03:55:34 PM PST 24
Peak memory 201224 kb
Host smart-23cd5e13-4402-4c9d-b440-ba2e20e7e194
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=761593156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.761593156
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2542732333
Short name T147
Test name
Test status
Simulation time 163935632619 ps
CPU time 342.32 seconds
Started Jan 21 03:53:48 PM PST 24
Finished Jan 21 03:59:32 PM PST 24
Peak memory 201216 kb
Host smart-7d4cc52d-8c44-4232-ba12-689ed0328338
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542732333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2542732333
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1004333407
Short name T502
Test name
Test status
Simulation time 494551138477 ps
CPU time 1178.3 seconds
Started Jan 21 03:53:48 PM PST 24
Finished Jan 21 04:13:27 PM PST 24
Peak memory 201196 kb
Host smart-1f2d5f41-1064-4e27-8c38-89a016dc417d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004333407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1004333407
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3606054194
Short name T346
Test name
Test status
Simulation time 106352475142 ps
CPU time 388.24 seconds
Started Jan 21 03:53:48 PM PST 24
Finished Jan 21 04:00:17 PM PST 24
Peak memory 201468 kb
Host smart-62825d30-57ca-4ea0-8ab5-908361454161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606054194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3606054194
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1494917188
Short name T410
Test name
Test status
Simulation time 24700692540 ps
CPU time 43.3 seconds
Started Jan 21 03:53:47 PM PST 24
Finished Jan 21 03:54:31 PM PST 24
Peak memory 201040 kb
Host smart-2c3481b5-7e77-4800-b079-feb489cc5df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494917188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1494917188
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2534003688
Short name T44
Test name
Test status
Simulation time 3336140132 ps
CPU time 2.62 seconds
Started Jan 21 03:53:48 PM PST 24
Finished Jan 21 03:53:52 PM PST 24
Peak memory 201016 kb
Host smart-562b8666-e9b3-46af-a28d-cda4d3ca3c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534003688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2534003688
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1205540237
Short name T88
Test name
Test status
Simulation time 5495559018 ps
CPU time 12.77 seconds
Started Jan 21 03:53:34 PM PST 24
Finished Jan 21 03:53:51 PM PST 24
Peak memory 200988 kb
Host smart-010da567-3e35-48dd-bd23-e79969e7b66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205540237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1205540237
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1889586596
Short name T730
Test name
Test status
Simulation time 264779701752 ps
CPU time 604.12 seconds
Started Jan 21 03:53:48 PM PST 24
Finished Jan 21 04:03:53 PM PST 24
Peak memory 201516 kb
Host smart-e10fe09b-a512-4d2f-bb9d-310a2fa6f81b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889586596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1889586596
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.301534305
Short name T268
Test name
Test status
Simulation time 261563856327 ps
CPU time 109.25 seconds
Started Jan 21 03:53:48 PM PST 24
Finished Jan 21 03:55:38 PM PST 24
Peak memory 209420 kb
Host smart-93d90e84-837b-4cb4-b598-a4c096659e08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301534305 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.301534305
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.259145598
Short name T791
Test name
Test status
Simulation time 314461488 ps
CPU time 0.85 seconds
Started Jan 21 03:54:04 PM PST 24
Finished Jan 21 03:54:05 PM PST 24
Peak memory 200668 kb
Host smart-d4fabd34-5c6e-4847-b33a-a4a7dd47ab66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259145598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.259145598
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.4237735192
Short name T766
Test name
Test status
Simulation time 165776859962 ps
CPU time 81.57 seconds
Started Jan 21 03:53:58 PM PST 24
Finished Jan 21 03:55:21 PM PST 24
Peak memory 201252 kb
Host smart-6de64de7-3aa3-40c0-aa43-4554f132ec4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237735192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.4237735192
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2494790727
Short name T696
Test name
Test status
Simulation time 504393468746 ps
CPU time 306.06 seconds
Started Jan 21 03:53:52 PM PST 24
Finished Jan 21 03:58:59 PM PST 24
Peak memory 201188 kb
Host smart-1daf32b1-2331-4267-8883-922a880bb754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494790727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2494790727
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.705166442
Short name T450
Test name
Test status
Simulation time 329732429146 ps
CPU time 788.51 seconds
Started Jan 21 03:53:53 PM PST 24
Finished Jan 21 04:07:02 PM PST 24
Peak memory 201044 kb
Host smart-115a5e73-265c-460f-bd73-834b981cdb56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=705166442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.705166442
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.555188601
Short name T525
Test name
Test status
Simulation time 487327652161 ps
CPU time 307.91 seconds
Started Jan 21 03:53:56 PM PST 24
Finished Jan 21 03:59:05 PM PST 24
Peak memory 201160 kb
Host smart-ae310c55-d189-402a-a1fc-c11c223c9845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555188601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.555188601
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1219471073
Short name T436
Test name
Test status
Simulation time 488433647971 ps
CPU time 363.95 seconds
Started Jan 21 03:53:54 PM PST 24
Finished Jan 21 03:59:59 PM PST 24
Peak memory 201100 kb
Host smart-d89816c7-4cee-408d-837e-80cbeb0f181f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219471073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1219471073
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3084326114
Short name T812
Test name
Test status
Simulation time 161747302006 ps
CPU time 387.42 seconds
Started Jan 21 03:53:56 PM PST 24
Finished Jan 21 04:00:24 PM PST 24
Peak memory 201136 kb
Host smart-c3529689-1c6e-4491-b5a8-4b4d6b9e52a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084326114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3084326114
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.59366797
Short name T462
Test name
Test status
Simulation time 488884227024 ps
CPU time 283.52 seconds
Started Jan 21 03:53:56 PM PST 24
Finished Jan 21 03:58:41 PM PST 24
Peak memory 201076 kb
Host smart-8ff4092d-14ef-49b5-9230-32c351359e96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59366797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.a
dc_ctrl_filters_wakeup_fixed.59366797
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2767514797
Short name T814
Test name
Test status
Simulation time 99444087612 ps
CPU time 403.91 seconds
Started Jan 21 03:54:05 PM PST 24
Finished Jan 21 04:00:50 PM PST 24
Peak memory 201384 kb
Host smart-43e928aa-dcad-485d-8b35-6ad00a83b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767514797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2767514797
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1919952198
Short name T803
Test name
Test status
Simulation time 46999682358 ps
CPU time 9.63 seconds
Started Jan 21 03:54:06 PM PST 24
Finished Jan 21 03:54:17 PM PST 24
Peak memory 201012 kb
Host smart-6d469584-cff8-4010-a002-31fd66d43c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919952198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1919952198
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1356726771
Short name T543
Test name
Test status
Simulation time 3793782107 ps
CPU time 2.41 seconds
Started Jan 21 04:00:25 PM PST 24
Finished Jan 21 04:00:29 PM PST 24
Peak memory 201068 kb
Host smart-7f42e78c-ff94-4da0-b652-2d13f7d0532f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356726771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1356726771
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.73275148
Short name T671
Test name
Test status
Simulation time 5795019171 ps
CPU time 3.75 seconds
Started Jan 21 03:53:54 PM PST 24
Finished Jan 21 03:53:58 PM PST 24
Peak memory 200980 kb
Host smart-e0e22f93-f31d-4d71-a13f-0c9bc9ec5b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73275148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.73275148
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2565625651
Short name T310
Test name
Test status
Simulation time 506293561765 ps
CPU time 631.73 seconds
Started Jan 21 03:54:05 PM PST 24
Finished Jan 21 04:04:38 PM PST 24
Peak memory 209680 kb
Host smart-72016d8d-e3c8-49ad-a98b-f5d20ac1c219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565625651 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2565625651
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.924364908
Short name T610
Test name
Test status
Simulation time 469702510 ps
CPU time 0.85 seconds
Started Jan 21 03:54:27 PM PST 24
Finished Jan 21 03:54:28 PM PST 24
Peak memory 200884 kb
Host smart-cad1eff2-7ae3-4330-b81e-d7edb7e3c528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924364908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.924364908
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3557795524
Short name T143
Test name
Test status
Simulation time 329236709367 ps
CPU time 47.1 seconds
Started Jan 21 05:35:41 PM PST 24
Finished Jan 21 05:36:36 PM PST 24
Peak memory 201168 kb
Host smart-42d34974-72b0-4d4d-a18e-0bd995184a2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557795524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3557795524
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3595323286
Short name T619
Test name
Test status
Simulation time 161260827218 ps
CPU time 62.69 seconds
Started Jan 21 03:54:11 PM PST 24
Finished Jan 21 03:55:14 PM PST 24
Peak memory 201168 kb
Host smart-1b710c6f-d324-4a02-955b-395266f8367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595323286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3595323286
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.781292307
Short name T434
Test name
Test status
Simulation time 165959100303 ps
CPU time 402.11 seconds
Started Jan 21 03:54:07 PM PST 24
Finished Jan 21 04:00:50 PM PST 24
Peak memory 201192 kb
Host smart-d35170d5-ef48-4f21-a3b6-35e9d53578a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=781292307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.781292307
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.4149520909
Short name T779
Test name
Test status
Simulation time 164177610327 ps
CPU time 380.47 seconds
Started Jan 21 03:54:04 PM PST 24
Finished Jan 21 04:00:26 PM PST 24
Peak memory 201224 kb
Host smart-ad6a16a5-cb23-44d4-a8c5-9de2e00a5f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149520909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.4149520909
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.747000935
Short name T787
Test name
Test status
Simulation time 335027777841 ps
CPU time 774.99 seconds
Started Jan 21 03:54:11 PM PST 24
Finished Jan 21 04:07:07 PM PST 24
Peak memory 201156 kb
Host smart-90574071-9a5b-41f5-aa58-472d5d865c3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=747000935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.747000935
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1529268381
Short name T222
Test name
Test status
Simulation time 495884036998 ps
CPU time 300.99 seconds
Started Jan 21 03:54:09 PM PST 24
Finished Jan 21 03:59:10 PM PST 24
Peak memory 201224 kb
Host smart-039fc25a-e1ea-40d7-a29d-3336e83c5395
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529268381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1529268381
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2078195538
Short name T709
Test name
Test status
Simulation time 334363411455 ps
CPU time 264.36 seconds
Started Jan 21 03:54:08 PM PST 24
Finished Jan 21 03:58:33 PM PST 24
Peak memory 201188 kb
Host smart-c29ca160-8eb6-447a-92d3-e323833deb93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078195538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2078195538
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3650273436
Short name T845
Test name
Test status
Simulation time 130015019871 ps
CPU time 516.68 seconds
Started Jan 21 03:54:23 PM PST 24
Finished Jan 21 04:03:01 PM PST 24
Peak memory 201496 kb
Host smart-47bd1bb2-2622-4627-a4c1-f0bbb40c6707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650273436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3650273436
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2468108037
Short name T753
Test name
Test status
Simulation time 5145554975 ps
CPU time 3.3 seconds
Started Jan 21 03:54:18 PM PST 24
Finished Jan 21 03:54:22 PM PST 24
Peak memory 201036 kb
Host smart-4b060908-1bf2-43a3-9ca2-40547ba17cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468108037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2468108037
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2124990670
Short name T85
Test name
Test status
Simulation time 6069281707 ps
CPU time 3.13 seconds
Started Jan 21 03:54:04 PM PST 24
Finished Jan 21 03:54:08 PM PST 24
Peak memory 201040 kb
Host smart-a12e1145-6375-417b-bf28-8a1e933e7972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124990670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2124990670
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1792619032
Short name T122
Test name
Test status
Simulation time 169418977509 ps
CPU time 24.08 seconds
Started Jan 21 03:54:24 PM PST 24
Finished Jan 21 03:54:49 PM PST 24
Peak memory 201260 kb
Host smart-dfa0f65a-e98c-4e38-8191-d02f837c65d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792619032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1792619032
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2059034081
Short name T317
Test name
Test status
Simulation time 78339062796 ps
CPU time 147.62 seconds
Started Jan 21 03:54:25 PM PST 24
Finished Jan 21 03:56:53 PM PST 24
Peak memory 209760 kb
Host smart-d48a314e-9fd4-4ea9-a9e8-32d8131c7037
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059034081 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2059034081
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2859221569
Short name T452
Test name
Test status
Simulation time 434195627 ps
CPU time 1.57 seconds
Started Jan 21 03:54:43 PM PST 24
Finished Jan 21 03:54:45 PM PST 24
Peak memory 200924 kb
Host smart-7b04f49c-f20f-4224-8c57-74b6d5c9fb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859221569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2859221569
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2478528642
Short name T204
Test name
Test status
Simulation time 503799830575 ps
CPU time 519.99 seconds
Started Jan 21 03:54:32 PM PST 24
Finished Jan 21 04:03:13 PM PST 24
Peak memory 201284 kb
Host smart-1ab80f5d-3633-4e7d-922d-0bd28e2af70d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478528642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2478528642
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.188025867
Short name T203
Test name
Test status
Simulation time 517615495850 ps
CPU time 545.48 seconds
Started Jan 21 03:54:32 PM PST 24
Finished Jan 21 04:03:38 PM PST 24
Peak memory 201236 kb
Host smart-8f1ca361-02a9-4612-94db-6a4b056d57a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188025867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.188025867
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3748302870
Short name T664
Test name
Test status
Simulation time 159926092662 ps
CPU time 380.69 seconds
Started Jan 21 03:54:33 PM PST 24
Finished Jan 21 04:00:55 PM PST 24
Peak memory 201144 kb
Host smart-e0db714a-7860-4591-887f-7338140b8426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748302870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3748302870
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.940572541
Short name T521
Test name
Test status
Simulation time 156335993677 ps
CPU time 365.28 seconds
Started Jan 21 03:54:34 PM PST 24
Finished Jan 21 04:00:40 PM PST 24
Peak memory 201164 kb
Host smart-6de27b26-f3f0-4722-9969-897dd51d3bba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=940572541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.940572541
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.849578151
Short name T94
Test name
Test status
Simulation time 325129431471 ps
CPU time 714.88 seconds
Started Jan 21 03:54:32 PM PST 24
Finished Jan 21 04:06:27 PM PST 24
Peak memory 201172 kb
Host smart-fdbd1d9b-da45-4d43-aa8b-428ab4c81b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849578151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.849578151
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3634710919
Short name T471
Test name
Test status
Simulation time 338015821059 ps
CPU time 908.34 seconds
Started Jan 21 04:56:09 PM PST 24
Finished Jan 21 05:11:19 PM PST 24
Peak memory 201172 kb
Host smart-35797a46-f4cc-44cb-8e40-1ef89ba03f55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634710919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3634710919
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3668156152
Short name T703
Test name
Test status
Simulation time 339572197068 ps
CPU time 56.64 seconds
Started Jan 21 03:54:33 PM PST 24
Finished Jan 21 03:55:31 PM PST 24
Peak memory 201160 kb
Host smart-6c1fd2f2-735b-4aed-9dec-64b3991686ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668156152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3668156152
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1737091877
Short name T531
Test name
Test status
Simulation time 333084444257 ps
CPU time 400.33 seconds
Started Jan 21 03:54:33 PM PST 24
Finished Jan 21 04:01:15 PM PST 24
Peak memory 201208 kb
Host smart-189022e4-e1ca-43a9-a9f2-fe9c04e724b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737091877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1737091877
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2645975928
Short name T193
Test name
Test status
Simulation time 82746602732 ps
CPU time 429.13 seconds
Started Jan 21 03:54:44 PM PST 24
Finished Jan 21 04:01:54 PM PST 24
Peak memory 201416 kb
Host smart-9d0ccd5e-ccf5-4ca3-a993-f508c0480785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645975928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2645975928
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3796972887
Short name T770
Test name
Test status
Simulation time 30957020844 ps
CPU time 67.78 seconds
Started Jan 21 03:54:45 PM PST 24
Finished Jan 21 03:55:54 PM PST 24
Peak memory 201028 kb
Host smart-cb28fde2-758b-4335-a935-a6084a57d223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796972887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3796972887
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.552133774
Short name T798
Test name
Test status
Simulation time 4759015373 ps
CPU time 5.11 seconds
Started Jan 21 03:54:46 PM PST 24
Finished Jan 21 03:54:52 PM PST 24
Peak memory 201024 kb
Host smart-8d824457-057c-450b-80cc-f4ff40ea4ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552133774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.552133774
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.392018509
Short name T466
Test name
Test status
Simulation time 5788711657 ps
CPU time 1.87 seconds
Started Jan 21 03:54:32 PM PST 24
Finished Jan 21 03:54:35 PM PST 24
Peak memory 200976 kb
Host smart-cb3de99b-9db3-4f55-9f2d-db3d1effce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392018509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.392018509
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3697449148
Short name T582
Test name
Test status
Simulation time 168911972760 ps
CPU time 97.46 seconds
Started Jan 21 03:54:44 PM PST 24
Finished Jan 21 03:56:22 PM PST 24
Peak memory 201144 kb
Host smart-98fa8e04-6c50-4b0a-ad84-9050572b3d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697449148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3697449148
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3319323699
Short name T12
Test name
Test status
Simulation time 219757540333 ps
CPU time 106.87 seconds
Started Jan 21 03:54:49 PM PST 24
Finished Jan 21 03:56:37 PM PST 24
Peak memory 201176 kb
Host smart-61b5168f-f909-43dc-93a1-c1ec5aaf93ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319323699 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3319323699
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1484026210
Short name T598
Test name
Test status
Simulation time 410203964 ps
CPU time 1.52 seconds
Started Jan 21 03:55:02 PM PST 24
Finished Jan 21 03:55:04 PM PST 24
Peak memory 200948 kb
Host smart-8a286ff0-b228-49c5-97b0-b1f4e259445e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484026210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1484026210
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3359649874
Short name T300
Test name
Test status
Simulation time 169963966966 ps
CPU time 185.36 seconds
Started Jan 21 03:54:50 PM PST 24
Finished Jan 21 03:57:56 PM PST 24
Peak memory 201228 kb
Host smart-d5ef3f14-9b0c-46a0-bef2-8d6ccbc5ba7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359649874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3359649874
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3648815429
Short name T781
Test name
Test status
Simulation time 168298493712 ps
CPU time 189.28 seconds
Started Jan 21 03:54:49 PM PST 24
Finished Jan 21 03:58:00 PM PST 24
Peak memory 201144 kb
Host smart-0d95ff34-e162-4b38-877b-f5692b10edf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648815429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3648815429
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3676430793
Short name T430
Test name
Test status
Simulation time 328285393702 ps
CPU time 183.08 seconds
Started Jan 21 03:54:46 PM PST 24
Finished Jan 21 03:57:50 PM PST 24
Peak memory 201160 kb
Host smart-b9c97103-62ae-4a66-837a-ef48b35ada8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676430793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3676430793
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.191103085
Short name T307
Test name
Test status
Simulation time 485798287825 ps
CPU time 583.27 seconds
Started Jan 21 03:54:45 PM PST 24
Finished Jan 21 04:04:29 PM PST 24
Peak memory 201176 kb
Host smart-f6e104c3-3552-422d-a37a-53ecbdcc5d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191103085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.191103085
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2224015980
Short name T412
Test name
Test status
Simulation time 328736783552 ps
CPU time 394.45 seconds
Started Jan 21 03:54:49 PM PST 24
Finished Jan 21 04:01:25 PM PST 24
Peak memory 201140 kb
Host smart-76321a7d-97c9-43c5-bf30-aa43957158ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224015980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2224015980
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2689316687
Short name T293
Test name
Test status
Simulation time 491373748653 ps
CPU time 818.42 seconds
Started Jan 21 03:54:49 PM PST 24
Finished Jan 21 04:08:29 PM PST 24
Peak memory 201220 kb
Host smart-7508352a-ef5b-4bea-a322-f27dbaa125a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689316687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2689316687
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2266315010
Short name T461
Test name
Test status
Simulation time 329158110071 ps
CPU time 742.41 seconds
Started Jan 21 03:54:47 PM PST 24
Finished Jan 21 04:07:10 PM PST 24
Peak memory 201120 kb
Host smart-9e0d33aa-5cb9-40f2-88f6-85bb31580337
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266315010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2266315010
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3571690981
Short name T189
Test name
Test status
Simulation time 126061131733 ps
CPU time 423.74 seconds
Started Jan 21 03:54:59 PM PST 24
Finished Jan 21 04:02:04 PM PST 24
Peak memory 201316 kb
Host smart-a1b5763d-2722-427b-b16a-f26072851f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571690981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3571690981
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3914195406
Short name T504
Test name
Test status
Simulation time 35441817467 ps
CPU time 82.38 seconds
Started Jan 21 03:54:59 PM PST 24
Finished Jan 21 03:56:22 PM PST 24
Peak memory 201008 kb
Host smart-5354cf90-9460-4301-963d-6691a6ee95d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914195406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3914195406
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2611741067
Short name T819
Test name
Test status
Simulation time 4906833195 ps
CPU time 8.82 seconds
Started Jan 21 03:54:52 PM PST 24
Finished Jan 21 03:55:01 PM PST 24
Peak memory 201236 kb
Host smart-0af716a6-dbf4-4db4-a5c2-9191194832e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611741067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2611741067
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1959493509
Short name T842
Test name
Test status
Simulation time 5701598053 ps
CPU time 13.41 seconds
Started Jan 21 03:54:44 PM PST 24
Finished Jan 21 03:54:58 PM PST 24
Peak memory 200960 kb
Host smart-7a79205b-3301-4e28-8e52-731e9030a5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959493509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1959493509
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2329628594
Short name T328
Test name
Test status
Simulation time 209837560529 ps
CPU time 232.81 seconds
Started Jan 21 03:55:03 PM PST 24
Finished Jan 21 03:58:56 PM PST 24
Peak memory 201172 kb
Host smart-dc420a08-8cbe-4086-b867-42e7c1a1c90b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329628594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2329628594
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2343409023
Short name T681
Test name
Test status
Simulation time 43063168054 ps
CPU time 65.49 seconds
Started Jan 21 03:55:02 PM PST 24
Finished Jan 21 03:56:08 PM PST 24
Peak memory 209872 kb
Host smart-803ff4ac-7b34-4b4a-b378-fd71b7046241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343409023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2343409023
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1307640381
Short name T415
Test name
Test status
Simulation time 312384046 ps
CPU time 0.84 seconds
Started Jan 21 03:55:13 PM PST 24
Finished Jan 21 03:55:17 PM PST 24
Peak memory 200988 kb
Host smart-5c919fec-8224-43c9-bc6a-29789ce135a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307640381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1307640381
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1204690341
Short name T163
Test name
Test status
Simulation time 165868384394 ps
CPU time 142.93 seconds
Started Jan 21 03:55:03 PM PST 24
Finished Jan 21 03:57:27 PM PST 24
Peak memory 201196 kb
Host smart-7790d8e0-1bad-490e-98db-c57b3ebde790
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204690341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1204690341
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.669463450
Short name T327
Test name
Test status
Simulation time 159356404472 ps
CPU time 88.95 seconds
Started Jan 21 03:55:09 PM PST 24
Finished Jan 21 03:56:45 PM PST 24
Peak memory 201208 kb
Host smart-1620234f-b6d7-4fb2-a095-35d9e9bd8d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669463450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.669463450
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1405359271
Short name T849
Test name
Test status
Simulation time 497763689367 ps
CPU time 540.2 seconds
Started Jan 21 05:45:23 PM PST 24
Finished Jan 21 05:54:24 PM PST 24
Peak memory 201272 kb
Host smart-b484c367-b258-4765-a837-91358b7782eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405359271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1405359271
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.920434976
Short name T726
Test name
Test status
Simulation time 485979565666 ps
CPU time 710.07 seconds
Started Jan 21 03:55:02 PM PST 24
Finished Jan 21 04:06:53 PM PST 24
Peak memory 201180 kb
Host smart-21232b68-234a-4b43-8fcc-c1cb23a5ae8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=920434976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.920434976
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2301834591
Short name T129
Test name
Test status
Simulation time 494564143024 ps
CPU time 1173.26 seconds
Started Jan 21 05:18:26 PM PST 24
Finished Jan 21 05:38:01 PM PST 24
Peak memory 201272 kb
Host smart-8fda455a-f4a6-4cb2-8817-7d29dad3faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301834591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2301834591
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3511713739
Short name T679
Test name
Test status
Simulation time 160370857673 ps
CPU time 349.53 seconds
Started Jan 21 03:55:03 PM PST 24
Finished Jan 21 04:00:53 PM PST 24
Peak memory 201092 kb
Host smart-76464b3c-ee28-4999-af0a-ad7885bbc72d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511713739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3511713739
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2439999073
Short name T683
Test name
Test status
Simulation time 168070894809 ps
CPU time 102.47 seconds
Started Jan 21 03:55:04 PM PST 24
Finished Jan 21 03:56:48 PM PST 24
Peak memory 201172 kb
Host smart-35d58bf8-2d38-46d7-bda7-10d070c7e5cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439999073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2439999073
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3522198207
Short name T755
Test name
Test status
Simulation time 104296572250 ps
CPU time 344.86 seconds
Started Jan 21 03:55:15 PM PST 24
Finished Jan 21 04:01:02 PM PST 24
Peak memory 201464 kb
Host smart-c571819d-b6ff-4984-ac7c-985c941c5d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522198207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3522198207
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.875632336
Short name T625
Test name
Test status
Simulation time 48565733514 ps
CPU time 96.12 seconds
Started Jan 21 03:55:12 PM PST 24
Finished Jan 21 03:56:52 PM PST 24
Peak memory 201016 kb
Host smart-2a55556e-81b8-4814-992a-926bbc2f20d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875632336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.875632336
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2205706715
Short name T827
Test name
Test status
Simulation time 3939620489 ps
CPU time 2.17 seconds
Started Jan 21 03:55:13 PM PST 24
Finished Jan 21 03:55:18 PM PST 24
Peak memory 201036 kb
Host smart-83743b7a-05fb-4dc7-be06-1ce2ce0f608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205706715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2205706715
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1780362961
Short name T815
Test name
Test status
Simulation time 5870922494 ps
CPU time 4.2 seconds
Started Jan 21 03:55:09 PM PST 24
Finished Jan 21 03:55:20 PM PST 24
Peak memory 201008 kb
Host smart-8eb330c3-c7d8-43f3-b13b-bc506f0379a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780362961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1780362961
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3250005889
Short name T280
Test name
Test status
Simulation time 328209681704 ps
CPU time 728.11 seconds
Started Jan 21 03:55:13 PM PST 24
Finished Jan 21 04:07:24 PM PST 24
Peak memory 201200 kb
Host smart-578ee2a9-fe09-4a0c-bfa7-576b37ed25d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250005889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3250005889
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3836917090
Short name T777
Test name
Test status
Simulation time 361261244 ps
CPU time 1.47 seconds
Started Jan 21 03:55:24 PM PST 24
Finished Jan 21 03:55:26 PM PST 24
Peak memory 200952 kb
Host smart-c47324f9-64a6-4f81-aa80-aa9a196b7131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836917090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3836917090
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2639833355
Short name T811
Test name
Test status
Simulation time 337320165424 ps
CPU time 297.73 seconds
Started Jan 21 03:55:24 PM PST 24
Finished Jan 21 04:00:23 PM PST 24
Peak memory 201164 kb
Host smart-64878234-b048-41ea-830e-6f14a8051e13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639833355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2639833355
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3431178189
Short name T560
Test name
Test status
Simulation time 328208536348 ps
CPU time 746.73 seconds
Started Jan 21 04:36:13 PM PST 24
Finished Jan 21 04:48:40 PM PST 24
Peak memory 201140 kb
Host smart-82c8382e-6e6d-487d-a7ff-3ce1064a2b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431178189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3431178189
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2539853801
Short name T630
Test name
Test status
Simulation time 326558386160 ps
CPU time 804.71 seconds
Started Jan 21 03:55:13 PM PST 24
Finished Jan 21 04:08:41 PM PST 24
Peak memory 201160 kb
Host smart-0aba07ad-b8d3-45cd-aa6f-d4a1c809541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539853801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2539853801
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2666494265
Short name T775
Test name
Test status
Simulation time 487233963986 ps
CPU time 144.2 seconds
Started Jan 21 03:55:16 PM PST 24
Finished Jan 21 03:57:42 PM PST 24
Peak memory 201364 kb
Host smart-b7b1a101-2a91-4c84-bf4d-71f661efd533
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666494265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2666494265
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1940037821
Short name T95
Test name
Test status
Simulation time 159094874738 ps
CPU time 391 seconds
Started Jan 21 03:55:12 PM PST 24
Finished Jan 21 04:01:47 PM PST 24
Peak memory 201152 kb
Host smart-a079aa0b-6b71-41f1-b00d-b7d25ce2442d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940037821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1940037821
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3777631041
Short name T487
Test name
Test status
Simulation time 161628823855 ps
CPU time 152.06 seconds
Started Jan 21 03:55:16 PM PST 24
Finished Jan 21 03:57:50 PM PST 24
Peak memory 201436 kb
Host smart-0f07a5ca-add7-48e2-baa4-525eb13ef2c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777631041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3777631041
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2022271828
Short name T649
Test name
Test status
Simulation time 183327514766 ps
CPU time 104.66 seconds
Started Jan 21 03:55:26 PM PST 24
Finished Jan 21 03:57:11 PM PST 24
Peak memory 201136 kb
Host smart-bc0a92c5-8554-45f1-a89d-6cead7498a43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022271828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2022271828
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1717566520
Short name T496
Test name
Test status
Simulation time 325528008405 ps
CPU time 172.48 seconds
Started Jan 21 03:55:22 PM PST 24
Finished Jan 21 03:58:16 PM PST 24
Peak memory 201140 kb
Host smart-f425bc89-524b-4175-9d43-5e4e910d7b6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717566520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1717566520
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3837497796
Short name T550
Test name
Test status
Simulation time 95625905137 ps
CPU time 336.14 seconds
Started Jan 21 04:44:28 PM PST 24
Finished Jan 21 04:50:04 PM PST 24
Peak memory 201424 kb
Host smart-22257aca-71e5-440d-866b-d50cd6b65d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837497796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3837497796
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1389101038
Short name T549
Test name
Test status
Simulation time 32548926043 ps
CPU time 7.83 seconds
Started Jan 21 03:55:25 PM PST 24
Finished Jan 21 03:55:34 PM PST 24
Peak memory 201032 kb
Host smart-27451b00-3265-4f58-bbc8-64b8d7d23d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389101038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1389101038
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1242602080
Short name T548
Test name
Test status
Simulation time 5103316683 ps
CPU time 6.64 seconds
Started Jan 21 03:55:24 PM PST 24
Finished Jan 21 03:55:31 PM PST 24
Peak memory 201008 kb
Host smart-a83369d4-c6c7-4788-8364-d34d80ad17b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242602080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1242602080
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3989735712
Short name T839
Test name
Test status
Simulation time 5982171838 ps
CPU time 1.54 seconds
Started Jan 21 03:55:12 PM PST 24
Finished Jan 21 03:55:17 PM PST 24
Peak memory 200968 kb
Host smart-acee18e5-296f-47fa-be1f-47a48d557380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989735712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3989735712
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3484153633
Short name T785
Test name
Test status
Simulation time 225722851970 ps
CPU time 199.45 seconds
Started Jan 21 03:55:26 PM PST 24
Finished Jan 21 03:58:47 PM PST 24
Peak memory 209772 kb
Host smart-a747f134-287f-4815-aa10-e8ba805d9cf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484153633 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3484153633
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1278545962
Short name T701
Test name
Test status
Simulation time 515904339 ps
CPU time 0.87 seconds
Started Jan 21 03:55:44 PM PST 24
Finished Jan 21 03:55:46 PM PST 24
Peak memory 201164 kb
Host smart-9529f70c-eef3-4e96-9398-c4ad8062dc9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278545962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1278545962
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2786880096
Short name T215
Test name
Test status
Simulation time 170073782669 ps
CPU time 99.76 seconds
Started Jan 21 03:55:40 PM PST 24
Finished Jan 21 03:57:22 PM PST 24
Peak memory 201204 kb
Host smart-4352512e-c29a-4b7d-a37f-815b1ab42367
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786880096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2786880096
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2116163987
Short name T205
Test name
Test status
Simulation time 329883805837 ps
CPU time 165.05 seconds
Started Jan 21 03:55:43 PM PST 24
Finished Jan 21 03:58:29 PM PST 24
Peak memory 201188 kb
Host smart-c013c1f6-a1d2-47e8-8738-41a7814fa763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116163987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2116163987
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1071978006
Short name T338
Test name
Test status
Simulation time 498612195152 ps
CPU time 460.54 seconds
Started Jan 21 03:55:30 PM PST 24
Finished Jan 21 04:03:11 PM PST 24
Peak memory 201240 kb
Host smart-75f87082-f2a4-467f-b325-4c81befcfdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071978006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1071978006
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2016335478
Short name T49
Test name
Test status
Simulation time 165860614357 ps
CPU time 95.99 seconds
Started Jan 21 03:55:27 PM PST 24
Finished Jan 21 03:57:04 PM PST 24
Peak memory 201164 kb
Host smart-99b38a29-a0be-4867-949b-ae103277416c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016335478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2016335478
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3510458639
Short name T768
Test name
Test status
Simulation time 487535459292 ps
CPU time 274.19 seconds
Started Jan 21 03:55:30 PM PST 24
Finished Jan 21 04:00:05 PM PST 24
Peak memory 201224 kb
Host smart-66774bc5-f5b8-4207-be47-773d4e2ef533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510458639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3510458639
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1882665946
Short name T648
Test name
Test status
Simulation time 165913507660 ps
CPU time 201.17 seconds
Started Jan 21 03:55:29 PM PST 24
Finished Jan 21 03:58:50 PM PST 24
Peak memory 201264 kb
Host smart-247527c3-3dca-47c7-8b32-9e4d91070b16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882665946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1882665946
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1362367029
Short name T109
Test name
Test status
Simulation time 163700537396 ps
CPU time 97.91 seconds
Started Jan 21 03:55:30 PM PST 24
Finished Jan 21 03:57:08 PM PST 24
Peak memory 201156 kb
Host smart-add4717a-a4b0-4ab8-a730-cf5613efa4a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362367029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1362367029
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2285283918
Short name T481
Test name
Test status
Simulation time 162353221736 ps
CPU time 368.41 seconds
Started Jan 21 03:55:39 PM PST 24
Finished Jan 21 04:01:50 PM PST 24
Peak memory 201180 kb
Host smart-4767448a-a836-40ea-b6b0-9c264d1924c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285283918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2285283918
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2816083082
Short name T580
Test name
Test status
Simulation time 110533711355 ps
CPU time 384.48 seconds
Started Jan 21 03:55:37 PM PST 24
Finished Jan 21 04:02:03 PM PST 24
Peak memory 201312 kb
Host smart-8f91f96c-23bd-41fe-9f33-df4cc715b2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816083082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2816083082
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3032622945
Short name T644
Test name
Test status
Simulation time 35982022543 ps
CPU time 19.54 seconds
Started Jan 21 03:55:43 PM PST 24
Finished Jan 21 03:56:03 PM PST 24
Peak memory 200984 kb
Host smart-ce441643-94d2-4721-aa81-da73de38652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032622945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3032622945
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1242656787
Short name T824
Test name
Test status
Simulation time 4073355034 ps
CPU time 3.05 seconds
Started Jan 21 03:55:37 PM PST 24
Finished Jan 21 03:55:41 PM PST 24
Peak memory 201044 kb
Host smart-2fbc4707-7084-45c3-9341-ae7c4344b989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242656787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1242656787
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3361121774
Short name T628
Test name
Test status
Simulation time 5622840800 ps
CPU time 2.58 seconds
Started Jan 21 03:55:29 PM PST 24
Finished Jan 21 03:55:33 PM PST 24
Peak memory 201020 kb
Host smart-791cd4d3-4834-464a-a219-6de529015938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361121774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3361121774
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3943293754
Short name T717
Test name
Test status
Simulation time 34803127591 ps
CPU time 79.95 seconds
Started Jan 21 03:55:39 PM PST 24
Finished Jan 21 03:57:01 PM PST 24
Peak memory 201020 kb
Host smart-79552f17-54f5-4f10-8d9e-8c92a068511c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943293754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3943293754
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.962428306
Short name T557
Test name
Test status
Simulation time 68067037163 ps
CPU time 50.18 seconds
Started Jan 21 03:55:42 PM PST 24
Finished Jan 21 03:56:33 PM PST 24
Peak memory 209428 kb
Host smart-a82afc4f-340a-4427-9b8a-2af3d3eed2b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962428306 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.962428306
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.588062323
Short name T754
Test name
Test status
Simulation time 489244268 ps
CPU time 0.78 seconds
Started Jan 21 03:50:25 PM PST 24
Finished Jan 21 03:50:26 PM PST 24
Peak memory 200908 kb
Host smart-b7b6d80e-a233-4db1-b43d-32ef5b31366a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588062323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.588062323
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2298178978
Short name T612
Test name
Test status
Simulation time 164683175829 ps
CPU time 385.52 seconds
Started Jan 21 03:50:27 PM PST 24
Finished Jan 21 03:56:55 PM PST 24
Peak memory 201288 kb
Host smart-a27fa0fc-5411-41cb-aa97-f820453957ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298178978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2298178978
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.304687108
Short name T240
Test name
Test status
Simulation time 169400811763 ps
CPU time 97.1 seconds
Started Jan 21 03:50:29 PM PST 24
Finished Jan 21 03:52:07 PM PST 24
Peak memory 201276 kb
Host smart-667421f6-c43e-4281-90cb-d18e41ca9b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304687108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.304687108
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1485073825
Short name T133
Test name
Test status
Simulation time 161227621214 ps
CPU time 368.15 seconds
Started Jan 21 03:50:27 PM PST 24
Finished Jan 21 03:56:36 PM PST 24
Peak memory 201092 kb
Host smart-8f8156a9-fdb7-4c61-b709-80436f1b6bd9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485073825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1485073825
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.4100554940
Short name T137
Test name
Test status
Simulation time 325775653218 ps
CPU time 209.37 seconds
Started Jan 21 03:50:21 PM PST 24
Finished Jan 21 03:53:52 PM PST 24
Peak memory 201248 kb
Host smart-9612485d-807f-41c5-a06a-4859b580ac21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100554940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.4100554940
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1368911934
Short name T432
Test name
Test status
Simulation time 162098767720 ps
CPU time 383.87 seconds
Started Jan 21 03:50:23 PM PST 24
Finished Jan 21 03:56:48 PM PST 24
Peak memory 201264 kb
Host smart-23dc41b3-6a39-4bac-9ba8-37ed579a3332
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368911934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1368911934
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2092189549
Short name T276
Test name
Test status
Simulation time 498802030607 ps
CPU time 144.73 seconds
Started Jan 21 04:08:10 PM PST 24
Finished Jan 21 04:10:38 PM PST 24
Peak memory 201148 kb
Host smart-5ea50d1e-0a51-46ea-a642-7be65461c1b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092189549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2092189549
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.331575724
Short name T520
Test name
Test status
Simulation time 331878068403 ps
CPU time 231.39 seconds
Started Jan 21 03:50:27 PM PST 24
Finished Jan 21 03:54:19 PM PST 24
Peak memory 201116 kb
Host smart-85e35d79-7682-4cc5-ada9-2f72f58c7dc1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331575724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.331575724
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3037246630
Short name T540
Test name
Test status
Simulation time 90857697792 ps
CPU time 380.03 seconds
Started Jan 21 03:50:22 PM PST 24
Finished Jan 21 03:56:43 PM PST 24
Peak memory 201504 kb
Host smart-975b594d-7b1c-46eb-acfd-315676baec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037246630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3037246630
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.115714103
Short name T853
Test name
Test status
Simulation time 24851984997 ps
CPU time 61.12 seconds
Started Jan 21 04:02:30 PM PST 24
Finished Jan 21 04:03:39 PM PST 24
Peak memory 201012 kb
Host smart-bfb345d0-ab59-4831-b5f8-7b3374e5f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115714103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.115714103
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3304342060
Short name T650
Test name
Test status
Simulation time 5540799795 ps
CPU time 2.43 seconds
Started Jan 21 03:50:27 PM PST 24
Finished Jan 21 03:50:31 PM PST 24
Peak memory 200976 kb
Host smart-b7f4efba-e8c3-4b7e-a616-c4178fb8d96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304342060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3304342060
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.941380894
Short name T706
Test name
Test status
Simulation time 5498840161 ps
CPU time 14.5 seconds
Started Jan 21 03:50:23 PM PST 24
Finished Jan 21 03:50:38 PM PST 24
Peak memory 200960 kb
Host smart-f11e6e79-dac8-4cad-a455-b8f38bbc3ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941380894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.941380894
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3630030509
Short name T311
Test name
Test status
Simulation time 201737950890 ps
CPU time 248.17 seconds
Started Jan 21 04:10:53 PM PST 24
Finished Jan 21 04:15:02 PM PST 24
Peak memory 201264 kb
Host smart-80e56f2e-424f-4b88-8258-ac421b096b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630030509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3630030509
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4111000953
Short name T282
Test name
Test status
Simulation time 329179178569 ps
CPU time 295.95 seconds
Started Jan 21 04:43:46 PM PST 24
Finished Jan 21 04:48:43 PM PST 24
Peak memory 209776 kb
Host smart-e3165ad2-6035-499f-a7cb-28a22d458471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111000953 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4111000953
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2219361801
Short name T762
Test name
Test status
Simulation time 325858588 ps
CPU time 0.78 seconds
Started Jan 21 03:56:08 PM PST 24
Finished Jan 21 03:56:14 PM PST 24
Peak memory 200976 kb
Host smart-cd0502a9-e55d-4284-b04b-303fefac87de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219361801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2219361801
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1441463099
Short name T144
Test name
Test status
Simulation time 494391075615 ps
CPU time 283.2 seconds
Started Jan 21 03:55:44 PM PST 24
Finished Jan 21 04:00:28 PM PST 24
Peak memory 201180 kb
Host smart-dceddbca-8777-48f5-b3f0-08f2d0e9da76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441463099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1441463099
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3575905213
Short name T577
Test name
Test status
Simulation time 329274788441 ps
CPU time 349.6 seconds
Started Jan 21 03:56:03 PM PST 24
Finished Jan 21 04:01:56 PM PST 24
Peak memory 201180 kb
Host smart-74445fe6-2320-4977-824e-4e47eb12a5f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575905213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3575905213
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.235656901
Short name T552
Test name
Test status
Simulation time 170067601776 ps
CPU time 77.92 seconds
Started Jan 21 03:55:45 PM PST 24
Finished Jan 21 03:57:03 PM PST 24
Peak memory 201208 kb
Host smart-57326db8-7ddf-4c84-b69c-97a0f06cf975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235656901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.235656901
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.566296370
Short name T18
Test name
Test status
Simulation time 491366972198 ps
CPU time 174.81 seconds
Started Jan 21 03:55:46 PM PST 24
Finished Jan 21 03:58:42 PM PST 24
Peak memory 201228 kb
Host smart-f5c300d5-1da7-410f-96cf-4f64feaa1246
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=566296370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.566296370
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3314653104
Short name T101
Test name
Test status
Simulation time 168603007138 ps
CPU time 363 seconds
Started Jan 21 03:56:03 PM PST 24
Finished Jan 21 04:02:09 PM PST 24
Peak memory 201180 kb
Host smart-29ccf8d5-d416-4c24-bdf5-24fbd7941e48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314653104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3314653104
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3099000087
Short name T692
Test name
Test status
Simulation time 498797547092 ps
CPU time 1145.53 seconds
Started Jan 21 03:55:59 PM PST 24
Finished Jan 21 04:15:06 PM PST 24
Peak memory 201420 kb
Host smart-9531b629-9cae-4fb7-a14f-7696ad375ea1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099000087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3099000087
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1173365397
Short name T201
Test name
Test status
Simulation time 84906722903 ps
CPU time 284.55 seconds
Started Jan 21 03:56:07 PM PST 24
Finished Jan 21 04:00:58 PM PST 24
Peak memory 201480 kb
Host smart-b256ddcb-a967-430a-909e-fe223257e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173365397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1173365397
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3934530913
Short name T574
Test name
Test status
Simulation time 47897472969 ps
CPU time 26.01 seconds
Started Jan 21 03:56:07 PM PST 24
Finished Jan 21 03:56:39 PM PST 24
Peak memory 200948 kb
Host smart-39be963d-1941-4b78-8009-3729a2c0d782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934530913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3934530913
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.12902078
Short name T719
Test name
Test status
Simulation time 4671313999 ps
CPU time 2.47 seconds
Started Jan 21 03:56:11 PM PST 24
Finished Jan 21 03:56:17 PM PST 24
Peak memory 200976 kb
Host smart-b2f5a0ef-28fa-42c5-bd34-096037abee0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12902078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.12902078
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1113421236
Short name T718
Test name
Test status
Simulation time 5984838369 ps
CPU time 2.61 seconds
Started Jan 21 03:55:46 PM PST 24
Finished Jan 21 03:55:50 PM PST 24
Peak memory 200960 kb
Host smart-026e3d28-a58b-497d-a38c-8d126691a7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113421236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1113421236
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2207303307
Short name T46
Test name
Test status
Simulation time 492203651208 ps
CPU time 309.38 seconds
Started Jan 21 03:56:16 PM PST 24
Finished Jan 21 04:01:28 PM PST 24
Peak memory 200848 kb
Host smart-a1acfd97-1b46-4443-b13d-400d444adfaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207303307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2207303307
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.62925094
Short name T607
Test name
Test status
Simulation time 29337939916 ps
CPU time 83.91 seconds
Started Jan 21 03:56:11 PM PST 24
Finished Jan 21 03:57:40 PM PST 24
Peak memory 201656 kb
Host smart-4a4b0237-2cd6-46da-8d80-e9dff364d940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62925094 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.62925094
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.263748799
Short name T455
Test name
Test status
Simulation time 315978343 ps
CPU time 0.79 seconds
Started Jan 21 04:31:46 PM PST 24
Finished Jan 21 04:31:49 PM PST 24
Peak memory 200988 kb
Host smart-ea1efad7-4089-4f88-89fd-8ef6946312fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263748799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.263748799
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2119626607
Short name T308
Test name
Test status
Simulation time 332760590412 ps
CPU time 422.61 seconds
Started Jan 21 03:56:13 PM PST 24
Finished Jan 21 04:03:20 PM PST 24
Peak memory 201152 kb
Host smart-c6fd705e-712c-4158-b0ac-008c25ddccc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119626607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2119626607
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1145646443
Short name T214
Test name
Test status
Simulation time 164298496336 ps
CPU time 106.27 seconds
Started Jan 21 03:56:13 PM PST 24
Finished Jan 21 03:58:04 PM PST 24
Peak memory 201228 kb
Host smart-adcc8600-8199-4410-ba4b-02d77bbc3086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145646443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1145646443
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.776216111
Short name T138
Test name
Test status
Simulation time 335963176304 ps
CPU time 216.55 seconds
Started Jan 21 03:56:08 PM PST 24
Finished Jan 21 03:59:50 PM PST 24
Peak memory 201092 kb
Host smart-2aa03e3f-cc02-4014-b1c3-a5753ebc3cc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=776216111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.776216111
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.4268027496
Short name T751
Test name
Test status
Simulation time 334714760372 ps
CPU time 377.43 seconds
Started Jan 21 03:56:15 PM PST 24
Finished Jan 21 04:02:36 PM PST 24
Peak memory 200816 kb
Host smart-17f2564a-ff41-4c73-8e8c-e99fa7e46ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268027496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4268027496
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2786193071
Short name T482
Test name
Test status
Simulation time 330744254150 ps
CPU time 682.63 seconds
Started Jan 21 03:56:06 PM PST 24
Finished Jan 21 04:07:35 PM PST 24
Peak memory 201220 kb
Host smart-7075f9e3-7a6e-4888-aab6-6b1e89ef9f65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786193071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2786193071
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4039686653
Short name T159
Test name
Test status
Simulation time 488509897742 ps
CPU time 572.35 seconds
Started Jan 21 03:56:14 PM PST 24
Finished Jan 21 04:05:51 PM PST 24
Peak memory 201224 kb
Host smart-945b87c9-4418-47ad-9c1e-e798aa1a1e73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039686653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4039686653
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3685597287
Short name T472
Test name
Test status
Simulation time 492376574926 ps
CPU time 680.87 seconds
Started Jan 21 03:56:07 PM PST 24
Finished Jan 21 04:07:34 PM PST 24
Peak memory 201076 kb
Host smart-ddd4e299-691e-4958-8b21-36c8029ff646
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685597287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3685597287
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2084160829
Short name T343
Test name
Test status
Simulation time 113466588043 ps
CPU time 360.64 seconds
Started Jan 21 03:56:12 PM PST 24
Finished Jan 21 04:02:18 PM PST 24
Peak memory 201544 kb
Host smart-3928ee1f-ba62-4098-bde3-06b3df0d55ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084160829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2084160829
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3295587721
Short name T621
Test name
Test status
Simulation time 29660160391 ps
CPU time 71.9 seconds
Started Jan 21 03:56:10 PM PST 24
Finished Jan 21 03:57:26 PM PST 24
Peak memory 200964 kb
Host smart-bd8134cd-20f9-472f-add0-9ec5f5bb8540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295587721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3295587721
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2231522119
Short name T816
Test name
Test status
Simulation time 3795022420 ps
CPU time 4.94 seconds
Started Jan 21 03:56:13 PM PST 24
Finished Jan 21 03:56:23 PM PST 24
Peak memory 201012 kb
Host smart-fa022c9f-aec6-448c-ba24-d56f1e37ec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231522119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2231522119
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2478503766
Short name T678
Test name
Test status
Simulation time 5796151777 ps
CPU time 14.42 seconds
Started Jan 21 03:56:15 PM PST 24
Finished Jan 21 03:56:33 PM PST 24
Peak memory 200548 kb
Host smart-329e35d0-710a-4490-86b7-565a8689df98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478503766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2478503766
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1099366656
Short name T490
Test name
Test status
Simulation time 176375135182 ps
CPU time 194.88 seconds
Started Jan 21 03:56:22 PM PST 24
Finished Jan 21 03:59:38 PM PST 24
Peak memory 201264 kb
Host smart-877113e9-ab2a-4cd7-bf4c-9ea1d1d378a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099366656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1099366656
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3262333853
Short name T336
Test name
Test status
Simulation time 224787281722 ps
CPU time 125.07 seconds
Started Jan 21 03:56:11 PM PST 24
Finished Jan 21 03:58:20 PM PST 24
Peak memory 209404 kb
Host smart-daf313e9-174b-483a-94c6-871ccafb5dd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262333853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3262333853
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.836092841
Short name T528
Test name
Test status
Simulation time 523406782 ps
CPU time 0.88 seconds
Started Jan 21 03:56:41 PM PST 24
Finished Jan 21 03:56:44 PM PST 24
Peak memory 200904 kb
Host smart-064fd3ae-f263-408b-b608-6e802c136604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836092841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.836092841
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3229096199
Short name T508
Test name
Test status
Simulation time 168948100903 ps
CPU time 13.98 seconds
Started Jan 21 03:56:27 PM PST 24
Finished Jan 21 03:56:42 PM PST 24
Peak memory 201368 kb
Host smart-18ef4622-2835-4cb8-8d35-cb9456ab41dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229096199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3229096199
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.539457026
Short name T657
Test name
Test status
Simulation time 165772869964 ps
CPU time 109.03 seconds
Started Jan 21 03:56:21 PM PST 24
Finished Jan 21 03:58:12 PM PST 24
Peak memory 201228 kb
Host smart-c847774b-2500-4b24-a7b7-fdc6d9c8d316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539457026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.539457026
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3286310381
Short name T611
Test name
Test status
Simulation time 488565968632 ps
CPU time 261.7 seconds
Started Jan 21 04:37:51 PM PST 24
Finished Jan 21 04:42:13 PM PST 24
Peak memory 201200 kb
Host smart-77640571-550e-4512-bb60-b080e66305a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286310381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3286310381
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3927985838
Short name T238
Test name
Test status
Simulation time 162354479803 ps
CPU time 111.3 seconds
Started Jan 21 04:30:08 PM PST 24
Finished Jan 21 04:32:01 PM PST 24
Peak memory 201148 kb
Host smart-5b7374d0-f21e-486d-ac7d-79a511326b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927985838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3927985838
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1196571313
Short name T161
Test name
Test status
Simulation time 330718714216 ps
CPU time 407.93 seconds
Started Jan 21 03:56:20 PM PST 24
Finished Jan 21 04:03:10 PM PST 24
Peak memory 201212 kb
Host smart-28ad1d4f-8cee-4b86-a3d9-4b53049617d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196571313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1196571313
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1662701601
Short name T272
Test name
Test status
Simulation time 490020023880 ps
CPU time 236.38 seconds
Started Jan 21 03:56:22 PM PST 24
Finished Jan 21 04:00:19 PM PST 24
Peak memory 201284 kb
Host smart-a2d7bc1e-d1e3-4be1-b577-bf9d9ee8d0fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662701601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1662701601
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4222300261
Short name T641
Test name
Test status
Simulation time 327730783229 ps
CPU time 192.75 seconds
Started Jan 21 03:56:28 PM PST 24
Finished Jan 21 03:59:42 PM PST 24
Peak memory 201100 kb
Host smart-165ccb9e-a019-4bb6-9e9e-b144c6d45003
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222300261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4222300261
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3039795142
Short name T848
Test name
Test status
Simulation time 38181538906 ps
CPU time 78.4 seconds
Started Jan 21 03:56:31 PM PST 24
Finished Jan 21 03:57:50 PM PST 24
Peak memory 201012 kb
Host smart-158b3a64-af59-480c-81ae-8a590a9bb10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039795142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3039795142
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3815461805
Short name T440
Test name
Test status
Simulation time 3932105814 ps
CPU time 10.07 seconds
Started Jan 21 03:56:27 PM PST 24
Finished Jan 21 03:56:38 PM PST 24
Peak memory 201008 kb
Host smart-a0b3622b-5e12-438e-81ea-734b135bcc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815461805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3815461805
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3908143339
Short name T788
Test name
Test status
Simulation time 6076904319 ps
CPU time 6.53 seconds
Started Jan 21 03:56:20 PM PST 24
Finished Jan 21 03:56:29 PM PST 24
Peak memory 200904 kb
Host smart-ddb1e369-1385-48b6-a3f4-8ec9770477d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908143339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3908143339
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.4112381692
Short name T164
Test name
Test status
Simulation time 335349229441 ps
CPU time 212.45 seconds
Started Jan 21 03:56:37 PM PST 24
Finished Jan 21 04:00:11 PM PST 24
Peak memory 201212 kb
Host smart-8ab9c474-ec5d-44ec-aab5-85cb197e64c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112381692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.4112381692
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3556126034
Short name T145
Test name
Test status
Simulation time 21048555045 ps
CPU time 65.31 seconds
Started Jan 21 03:56:31 PM PST 24
Finished Jan 21 03:57:37 PM PST 24
Peak memory 217864 kb
Host smart-e377bb98-fafe-4111-bde1-bcac90ebf7d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556126034 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3556126034
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2844701880
Short name T417
Test name
Test status
Simulation time 372563969 ps
CPU time 1.46 seconds
Started Jan 21 03:56:53 PM PST 24
Finished Jan 21 03:56:56 PM PST 24
Peak memory 200936 kb
Host smart-1668bca1-095c-4d20-a30a-d28757cfc4ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844701880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2844701880
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2542675694
Short name T126
Test name
Test status
Simulation time 164138174486 ps
CPU time 102.7 seconds
Started Jan 21 03:56:51 PM PST 24
Finished Jan 21 03:58:35 PM PST 24
Peak memory 201208 kb
Host smart-c8b20636-f7fb-4561-aa13-ac1a7508f68e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542675694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2542675694
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1010972809
Short name T821
Test name
Test status
Simulation time 495176498174 ps
CPU time 325.01 seconds
Started Jan 21 03:56:49 PM PST 24
Finished Jan 21 04:02:16 PM PST 24
Peak memory 201112 kb
Host smart-7ace16be-c288-45b9-861d-eb013d01b15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010972809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1010972809
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2470283299
Short name T807
Test name
Test status
Simulation time 494571793789 ps
CPU time 1174.78 seconds
Started Jan 21 03:56:53 PM PST 24
Finished Jan 21 04:16:29 PM PST 24
Peak memory 201188 kb
Host smart-c04f0d59-db33-4dac-9ca6-d28d1b55bd67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470283299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2470283299
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1391668147
Short name T128
Test name
Test status
Simulation time 493130030275 ps
CPU time 292.1 seconds
Started Jan 21 03:56:53 PM PST 24
Finished Jan 21 04:01:46 PM PST 24
Peak memory 201268 kb
Host smart-7af4de56-8615-4a79-9989-b0f63334b449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391668147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1391668147
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3687519289
Short name T419
Test name
Test status
Simulation time 327916476858 ps
CPU time 140.44 seconds
Started Jan 21 03:56:49 PM PST 24
Finished Jan 21 03:59:11 PM PST 24
Peak memory 201160 kb
Host smart-39a7ba50-4a1b-4d70-90ed-c3ff884710c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687519289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3687519289
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3480475327
Short name T225
Test name
Test status
Simulation time 491203889739 ps
CPU time 277.09 seconds
Started Jan 21 03:56:50 PM PST 24
Finished Jan 21 04:01:28 PM PST 24
Peak memory 201204 kb
Host smart-47eeadda-a358-4a62-a657-709ebe40d430
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480475327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3480475327
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1467413119
Short name T737
Test name
Test status
Simulation time 500409400440 ps
CPU time 103.42 seconds
Started Jan 21 03:56:50 PM PST 24
Finished Jan 21 03:58:34 PM PST 24
Peak memory 201156 kb
Host smart-ffba04dd-6075-46bb-b2ea-cac791de2322
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467413119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1467413119
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3944777541
Short name T772
Test name
Test status
Simulation time 124427292610 ps
CPU time 651.74 seconds
Started Jan 21 03:56:54 PM PST 24
Finished Jan 21 04:07:47 PM PST 24
Peak memory 201412 kb
Host smart-faaa6f9b-3aaa-4f52-87db-06ab2dae06d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944777541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3944777541
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2529981063
Short name T562
Test name
Test status
Simulation time 44446371115 ps
CPU time 21.08 seconds
Started Jan 21 03:56:51 PM PST 24
Finished Jan 21 03:57:14 PM PST 24
Peak memory 200996 kb
Host smart-42c5e368-7fc9-46a3-b5e5-efef05be8cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529981063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2529981063
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1321899767
Short name T523
Test name
Test status
Simulation time 3595776300 ps
CPU time 9.33 seconds
Started Jan 21 03:56:51 PM PST 24
Finished Jan 21 03:57:02 PM PST 24
Peak memory 201044 kb
Host smart-f2e7b25e-ed71-40fb-bb4e-ed95e5bb9053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321899767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1321899767
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.43674077
Short name T51
Test name
Test status
Simulation time 5837711501 ps
CPU time 7.11 seconds
Started Jan 21 03:56:49 PM PST 24
Finished Jan 21 03:56:57 PM PST 24
Peak memory 201000 kb
Host smart-9edee3fd-3729-4fcd-9974-1994feedd8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43674077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.43674077
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2444897917
Short name T316
Test name
Test status
Simulation time 488263727916 ps
CPU time 602.43 seconds
Started Jan 21 03:56:54 PM PST 24
Finished Jan 21 04:06:58 PM PST 24
Peak memory 201176 kb
Host smart-779a62a9-3ead-4bff-9c77-f0f443933971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444897917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2444897917
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2561135339
Short name T729
Test name
Test status
Simulation time 286006435921 ps
CPU time 42.76 seconds
Started Jan 21 03:56:53 PM PST 24
Finished Jan 21 03:57:37 PM PST 24
Peak memory 209360 kb
Host smart-280de9d1-a3d0-4aa5-aa86-cda37977d375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561135339 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2561135339
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.878209231
Short name T37
Test name
Test status
Simulation time 409519411 ps
CPU time 1.58 seconds
Started Jan 21 03:57:13 PM PST 24
Finished Jan 21 03:57:15 PM PST 24
Peak memory 200936 kb
Host smart-aea7219c-06c7-4c3a-83ff-d58ab5af5486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878209231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.878209231
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1204831197
Short name T171
Test name
Test status
Simulation time 334771060453 ps
CPU time 200.95 seconds
Started Jan 21 03:57:02 PM PST 24
Finished Jan 21 04:00:24 PM PST 24
Peak memory 201104 kb
Host smart-fcdec339-fe61-4563-b617-15d83e040a70
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204831197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1204831197
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1032252893
Short name T764
Test name
Test status
Simulation time 335253509809 ps
CPU time 363.28 seconds
Started Jan 21 03:57:14 PM PST 24
Finished Jan 21 04:03:18 PM PST 24
Peak memory 201132 kb
Host smart-aec52bd2-5754-4fcb-b18c-7da267628cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032252893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1032252893
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1514198538
Short name T333
Test name
Test status
Simulation time 495529488965 ps
CPU time 1107.35 seconds
Started Jan 21 03:57:02 PM PST 24
Finished Jan 21 04:15:30 PM PST 24
Peak memory 201180 kb
Host smart-ee78e426-f489-431b-a6bc-b050ed7bb2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514198538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1514198538
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2973673330
Short name T587
Test name
Test status
Simulation time 167289130340 ps
CPU time 58.49 seconds
Started Jan 21 03:57:00 PM PST 24
Finished Jan 21 03:57:59 PM PST 24
Peak memory 201040 kb
Host smart-101d8f4d-3d44-4259-89b4-6ea91f4c70ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973673330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2973673330
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.475966893
Short name T750
Test name
Test status
Simulation time 330398389003 ps
CPU time 444.65 seconds
Started Jan 21 03:56:53 PM PST 24
Finished Jan 21 04:04:20 PM PST 24
Peak memory 201216 kb
Host smart-fa5c6d57-e834-4f93-b732-d1a8db67941a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475966893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.475966893
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1916764241
Short name T614
Test name
Test status
Simulation time 165397486734 ps
CPU time 392.19 seconds
Started Jan 21 03:56:52 PM PST 24
Finished Jan 21 04:03:26 PM PST 24
Peak memory 201152 kb
Host smart-ce26ab3c-12a0-48e5-a0ff-a8245615a97c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916764241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1916764241
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.291010168
Short name T852
Test name
Test status
Simulation time 496190191675 ps
CPU time 326.7 seconds
Started Jan 21 03:57:03 PM PST 24
Finished Jan 21 04:02:30 PM PST 24
Peak memory 201100 kb
Host smart-90718434-bdda-4f28-8182-948a7da43396
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291010168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.291010168
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1997279682
Short name T186
Test name
Test status
Simulation time 106763384770 ps
CPU time 520.27 seconds
Started Jan 21 04:24:14 PM PST 24
Finished Jan 21 04:32:56 PM PST 24
Peak memory 201468 kb
Host smart-9c3bc090-f847-454c-a44b-51c4426ec830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997279682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1997279682
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.381526740
Short name T632
Test name
Test status
Simulation time 25032387668 ps
CPU time 14.58 seconds
Started Jan 21 04:22:42 PM PST 24
Finished Jan 21 04:22:59 PM PST 24
Peak memory 201016 kb
Host smart-6d6ee4b2-1c08-4a2b-8335-baf5e99e11db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381526740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.381526740
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3097927762
Short name T765
Test name
Test status
Simulation time 3156765319 ps
CPU time 2.71 seconds
Started Jan 21 04:26:09 PM PST 24
Finished Jan 21 04:26:14 PM PST 24
Peak memory 200968 kb
Host smart-9573ce06-2e4f-4482-9316-59bc961929c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097927762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3097927762
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4064136521
Short name T84
Test name
Test status
Simulation time 6035886265 ps
CPU time 13.7 seconds
Started Jan 21 03:56:53 PM PST 24
Finished Jan 21 03:57:09 PM PST 24
Peak memory 200900 kb
Host smart-124545b8-1002-4e7c-bcd6-d7d0e2ba153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064136521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4064136521
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.718833971
Short name T840
Test name
Test status
Simulation time 434726503348 ps
CPU time 223.67 seconds
Started Jan 21 03:57:13 PM PST 24
Finished Jan 21 04:00:57 PM PST 24
Peak memory 209796 kb
Host smart-f90afcaa-a8d0-4605-b1a6-2379d8fecdec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718833971 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.718833971
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.983327973
Short name T661
Test name
Test status
Simulation time 341290930 ps
CPU time 0.7 seconds
Started Jan 21 04:27:23 PM PST 24
Finished Jan 21 04:27:24 PM PST 24
Peak memory 200928 kb
Host smart-222b47bd-5007-40e4-af20-9a04e2e1d9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983327973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.983327973
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.497269817
Short name T822
Test name
Test status
Simulation time 163365637509 ps
CPU time 101.1 seconds
Started Jan 21 03:57:22 PM PST 24
Finished Jan 21 03:59:04 PM PST 24
Peak memory 201252 kb
Host smart-afd2a9cd-9944-4967-a745-f96dcdada843
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497269817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.497269817
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1785931453
Short name T90
Test name
Test status
Simulation time 167790926425 ps
CPU time 199.09 seconds
Started Jan 21 03:57:28 PM PST 24
Finished Jan 21 04:00:48 PM PST 24
Peak memory 201208 kb
Host smart-24ed547d-6033-4c94-a7aa-e32fea2fdf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785931453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1785931453
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2882096261
Short name T742
Test name
Test status
Simulation time 159909151544 ps
CPU time 372.1 seconds
Started Jan 21 03:57:26 PM PST 24
Finished Jan 21 04:03:39 PM PST 24
Peak memory 201244 kb
Host smart-4e9a4008-8811-4243-8630-376bdc29003f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882096261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2882096261
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1766044751
Short name T453
Test name
Test status
Simulation time 160763972007 ps
CPU time 174.77 seconds
Started Jan 21 03:57:29 PM PST 24
Finished Jan 21 04:00:26 PM PST 24
Peak memory 201104 kb
Host smart-cdde2bb3-2fc6-4240-b2ae-b9c2a225f0c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766044751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1766044751
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3457838554
Short name T836
Test name
Test status
Simulation time 164117894477 ps
CPU time 198.77 seconds
Started Jan 21 03:57:24 PM PST 24
Finished Jan 21 04:00:43 PM PST 24
Peak memory 201172 kb
Host smart-3a8a616f-ee58-4b47-bb4e-178d37af0eaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457838554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3457838554
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.996742399
Short name T224
Test name
Test status
Simulation time 165463687450 ps
CPU time 370.31 seconds
Started Jan 21 03:57:30 PM PST 24
Finished Jan 21 04:03:42 PM PST 24
Peak memory 201164 kb
Host smart-2b5650ac-31cd-41f2-bd3a-d3d5dfb132d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996742399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.996742399
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.925621396
Short name T344
Test name
Test status
Simulation time 129788083832 ps
CPU time 372.4 seconds
Started Jan 21 03:57:31 PM PST 24
Finished Jan 21 04:03:45 PM PST 24
Peak memory 201408 kb
Host smart-eec72faf-0407-4ff0-8686-352d3f3e187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925621396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.925621396
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.166016949
Short name T559
Test name
Test status
Simulation time 35286780014 ps
CPU time 52.19 seconds
Started Jan 21 03:57:26 PM PST 24
Finished Jan 21 03:58:19 PM PST 24
Peak memory 201236 kb
Host smart-25361723-fd9a-4816-9f41-22310e2328ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166016949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.166016949
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2702613904
Short name T667
Test name
Test status
Simulation time 4538037706 ps
CPU time 3.23 seconds
Started Jan 21 03:57:27 PM PST 24
Finished Jan 21 03:57:31 PM PST 24
Peak memory 201020 kb
Host smart-dc70413d-046a-456c-8422-c45338557fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702613904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2702613904
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3374037318
Short name T431
Test name
Test status
Simulation time 5921993620 ps
CPU time 3.36 seconds
Started Jan 21 04:22:07 PM PST 24
Finished Jan 21 04:22:11 PM PST 24
Peak memory 201016 kb
Host smart-4c3d2536-b851-4c6d-b247-acdc41a91aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374037318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3374037318
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2346530603
Short name T638
Test name
Test status
Simulation time 436202965 ps
CPU time 1.67 seconds
Started Jan 21 03:57:38 PM PST 24
Finished Jan 21 03:57:41 PM PST 24
Peak memory 201008 kb
Host smart-e65a48fb-bd4b-459a-bffe-6d13ba8833a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346530603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2346530603
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1818446603
Short name T530
Test name
Test status
Simulation time 158242159215 ps
CPU time 98.44 seconds
Started Jan 21 03:57:31 PM PST 24
Finished Jan 21 03:59:10 PM PST 24
Peak memory 201096 kb
Host smart-314eb9f3-9a5f-45c3-8d9c-d3464525c75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818446603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1818446603
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2809342327
Short name T809
Test name
Test status
Simulation time 162081495915 ps
CPU time 401 seconds
Started Jan 21 04:52:02 PM PST 24
Finished Jan 21 04:58:44 PM PST 24
Peak memory 201192 kb
Host smart-49e07c68-9d27-4cec-910e-bb272214cc7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809342327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2809342327
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4096623040
Short name T597
Test name
Test status
Simulation time 323904987068 ps
CPU time 360.69 seconds
Started Jan 21 03:57:33 PM PST 24
Finished Jan 21 04:03:35 PM PST 24
Peak memory 201184 kb
Host smart-54dc63a8-1081-4180-a274-f52959d2d277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096623040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4096623040
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.4021343056
Short name T586
Test name
Test status
Simulation time 493217102005 ps
CPU time 1115.07 seconds
Started Jan 21 04:34:12 PM PST 24
Finished Jan 21 04:52:48 PM PST 24
Peak memory 201224 kb
Host smart-8e35d006-d3a0-4fd8-a100-805b68ec80f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021343056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.4021343056
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.213165900
Short name T167
Test name
Test status
Simulation time 323769562675 ps
CPU time 186.13 seconds
Started Jan 21 06:07:01 PM PST 24
Finished Jan 21 06:10:10 PM PST 24
Peak memory 201192 kb
Host smart-25567bea-42e7-4821-addf-4249ae547889
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213165900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.213165900
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.181491123
Short name T509
Test name
Test status
Simulation time 328243482323 ps
CPU time 736.39 seconds
Started Jan 21 03:57:41 PM PST 24
Finished Jan 21 04:09:59 PM PST 24
Peak memory 201080 kb
Host smart-d862adc6-0aad-40ce-9c1e-01f271934dc4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181491123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.181491123
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.433046308
Short name T713
Test name
Test status
Simulation time 116020863604 ps
CPU time 402 seconds
Started Jan 21 03:57:39 PM PST 24
Finished Jan 21 04:04:21 PM PST 24
Peak memory 201452 kb
Host smart-32dd9434-b92f-4cea-a77b-621056a14f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433046308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.433046308
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3023160395
Short name T98
Test name
Test status
Simulation time 21982700712 ps
CPU time 3.24 seconds
Started Jan 21 03:57:38 PM PST 24
Finished Jan 21 03:57:42 PM PST 24
Peak memory 201012 kb
Host smart-57d3e15f-64be-490f-b2d8-dc3fa6d8f10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023160395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3023160395
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3420982926
Short name T491
Test name
Test status
Simulation time 3337543833 ps
CPU time 8.78 seconds
Started Jan 21 03:57:39 PM PST 24
Finished Jan 21 03:57:49 PM PST 24
Peak memory 201236 kb
Host smart-56471907-e115-4a0f-a5c7-5a3f9fff0b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420982926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3420982926
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.4241300641
Short name T522
Test name
Test status
Simulation time 5896988827 ps
CPU time 15.52 seconds
Started Jan 21 05:25:06 PM PST 24
Finished Jan 21 05:25:29 PM PST 24
Peak memory 201032 kb
Host smart-8a34179e-6090-45b8-8d8f-2c38b8d74a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241300641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4241300641
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.4082798813
Short name T794
Test name
Test status
Simulation time 373066189406 ps
CPU time 243.47 seconds
Started Jan 21 03:57:40 PM PST 24
Finished Jan 21 04:01:44 PM PST 24
Peak memory 201124 kb
Host smart-3a3a11bc-2a3f-48e3-8ae2-0cfd242c4543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082798813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.4082798813
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2448644882
Short name T694
Test name
Test status
Simulation time 39913123314 ps
CPU time 136.55 seconds
Started Jan 21 03:57:40 PM PST 24
Finished Jan 21 03:59:58 PM PST 24
Peak memory 209828 kb
Host smart-9d61fac5-f001-4382-9009-d8ae4fac88ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448644882 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2448644882
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1367309698
Short name T499
Test name
Test status
Simulation time 389432394 ps
CPU time 1.57 seconds
Started Jan 21 03:58:05 PM PST 24
Finished Jan 21 03:58:07 PM PST 24
Peak memory 200908 kb
Host smart-14ecc29a-2037-4a5d-9e59-26282e56e705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367309698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1367309698
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2141537875
Short name T237
Test name
Test status
Simulation time 164487656816 ps
CPU time 165.98 seconds
Started Jan 21 03:57:54 PM PST 24
Finished Jan 21 04:00:41 PM PST 24
Peak memory 201188 kb
Host smart-f8e5d35e-cb03-4711-bb54-9ce06208d759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141537875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2141537875
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.285268445
Short name T339
Test name
Test status
Simulation time 318933560020 ps
CPU time 206.1 seconds
Started Jan 21 03:57:46 PM PST 24
Finished Jan 21 04:01:13 PM PST 24
Peak memory 201172 kb
Host smart-54d84982-f9d2-44c4-832b-245d36ce704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285268445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.285268445
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3740371927
Short name T467
Test name
Test status
Simulation time 165928637085 ps
CPU time 202.75 seconds
Started Jan 21 03:57:44 PM PST 24
Finished Jan 21 04:01:07 PM PST 24
Peak memory 201176 kb
Host smart-5c5ea8bf-2598-4b89-9235-13179219b8a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740371927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3740371927
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1470006422
Short name T513
Test name
Test status
Simulation time 497866757757 ps
CPU time 961.94 seconds
Started Jan 21 03:57:43 PM PST 24
Finished Jan 21 04:13:45 PM PST 24
Peak memory 201208 kb
Host smart-53f05aae-031c-40f9-839c-7b3059a74c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470006422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1470006422
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1643473426
Short name T856
Test name
Test status
Simulation time 165216926743 ps
CPU time 387.95 seconds
Started Jan 21 03:57:47 PM PST 24
Finished Jan 21 04:04:16 PM PST 24
Peak memory 201212 kb
Host smart-660d6dda-1756-4667-bfbc-8c34a3040826
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643473426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1643473426
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3055179919
Short name T825
Test name
Test status
Simulation time 495436086844 ps
CPU time 1134.34 seconds
Started Jan 21 03:57:44 PM PST 24
Finished Jan 21 04:16:39 PM PST 24
Peak memory 201168 kb
Host smart-ee34eb8a-a44a-483b-83a3-fa900c942010
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055179919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3055179919
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2836566726
Short name T800
Test name
Test status
Simulation time 336271125497 ps
CPU time 216.07 seconds
Started Jan 21 03:57:46 PM PST 24
Finished Jan 21 04:01:22 PM PST 24
Peak memory 201284 kb
Host smart-7691ba71-1ba7-4799-8111-cbc9cc6e1f9b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836566726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2836566726
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3450469170
Short name T196
Test name
Test status
Simulation time 102644039312 ps
CPU time 352.98 seconds
Started Jan 21 03:57:52 PM PST 24
Finished Jan 21 04:03:46 PM PST 24
Peak memory 201432 kb
Host smart-0177e6e7-7ccf-401a-b8e0-636e4f93c78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450469170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3450469170
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.153178147
Short name T686
Test name
Test status
Simulation time 36740402862 ps
CPU time 19.55 seconds
Started Jan 21 03:57:57 PM PST 24
Finished Jan 21 03:58:17 PM PST 24
Peak memory 200988 kb
Host smart-b7fc43c9-7102-4635-bd81-72c268bd7818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153178147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.153178147
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1738860166
Short name T805
Test name
Test status
Simulation time 3616964281 ps
CPU time 5.23 seconds
Started Jan 21 03:57:55 PM PST 24
Finished Jan 21 03:58:01 PM PST 24
Peak memory 200972 kb
Host smart-c7b0bdc3-c6e0-4c60-a822-196614a476eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738860166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1738860166
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.4222161322
Short name T746
Test name
Test status
Simulation time 5860665626 ps
CPU time 7.36 seconds
Started Jan 21 03:57:46 PM PST 24
Finished Jan 21 03:57:54 PM PST 24
Peak memory 201036 kb
Host smart-05068002-1568-4669-bdb6-e2228974e61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222161322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.4222161322
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2316743435
Short name T213
Test name
Test status
Simulation time 206286163061 ps
CPU time 118.41 seconds
Started Jan 21 03:57:54 PM PST 24
Finished Jan 21 03:59:53 PM PST 24
Peak memory 209432 kb
Host smart-5c54856b-7eca-4077-a673-ddef4f8b33a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316743435 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2316743435
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2685486606
Short name T444
Test name
Test status
Simulation time 496686733 ps
CPU time 0.92 seconds
Started Jan 21 04:19:53 PM PST 24
Finished Jan 21 04:20:07 PM PST 24
Peak memory 200916 kb
Host smart-b06968cb-1468-4328-8a38-d8b3edbc73ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685486606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2685486606
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2519384686
Short name T818
Test name
Test status
Simulation time 333241884265 ps
CPU time 214.78 seconds
Started Jan 21 03:58:15 PM PST 24
Finished Jan 21 04:01:55 PM PST 24
Peak memory 201160 kb
Host smart-1f0c0d1d-c800-4136-a6c6-2ec6621e970e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519384686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2519384686
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3061526872
Short name T500
Test name
Test status
Simulation time 329444934443 ps
CPU time 372.06 seconds
Started Jan 21 03:58:17 PM PST 24
Finished Jan 21 04:04:32 PM PST 24
Peak memory 201200 kb
Host smart-87439206-8f7d-4741-8809-9f6fed20fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061526872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3061526872
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3757022760
Short name T165
Test name
Test status
Simulation time 500489256878 ps
CPU time 286.18 seconds
Started Jan 21 03:58:05 PM PST 24
Finished Jan 21 04:02:52 PM PST 24
Peak memory 201096 kb
Host smart-6153546a-c8d2-451b-bf07-1f83588733dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757022760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3757022760
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1357959673
Short name T418
Test name
Test status
Simulation time 322775036965 ps
CPU time 732.14 seconds
Started Jan 21 03:58:14 PM PST 24
Finished Jan 21 04:10:32 PM PST 24
Peak memory 201244 kb
Host smart-62202900-d74a-458d-bfa2-b6a656154179
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357959673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1357959673
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3372839696
Short name T14
Test name
Test status
Simulation time 324967453901 ps
CPU time 192.24 seconds
Started Jan 21 03:58:04 PM PST 24
Finished Jan 21 04:01:17 PM PST 24
Peak memory 201172 kb
Host smart-b3293747-3978-4a7f-8cec-32df5255eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372839696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3372839696
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2848093186
Short name T634
Test name
Test status
Simulation time 158859093617 ps
CPU time 91.57 seconds
Started Jan 21 03:58:04 PM PST 24
Finished Jan 21 03:59:36 PM PST 24
Peak memory 201236 kb
Host smart-062f3138-d713-472c-9cec-5404ec03320e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848093186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2848093186
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1406514518
Short name T516
Test name
Test status
Simulation time 164978909788 ps
CPU time 199.14 seconds
Started Jan 21 04:37:12 PM PST 24
Finished Jan 21 04:40:32 PM PST 24
Peak memory 201108 kb
Host smart-100c6727-7f01-42c6-8303-aa853c4ec909
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406514518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1406514518
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1087017310
Short name T817
Test name
Test status
Simulation time 123458920410 ps
CPU time 439.45 seconds
Started Jan 21 03:58:11 PM PST 24
Finished Jan 21 04:05:36 PM PST 24
Peak memory 201376 kb
Host smart-63a10bfe-6650-4ac4-9c1d-86dd0aaee626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087017310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1087017310
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2250864488
Short name T553
Test name
Test status
Simulation time 39328696752 ps
CPU time 62.51 seconds
Started Jan 21 03:58:14 PM PST 24
Finished Jan 21 03:59:23 PM PST 24
Peak memory 200928 kb
Host smart-d6e3fa7e-4236-423b-9c63-bbb1cee738cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250864488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2250864488
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3987184720
Short name T413
Test name
Test status
Simulation time 4725314159 ps
CPU time 3.43 seconds
Started Jan 21 06:21:57 PM PST 24
Finished Jan 21 06:22:03 PM PST 24
Peak memory 200988 kb
Host smart-f16a9a6b-ab91-4c4c-b41c-3d4754263990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987184720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3987184720
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.483109579
Short name T684
Test name
Test status
Simulation time 6023160474 ps
CPU time 8.8 seconds
Started Jan 21 03:58:03 PM PST 24
Finished Jan 21 03:58:13 PM PST 24
Peak memory 201008 kb
Host smart-a761a9ec-8267-495e-ba34-10efcf13748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483109579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.483109579
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1196353987
Short name T799
Test name
Test status
Simulation time 234164212129 ps
CPU time 271.72 seconds
Started Jan 21 03:58:17 PM PST 24
Finished Jan 21 04:02:52 PM PST 24
Peak memory 209816 kb
Host smart-149e2ac2-b7a2-4305-a175-f5683cadb894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196353987 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1196353987
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3011062135
Short name T720
Test name
Test status
Simulation time 347492335 ps
CPU time 1.42 seconds
Started Jan 21 03:58:33 PM PST 24
Finished Jan 21 03:58:36 PM PST 24
Peak memory 200892 kb
Host smart-71abbe71-267b-4ac0-822d-ec7f7957cda3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011062135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3011062135
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1119991823
Short name T312
Test name
Test status
Simulation time 164282934548 ps
CPU time 82.9 seconds
Started Jan 21 03:58:27 PM PST 24
Finished Jan 21 03:59:50 PM PST 24
Peak memory 201108 kb
Host smart-fc0beb3a-49c6-4342-8551-4b165b99dfd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119991823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1119991823
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1837818545
Short name T834
Test name
Test status
Simulation time 330429642860 ps
CPU time 298.55 seconds
Started Jan 21 04:33:21 PM PST 24
Finished Jan 21 04:38:21 PM PST 24
Peak memory 201368 kb
Host smart-a8008284-7f2a-44f4-af6a-8c3d45e2a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837818545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1837818545
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3009264493
Short name T529
Test name
Test status
Simulation time 492083053392 ps
CPU time 1182.57 seconds
Started Jan 21 03:58:25 PM PST 24
Finished Jan 21 04:18:09 PM PST 24
Peak memory 201148 kb
Host smart-80999d27-77d5-4c36-bfa3-56ab3a2fd0bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009264493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3009264493
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2538798907
Short name T744
Test name
Test status
Simulation time 490470807561 ps
CPU time 1215.58 seconds
Started Jan 21 03:58:18 PM PST 24
Finished Jan 21 04:18:37 PM PST 24
Peak memory 201176 kb
Host smart-53148818-5b7b-4195-8bbe-0180b218349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538798907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2538798907
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1786747340
Short name T708
Test name
Test status
Simulation time 487720234043 ps
CPU time 294.43 seconds
Started Jan 21 03:58:18 PM PST 24
Finished Jan 21 04:03:18 PM PST 24
Peak memory 201160 kb
Host smart-6794d6a7-b702-44f7-8cb8-5368d008e674
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786747340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1786747340
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3820522356
Short name T792
Test name
Test status
Simulation time 363841959305 ps
CPU time 235.01 seconds
Started Jan 21 04:19:49 PM PST 24
Finished Jan 21 04:23:58 PM PST 24
Peak memory 201232 kb
Host smart-b578a1bc-322d-4805-8c16-233f1c3e73ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820522356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3820522356
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2781738441
Short name T711
Test name
Test status
Simulation time 498170386194 ps
CPU time 294.8 seconds
Started Jan 21 03:58:29 PM PST 24
Finished Jan 21 04:03:25 PM PST 24
Peak memory 201420 kb
Host smart-2cacf5ed-e450-45a6-8b25-0c4048667eb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781738441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2781738441
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2360716260
Short name T669
Test name
Test status
Simulation time 114763511881 ps
CPU time 630.87 seconds
Started Jan 21 03:58:26 PM PST 24
Finished Jan 21 04:08:58 PM PST 24
Peak memory 201516 kb
Host smart-a75f791b-6528-4bf2-9c61-df1775210fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360716260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2360716260
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2115775121
Short name T544
Test name
Test status
Simulation time 41376612168 ps
CPU time 25.45 seconds
Started Jan 21 03:58:26 PM PST 24
Finished Jan 21 03:58:53 PM PST 24
Peak memory 200936 kb
Host smart-4b4f9781-e487-4ce4-97c9-704de7cb1151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115775121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2115775121
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.331940873
Short name T707
Test name
Test status
Simulation time 4834204320 ps
CPU time 12.08 seconds
Started Jan 21 04:51:21 PM PST 24
Finished Jan 21 04:51:34 PM PST 24
Peak memory 201012 kb
Host smart-fa24ce26-ebad-4126-a0ba-eac835f131cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331940873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.331940873
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3932143734
Short name T715
Test name
Test status
Simulation time 5808401259 ps
CPU time 13.89 seconds
Started Jan 21 03:58:19 PM PST 24
Finished Jan 21 03:58:38 PM PST 24
Peak memory 201032 kb
Host smart-dbdb9b79-27e1-44a3-9d95-95fc8444dc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932143734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3932143734
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3928803920
Short name T795
Test name
Test status
Simulation time 29217541906 ps
CPU time 47.52 seconds
Started Jan 21 03:58:26 PM PST 24
Finished Jan 21 03:59:15 PM PST 24
Peak memory 209432 kb
Host smart-94d66476-32a3-4823-a54a-aa82a12f09c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928803920 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3928803920
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3479829219
Short name T463
Test name
Test status
Simulation time 451808740 ps
CPU time 1.76 seconds
Started Jan 21 03:50:33 PM PST 24
Finished Jan 21 03:50:36 PM PST 24
Peak memory 200972 kb
Host smart-e9cecd63-2640-45e5-a2c7-1a5d1f9fc596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479829219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3479829219
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3791092019
Short name T288
Test name
Test status
Simulation time 336267744349 ps
CPU time 96.22 seconds
Started Jan 21 03:50:29 PM PST 24
Finished Jan 21 03:52:06 PM PST 24
Peak memory 201172 kb
Host smart-71122f93-0ebd-41ef-8fae-5f4a81106df4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791092019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3791092019
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1480190586
Short name T329
Test name
Test status
Simulation time 485952904749 ps
CPU time 325.15 seconds
Started Jan 21 03:50:32 PM PST 24
Finished Jan 21 03:55:58 PM PST 24
Peak memory 201280 kb
Host smart-71e55dd6-bb2c-4ac9-a9a7-b380e9140ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480190586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1480190586
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1818563426
Short name T270
Test name
Test status
Simulation time 326202699156 ps
CPU time 502.35 seconds
Started Jan 21 04:02:38 PM PST 24
Finished Jan 21 04:11:08 PM PST 24
Peak memory 201136 kb
Host smart-2365f948-04b2-4d3a-bcd2-9be5ce3d6d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818563426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1818563426
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3447309853
Short name T150
Test name
Test status
Simulation time 498030127343 ps
CPU time 1202.02 seconds
Started Jan 21 03:50:26 PM PST 24
Finished Jan 21 04:10:29 PM PST 24
Peak memory 201180 kb
Host smart-64554d63-a8c9-49ac-8019-5aff3dae2b53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447309853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3447309853
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4269522546
Short name T21
Test name
Test status
Simulation time 498397971292 ps
CPU time 1015.78 seconds
Started Jan 21 03:50:30 PM PST 24
Finished Jan 21 04:07:27 PM PST 24
Peak memory 201268 kb
Host smart-ed935510-6cc8-4a44-8e8e-9bc3f8a4482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269522546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4269522546
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3929354539
Short name T579
Test name
Test status
Simulation time 493365566043 ps
CPU time 176.12 seconds
Started Jan 21 03:50:27 PM PST 24
Finished Jan 21 03:53:24 PM PST 24
Peak memory 201232 kb
Host smart-9ba89466-bab1-4a55-bd4e-d4328f5d76a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929354539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3929354539
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4247614961
Short name T426
Test name
Test status
Simulation time 331832169347 ps
CPU time 211.58 seconds
Started Jan 21 04:25:25 PM PST 24
Finished Jan 21 04:28:57 PM PST 24
Peak memory 201236 kb
Host smart-585acf31-1668-44a8-8d9a-1a2b09a30565
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247614961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4247614961
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2317923495
Short name T789
Test name
Test status
Simulation time 97924463242 ps
CPU time 275.69 seconds
Started Jan 21 03:50:34 PM PST 24
Finished Jan 21 03:55:10 PM PST 24
Peak memory 201340 kb
Host smart-afc05230-e6ae-4ece-a032-ab98d2f29c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317923495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2317923495
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1114523409
Short name T512
Test name
Test status
Simulation time 40687704202 ps
CPU time 51.16 seconds
Started Jan 21 04:32:55 PM PST 24
Finished Jan 21 04:33:49 PM PST 24
Peak memory 201028 kb
Host smart-fbabe5e5-4281-4dbd-9ea9-9baac3e6ff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114523409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1114523409
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.910422254
Short name T423
Test name
Test status
Simulation time 4326577491 ps
CPU time 2.96 seconds
Started Jan 21 03:50:30 PM PST 24
Finished Jan 21 03:50:34 PM PST 24
Peak memory 200992 kb
Host smart-af6f5978-821e-4e14-88d6-b6435af52c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910422254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.910422254
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3933666381
Short name T42
Test name
Test status
Simulation time 3803351858 ps
CPU time 3.17 seconds
Started Jan 21 03:50:26 PM PST 24
Finished Jan 21 03:50:30 PM PST 24
Peak memory 216236 kb
Host smart-78747649-13dd-4e5f-9a40-db037f4844ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933666381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3933666381
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.4057338661
Short name T797
Test name
Test status
Simulation time 5899210529 ps
CPU time 15.32 seconds
Started Jan 21 03:50:24 PM PST 24
Finished Jan 21 03:50:40 PM PST 24
Peak memory 200936 kb
Host smart-e657ce83-bbb8-417c-bc5f-f642a2b607e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057338661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.4057338661
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2858704470
Short name T747
Test name
Test status
Simulation time 502312174650 ps
CPU time 307.99 seconds
Started Jan 21 03:50:32 PM PST 24
Finished Jan 21 03:55:41 PM PST 24
Peak memory 201164 kb
Host smart-94abfb58-044d-43ba-be51-4ab1628533b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858704470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2858704470
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3097661730
Short name T722
Test name
Test status
Simulation time 412405822 ps
CPU time 0.67 seconds
Started Jan 21 03:58:41 PM PST 24
Finished Jan 21 03:58:46 PM PST 24
Peak memory 200960 kb
Host smart-2ef15eca-af14-4a8d-b93f-2066283fd956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097661730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3097661730
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2611749004
Short name T823
Test name
Test status
Simulation time 331206550410 ps
CPU time 225.15 seconds
Started Jan 21 03:58:42 PM PST 24
Finished Jan 21 04:02:32 PM PST 24
Peak memory 201116 kb
Host smart-af9240f9-0d36-4501-b03c-0b77372e3dbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611749004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2611749004
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1672162533
Short name T264
Test name
Test status
Simulation time 325371389398 ps
CPU time 207.65 seconds
Started Jan 21 03:58:40 PM PST 24
Finished Jan 21 04:02:10 PM PST 24
Peak memory 201248 kb
Host smart-258776aa-e08e-4071-b850-a4bd7c55aedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672162533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1672162533
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.888705234
Short name T121
Test name
Test status
Simulation time 167375026687 ps
CPU time 383.65 seconds
Started Jan 21 03:58:39 PM PST 24
Finished Jan 21 04:05:05 PM PST 24
Peak memory 201164 kb
Host smart-fae846c8-2c5c-4fde-b428-6aa198378f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888705234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.888705234
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2112597657
Short name T705
Test name
Test status
Simulation time 333869839926 ps
CPU time 184.09 seconds
Started Jan 21 03:58:37 PM PST 24
Finished Jan 21 04:01:42 PM PST 24
Peak memory 201152 kb
Host smart-58dcede8-8df5-497b-80e2-043c7041c407
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112597657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2112597657
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.953662638
Short name T601
Test name
Test status
Simulation time 163788598008 ps
CPU time 27.12 seconds
Started Jan 21 03:58:36 PM PST 24
Finished Jan 21 03:59:04 PM PST 24
Peak memory 201084 kb
Host smart-244f204f-0528-4f48-a4f2-8e2b9e9ae738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953662638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.953662638
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2551808757
Short name T152
Test name
Test status
Simulation time 165414335933 ps
CPU time 176.26 seconds
Started Jan 21 03:58:34 PM PST 24
Finished Jan 21 04:01:31 PM PST 24
Peak memory 201436 kb
Host smart-0074f05e-fa7d-418d-b26f-a3b5bd698f5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551808757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2551808757
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3203792478
Short name T287
Test name
Test status
Simulation time 158835481702 ps
CPU time 404.31 seconds
Started Jan 21 04:32:46 PM PST 24
Finished Jan 21 04:39:38 PM PST 24
Peak memory 201132 kb
Host smart-971ee60f-6ba2-480a-987e-8357e51a982b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203792478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3203792478
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.257808076
Short name T655
Test name
Test status
Simulation time 159108344604 ps
CPU time 62.18 seconds
Started Jan 21 03:58:34 PM PST 24
Finished Jan 21 03:59:37 PM PST 24
Peak memory 201152 kb
Host smart-24a3127e-f651-4538-ba4f-648482da40ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257808076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.257808076
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.425966494
Short name T735
Test name
Test status
Simulation time 81046525084 ps
CPU time 331.32 seconds
Started Jan 21 05:35:24 PM PST 24
Finished Jan 21 05:41:11 PM PST 24
Peak memory 201512 kb
Host smart-be004d28-c6d1-47cd-ac8d-be79b4039de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425966494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.425966494
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.433271588
Short name T441
Test name
Test status
Simulation time 31768669615 ps
CPU time 20.2 seconds
Started Jan 21 04:51:49 PM PST 24
Finished Jan 21 04:52:10 PM PST 24
Peak memory 201028 kb
Host smart-9a04f54a-487c-4958-98fe-9f92432754c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433271588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.433271588
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.452664689
Short name T688
Test name
Test status
Simulation time 3898163127 ps
CPU time 1.52 seconds
Started Jan 21 03:58:41 PM PST 24
Finished Jan 21 03:58:48 PM PST 24
Peak memory 200980 kb
Host smart-a3bbd477-7583-4251-b3cf-7306f2dd796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452664689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.452664689
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2638895308
Short name T428
Test name
Test status
Simulation time 5988899831 ps
CPU time 15.2 seconds
Started Jan 21 03:58:35 PM PST 24
Finished Jan 21 03:58:51 PM PST 24
Peak memory 200928 kb
Host smart-d6c99ea6-b37f-4115-af94-986b32310c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638895308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2638895308
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.250097551
Short name T220
Test name
Test status
Simulation time 322554624976 ps
CPU time 394.22 seconds
Started Jan 21 04:47:34 PM PST 24
Finished Jan 21 04:54:09 PM PST 24
Peak memory 201280 kb
Host smart-3c48ce02-c160-4c86-b6f1-3f807aa38f53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250097551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
250097551
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1979961524
Short name T555
Test name
Test status
Simulation time 436014837 ps
CPU time 0.68 seconds
Started Jan 21 03:59:01 PM PST 24
Finished Jan 21 03:59:08 PM PST 24
Peak memory 200956 kb
Host smart-fd92ef51-39d8-44f8-9d75-f851dfcbb5ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979961524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1979961524
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1557307342
Short name T617
Test name
Test status
Simulation time 169632109408 ps
CPU time 404.27 seconds
Started Jan 21 03:58:52 PM PST 24
Finished Jan 21 04:05:37 PM PST 24
Peak memory 201260 kb
Host smart-bb871c2f-dfdf-4a2b-85d6-0b83d60fb504
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557307342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1557307342
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1797897083
Short name T564
Test name
Test status
Simulation time 160070683737 ps
CPU time 76.21 seconds
Started Jan 21 03:58:52 PM PST 24
Finished Jan 21 04:00:10 PM PST 24
Peak memory 201156 kb
Host smart-ddb18f36-6440-4e3f-aac2-7532031cf928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797897083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1797897083
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.770545500
Short name T15
Test name
Test status
Simulation time 162233897807 ps
CPU time 104.98 seconds
Started Jan 21 06:02:34 PM PST 24
Finished Jan 21 06:04:20 PM PST 24
Peak memory 201272 kb
Host smart-50676c3a-2b2f-471b-922d-c0fabfe78057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770545500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.770545500
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1268701141
Short name T699
Test name
Test status
Simulation time 486417349305 ps
CPU time 633.15 seconds
Started Jan 21 05:08:53 PM PST 24
Finished Jan 21 05:19:27 PM PST 24
Peak memory 201160 kb
Host smart-7203316d-b739-4302-8a25-4337bd3a8b6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268701141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1268701141
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.411807193
Short name T91
Test name
Test status
Simulation time 496839145513 ps
CPU time 1171.69 seconds
Started Jan 21 05:40:33 PM PST 24
Finished Jan 21 06:00:06 PM PST 24
Peak memory 201280 kb
Host smart-f6d529f1-0ef4-409b-99e6-791861ee6621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411807193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.411807193
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.233522648
Short name T810
Test name
Test status
Simulation time 322743252068 ps
CPU time 162.38 seconds
Started Jan 21 03:58:40 PM PST 24
Finished Jan 21 04:01:25 PM PST 24
Peak memory 201248 kb
Host smart-a86f3e3b-284f-42f3-ab39-5c2b90eeed00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=233522648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.233522648
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1930603824
Short name T294
Test name
Test status
Simulation time 162974583031 ps
CPU time 88.97 seconds
Started Jan 21 03:58:52 PM PST 24
Finished Jan 21 04:00:22 PM PST 24
Peak memory 201140 kb
Host smart-3120e618-3b9d-4420-9984-041ba806d80b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930603824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1930603824
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2720919734
Short name T829
Test name
Test status
Simulation time 331812933887 ps
CPU time 398.22 seconds
Started Jan 21 03:58:47 PM PST 24
Finished Jan 21 04:05:27 PM PST 24
Peak memory 201244 kb
Host smart-949b6d6d-c279-422f-99e8-d954d7dec7a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720919734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2720919734
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1126104894
Short name T760
Test name
Test status
Simulation time 96416986680 ps
CPU time 483.27 seconds
Started Jan 21 04:14:38 PM PST 24
Finished Jan 21 04:22:42 PM PST 24
Peak memory 201484 kb
Host smart-ae9e662f-375d-440b-8aba-2f1dbb534f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126104894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1126104894
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3876456587
Short name T468
Test name
Test status
Simulation time 41373666222 ps
CPU time 27.6 seconds
Started Jan 21 03:58:53 PM PST 24
Finished Jan 21 03:59:21 PM PST 24
Peak memory 201020 kb
Host smart-24e0dc22-dd0d-4867-9a3b-f04e4c4a68b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876456587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3876456587
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.219463145
Short name T820
Test name
Test status
Simulation time 3737624500 ps
CPU time 8.46 seconds
Started Jan 21 03:58:52 PM PST 24
Finished Jan 21 03:59:01 PM PST 24
Peak memory 200960 kb
Host smart-5875be32-b356-4928-a254-ec9581e80df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219463145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.219463145
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1431489554
Short name T87
Test name
Test status
Simulation time 5588644705 ps
CPU time 4.33 seconds
Started Jan 21 04:15:31 PM PST 24
Finished Jan 21 04:15:38 PM PST 24
Peak memory 200956 kb
Host smart-df4c454d-4a3f-417c-9d66-b5d4fa1ec6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431489554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1431489554
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3672370964
Short name T813
Test name
Test status
Simulation time 382003663635 ps
CPU time 260.86 seconds
Started Jan 21 03:58:54 PM PST 24
Finished Jan 21 04:03:16 PM PST 24
Peak memory 201220 kb
Host smart-6ade099d-b8ba-4f38-ba3a-41cc21f38200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672370964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3672370964
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.351468021
Short name T438
Test name
Test status
Simulation time 406917270 ps
CPU time 0.82 seconds
Started Jan 21 03:59:16 PM PST 24
Finished Jan 21 03:59:18 PM PST 24
Peak memory 200940 kb
Host smart-03967a50-ab6f-4188-bfe4-59b218d33f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351468021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.351468021
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2862025866
Short name T283
Test name
Test status
Simulation time 165607612860 ps
CPU time 87.46 seconds
Started Jan 21 03:59:10 PM PST 24
Finished Jan 21 04:00:39 PM PST 24
Peak memory 201236 kb
Host smart-5ea548a1-952f-441a-8a4e-6c8c0ff290e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862025866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2862025866
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.872930026
Short name T808
Test name
Test status
Simulation time 489566646491 ps
CPU time 597.3 seconds
Started Jan 21 03:59:03 PM PST 24
Finished Jan 21 04:09:05 PM PST 24
Peak memory 201132 kb
Host smart-54e35498-d4a7-412f-835d-abfe281797bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=872930026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.872930026
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.863997715
Short name T290
Test name
Test status
Simulation time 496392460067 ps
CPU time 96.08 seconds
Started Jan 21 03:59:01 PM PST 24
Finished Jan 21 04:00:44 PM PST 24
Peak memory 201080 kb
Host smart-4fa874e9-7d22-414a-8e9b-338230f7ac6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863997715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.863997715
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.879325378
Short name T801
Test name
Test status
Simulation time 492511965182 ps
CPU time 182.87 seconds
Started Jan 21 03:59:01 PM PST 24
Finished Jan 21 04:02:10 PM PST 24
Peak memory 201408 kb
Host smart-f2fd2fa0-7428-4af5-b339-b648f628c846
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=879325378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.879325378
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3278325444
Short name T206
Test name
Test status
Simulation time 163846537763 ps
CPU time 252.43 seconds
Started Jan 21 03:59:12 PM PST 24
Finished Jan 21 04:03:25 PM PST 24
Peak memory 201196 kb
Host smart-36ef4ce2-bc9e-4d0b-86dc-8fbcbe3f2f12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278325444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3278325444
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3277108529
Short name T424
Test name
Test status
Simulation time 164127443999 ps
CPU time 363.68 seconds
Started Jan 21 03:59:10 PM PST 24
Finished Jan 21 04:05:16 PM PST 24
Peak memory 201168 kb
Host smart-0ecb324c-43a3-4a10-bde0-09766aafc845
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277108529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3277108529
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2638208090
Short name T345
Test name
Test status
Simulation time 107976374882 ps
CPU time 553.85 seconds
Started Jan 21 03:59:16 PM PST 24
Finished Jan 21 04:08:31 PM PST 24
Peak memory 201484 kb
Host smart-6abc6cfc-c82e-4003-a6fc-0222bdb98f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638208090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2638208090
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2124902187
Short name T695
Test name
Test status
Simulation time 45868061254 ps
CPU time 27.6 seconds
Started Jan 21 03:59:15 PM PST 24
Finished Jan 21 03:59:44 PM PST 24
Peak memory 201032 kb
Host smart-090ccab1-8d7b-4ff9-aa49-84a26a594e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124902187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2124902187
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.4239488593
Short name T626
Test name
Test status
Simulation time 3205854303 ps
CPU time 7.6 seconds
Started Jan 21 03:59:09 PM PST 24
Finished Jan 21 03:59:20 PM PST 24
Peak memory 200992 kb
Host smart-83166856-d703-4792-bdeb-2a77945dc8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239488593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4239488593
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.4065344630
Short name T645
Test name
Test status
Simulation time 5568011520 ps
CPU time 13.42 seconds
Started Jan 21 03:59:01 PM PST 24
Finished Jan 21 03:59:21 PM PST 24
Peak memory 200924 kb
Host smart-03e26ff0-c781-4061-81a0-0d24bffcba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065344630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.4065344630
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1122794811
Short name T325
Test name
Test status
Simulation time 177246105720 ps
CPU time 383.72 seconds
Started Jan 21 03:59:15 PM PST 24
Finished Jan 21 04:05:40 PM PST 24
Peak memory 201260 kb
Host smart-360ebace-b809-415e-93d2-f3de631b752b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122794811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1122794811
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1151728902
Short name T96
Test name
Test status
Simulation time 44998562068 ps
CPU time 48.43 seconds
Started Jan 21 03:59:15 PM PST 24
Finished Jan 21 04:00:04 PM PST 24
Peak memory 209764 kb
Host smart-ae0016e1-c24a-4142-b243-0bcc5a61979a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151728902 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1151728902
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1893164686
Short name T734
Test name
Test status
Simulation time 430539555 ps
CPU time 1.56 seconds
Started Jan 21 03:59:30 PM PST 24
Finished Jan 21 03:59:33 PM PST 24
Peak memory 200992 kb
Host smart-09fe6764-a6be-4ae2-bdfd-c173f87bcdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893164686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1893164686
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.820290397
Short name T554
Test name
Test status
Simulation time 332536688655 ps
CPU time 172.3 seconds
Started Jan 21 03:59:29 PM PST 24
Finished Jan 21 04:02:22 PM PST 24
Peak memory 201236 kb
Host smart-860c3261-77bb-4367-957f-a282bebed12c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=820290397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.820290397
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2763120656
Short name T52
Test name
Test status
Simulation time 324063900265 ps
CPU time 750.36 seconds
Started Jan 21 03:59:18 PM PST 24
Finished Jan 21 04:11:49 PM PST 24
Peak memory 201176 kb
Host smart-32db0592-c7f7-44ee-b1f6-dd0b6db905f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763120656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2763120656
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1708537716
Short name T13
Test name
Test status
Simulation time 164935274281 ps
CPU time 373.24 seconds
Started Jan 21 03:59:16 PM PST 24
Finished Jan 21 04:05:30 PM PST 24
Peak memory 201212 kb
Host smart-a4db8d21-f5e5-44eb-bf94-cef7604b4395
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708537716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1708537716
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2593689025
Short name T263
Test name
Test status
Simulation time 332599674336 ps
CPU time 198.53 seconds
Started Jan 21 03:59:31 PM PST 24
Finished Jan 21 04:02:51 PM PST 24
Peak memory 201140 kb
Host smart-56b92b35-41c3-42ff-8247-3f36699b92e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593689025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2593689025
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3111613721
Short name T857
Test name
Test status
Simulation time 162748145682 ps
CPU time 87.45 seconds
Started Jan 21 03:59:27 PM PST 24
Finished Jan 21 04:00:56 PM PST 24
Peak memory 201184 kb
Host smart-c2553350-2651-4ac4-8077-acae3874842e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111613721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3111613721
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.71087732
Short name T748
Test name
Test status
Simulation time 102261866801 ps
CPU time 572.64 seconds
Started Jan 21 03:59:31 PM PST 24
Finished Jan 21 04:09:06 PM PST 24
Peak memory 201416 kb
Host smart-d71de522-b8bc-432d-99bb-cebe7a874615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71087732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.71087732
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.566299679
Short name T479
Test name
Test status
Simulation time 26664471287 ps
CPU time 14.9 seconds
Started Jan 21 06:54:21 PM PST 24
Finished Jan 21 06:54:36 PM PST 24
Peak memory 201036 kb
Host smart-7ea98aa1-d260-404e-9f31-6540c954f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566299679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.566299679
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3969130531
Short name T524
Test name
Test status
Simulation time 4393991729 ps
CPU time 4.41 seconds
Started Jan 21 03:59:31 PM PST 24
Finished Jan 21 03:59:38 PM PST 24
Peak memory 200996 kb
Host smart-65e885a9-0b5d-4c0f-88b0-53a541d4d6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969130531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3969130531
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.919197984
Short name T495
Test name
Test status
Simulation time 5777877389 ps
CPU time 2.83 seconds
Started Jan 21 03:59:17 PM PST 24
Finished Jan 21 03:59:20 PM PST 24
Peak memory 200872 kb
Host smart-52c28a24-6588-431c-94c8-843b74a9e6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919197984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.919197984
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.102497596
Short name T11
Test name
Test status
Simulation time 208236323749 ps
CPU time 118.81 seconds
Started Jan 21 03:59:31 PM PST 24
Finished Jan 21 04:01:32 PM PST 24
Peak memory 201176 kb
Host smart-15dfad68-84be-4aa4-a1f1-0d8610f8f5bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102497596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
102497596
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.910488206
Short name T131
Test name
Test status
Simulation time 104310111429 ps
CPU time 223.89 seconds
Started Jan 21 03:59:30 PM PST 24
Finished Jan 21 04:03:16 PM PST 24
Peak memory 209588 kb
Host smart-844dcd6e-fd40-4852-92e1-585dc757fc5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910488206 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.910488206
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1142146170
Short name T778
Test name
Test status
Simulation time 468252571 ps
CPU time 0.91 seconds
Started Jan 21 03:59:42 PM PST 24
Finished Jan 21 03:59:44 PM PST 24
Peak memory 200968 kb
Host smart-2a55a450-db86-4491-b754-47cf59d25a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142146170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1142146170
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.782534665
Short name T332
Test name
Test status
Simulation time 168122193573 ps
CPU time 72.43 seconds
Started Jan 21 03:59:36 PM PST 24
Finished Jan 21 04:00:49 PM PST 24
Peak memory 201140 kb
Host smart-9fa7d1d5-8fbc-4182-9e6c-16d06ca79d64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782534665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.782534665
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1591476916
Short name T690
Test name
Test status
Simulation time 486756921932 ps
CPU time 210.99 seconds
Started Jan 21 04:28:19 PM PST 24
Finished Jan 21 04:31:51 PM PST 24
Peak memory 201240 kb
Host smart-4c0ad573-4bfc-41f0-9257-93a59cebcf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591476916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1591476916
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1920396910
Short name T687
Test name
Test status
Simulation time 505157445850 ps
CPU time 314.47 seconds
Started Jan 21 03:59:35 PM PST 24
Finished Jan 21 04:04:51 PM PST 24
Peak memory 201108 kb
Host smart-387c2bab-3ef3-461e-a330-1b6da92d1485
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920396910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1920396910
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2062370453
Short name T118
Test name
Test status
Simulation time 325055992887 ps
CPU time 238.12 seconds
Started Jan 21 04:27:37 PM PST 24
Finished Jan 21 04:31:36 PM PST 24
Peak memory 201244 kb
Host smart-d296be91-c36c-4f90-97b1-6feba0543a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062370453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2062370453
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4183415493
Short name T153
Test name
Test status
Simulation time 323884846724 ps
CPU time 206.13 seconds
Started Jan 21 03:59:35 PM PST 24
Finished Jan 21 04:03:02 PM PST 24
Peak memory 201120 kb
Host smart-a261fef2-d4f5-45dd-a0a0-85c0107d22be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183415493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4183415493
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3558411233
Short name T429
Test name
Test status
Simulation time 501723541436 ps
CPU time 1201.02 seconds
Started Jan 21 03:59:36 PM PST 24
Finished Jan 21 04:19:38 PM PST 24
Peak memory 201176 kb
Host smart-f2e78ed1-f180-49d0-8cd3-8bdae876bb6a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558411233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3558411233
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1179403355
Short name T469
Test name
Test status
Simulation time 72924563377 ps
CPU time 336.28 seconds
Started Jan 21 04:17:25 PM PST 24
Finished Jan 21 04:23:02 PM PST 24
Peak memory 201512 kb
Host smart-908a563c-5630-40ec-bc40-b1d7a2184087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179403355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1179403355
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.121646958
Short name T456
Test name
Test status
Simulation time 28187210816 ps
CPU time 15.1 seconds
Started Jan 21 03:59:44 PM PST 24
Finished Jan 21 04:00:00 PM PST 24
Peak memory 200976 kb
Host smart-361c0855-3e32-4e39-ab1f-83f3efb7226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121646958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.121646958
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2623007658
Short name T624
Test name
Test status
Simulation time 4772865759 ps
CPU time 4.84 seconds
Started Jan 21 03:59:45 PM PST 24
Finished Jan 21 03:59:51 PM PST 24
Peak memory 201012 kb
Host smart-27885a55-2000-492f-b7a1-d23fdf1bf464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623007658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2623007658
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.280362275
Short name T421
Test name
Test status
Simulation time 5985538629 ps
CPU time 2.21 seconds
Started Jan 21 03:59:30 PM PST 24
Finished Jan 21 03:59:33 PM PST 24
Peak memory 200992 kb
Host smart-a42fb6f6-ad30-4d43-a50b-5ebafc86e566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280362275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.280362275
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2896279858
Short name T115
Test name
Test status
Simulation time 329696876560 ps
CPU time 54.65 seconds
Started Jan 21 03:59:45 PM PST 24
Finished Jan 21 04:00:40 PM PST 24
Peak memory 201112 kb
Host smart-7b96e005-d528-439e-83d8-094a90d79aae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896279858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2896279858
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2595568989
Short name T190
Test name
Test status
Simulation time 327450913984 ps
CPU time 292.52 seconds
Started Jan 21 03:59:45 PM PST 24
Finished Jan 21 04:04:39 PM PST 24
Peak memory 209696 kb
Host smart-16f9f388-cdab-4842-a8c5-e2edc5aae655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595568989 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2595568989
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1570399278
Short name T275
Test name
Test status
Simulation time 495423871351 ps
CPU time 680.55 seconds
Started Jan 21 03:59:55 PM PST 24
Finished Jan 21 04:11:16 PM PST 24
Peak memory 201228 kb
Host smart-12fdce6d-8f49-4a40-a7ab-c39f41382caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570399278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1570399278
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3942032093
Short name T239
Test name
Test status
Simulation time 164878857231 ps
CPU time 411.43 seconds
Started Jan 21 04:43:32 PM PST 24
Finished Jan 21 04:50:24 PM PST 24
Peak memory 201204 kb
Host smart-28e4d3b5-c394-4867-bc22-bb7d0306fa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942032093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3942032093
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.4251321647
Short name T271
Test name
Test status
Simulation time 497545440156 ps
CPU time 1087.05 seconds
Started Jan 21 03:59:54 PM PST 24
Finished Jan 21 04:18:02 PM PST 24
Peak memory 201080 kb
Host smart-f178c87f-0c0d-4f76-93c1-f8a4a08da089
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251321647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.4251321647
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4000398326
Short name T177
Test name
Test status
Simulation time 327364978286 ps
CPU time 114.74 seconds
Started Jan 21 03:59:45 PM PST 24
Finished Jan 21 04:01:41 PM PST 24
Peak memory 201180 kb
Host smart-8666efd5-dd71-46da-abac-972518f5a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000398326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4000398326
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.4054100879
Short name T697
Test name
Test status
Simulation time 495489658116 ps
CPU time 296.16 seconds
Started Jan 21 03:59:49 PM PST 24
Finished Jan 21 04:04:46 PM PST 24
Peak memory 201156 kb
Host smart-89f834d5-70d5-4c5b-b9dc-a0bd75680ac7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054100879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.4054100879
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.855941131
Short name T249
Test name
Test status
Simulation time 166977045182 ps
CPU time 385.77 seconds
Started Jan 21 03:59:49 PM PST 24
Finished Jan 21 04:06:16 PM PST 24
Peak memory 201104 kb
Host smart-1814cd32-0f9a-4dea-a9de-9f13e977d381
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855941131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.855941131
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2870267704
Short name T665
Test name
Test status
Simulation time 164703276364 ps
CPU time 105.34 seconds
Started Jan 21 03:59:48 PM PST 24
Finished Jan 21 04:01:34 PM PST 24
Peak memory 201124 kb
Host smart-92cc826d-76a2-464d-a3bb-c3888ed78891
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870267704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2870267704
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2537908858
Short name T200
Test name
Test status
Simulation time 81976464135 ps
CPU time 305.63 seconds
Started Jan 21 04:46:27 PM PST 24
Finished Jan 21 04:51:33 PM PST 24
Peak memory 201504 kb
Host smart-78028b0c-3552-4e00-90b8-797b42d39625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537908858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2537908858
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3538198665
Short name T114
Test name
Test status
Simulation time 23554973336 ps
CPU time 13.4 seconds
Started Jan 21 03:59:56 PM PST 24
Finished Jan 21 04:00:10 PM PST 24
Peak memory 201000 kb
Host smart-ad63e388-4339-4f1b-a4a5-14f0542fb3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538198665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3538198665
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4046124450
Short name T575
Test name
Test status
Simulation time 3491553865 ps
CPU time 8.17 seconds
Started Jan 21 03:59:55 PM PST 24
Finished Jan 21 04:00:04 PM PST 24
Peak memory 200956 kb
Host smart-7d0b7735-7932-4882-be73-2e71fbdbf847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046124450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4046124450
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3899720790
Short name T570
Test name
Test status
Simulation time 5711441772 ps
CPU time 1.75 seconds
Started Jan 21 03:59:44 PM PST 24
Finished Jan 21 03:59:47 PM PST 24
Peak memory 201224 kb
Host smart-fce8876b-4ac5-4fea-b4fc-c85bd21a37fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899720790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3899720790
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.412789375
Short name T477
Test name
Test status
Simulation time 533409010 ps
CPU time 1.85 seconds
Started Jan 21 04:00:24 PM PST 24
Finished Jan 21 04:00:26 PM PST 24
Peak memory 200948 kb
Host smart-0b90ab7f-fdbe-486f-8a73-b315db11543c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412789375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.412789375
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2781163991
Short name T209
Test name
Test status
Simulation time 494346325575 ps
CPU time 814.05 seconds
Started Jan 21 04:00:12 PM PST 24
Finished Jan 21 04:13:49 PM PST 24
Peak memory 201168 kb
Host smart-541aba13-1f1d-4c34-8f1d-a44cbec3e1dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781163991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2781163991
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.592080910
Short name T173
Test name
Test status
Simulation time 327266275335 ps
CPU time 359.98 seconds
Started Jan 21 04:28:10 PM PST 24
Finished Jan 21 04:34:11 PM PST 24
Peak memory 201272 kb
Host smart-be7c55c0-4e45-4625-8c4b-278facc174a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592080910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.592080910
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3285768603
Short name T141
Test name
Test status
Simulation time 328565325930 ps
CPU time 189.08 seconds
Started Jan 21 04:00:09 PM PST 24
Finished Jan 21 04:03:19 PM PST 24
Peak memory 201208 kb
Host smart-9579703e-6a93-4032-b54a-ec982ded3079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285768603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3285768603
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.349529296
Short name T427
Test name
Test status
Simulation time 332810462592 ps
CPU time 381.28 seconds
Started Jan 21 04:40:33 PM PST 24
Finished Jan 21 04:46:55 PM PST 24
Peak memory 201232 kb
Host smart-eb0c32f5-c998-4c42-9b1d-34bd22b6c802
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=349529296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.349529296
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3063945680
Short name T246
Test name
Test status
Simulation time 164833446728 ps
CPU time 95.31 seconds
Started Jan 21 04:00:11 PM PST 24
Finished Jan 21 04:01:48 PM PST 24
Peak memory 201148 kb
Host smart-820d7897-96c0-4350-a7a4-643480aa61db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063945680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3063945680
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.160052157
Short name T465
Test name
Test status
Simulation time 329075497990 ps
CPU time 57.44 seconds
Started Jan 21 04:00:18 PM PST 24
Finished Jan 21 04:01:17 PM PST 24
Peak memory 201204 kb
Host smart-4920b284-a7ac-4d77-a85e-b607e697cc12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=160052157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.160052157
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2896966333
Short name T221
Test name
Test status
Simulation time 327340378765 ps
CPU time 52.25 seconds
Started Jan 21 04:00:09 PM PST 24
Finished Jan 21 04:01:02 PM PST 24
Peak memory 201164 kb
Host smart-8e7f6080-7f35-4fee-a013-de9e9a2b4e83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896966333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2896966333
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2329974696
Short name T691
Test name
Test status
Simulation time 326120704661 ps
CPU time 182.8 seconds
Started Jan 21 04:00:09 PM PST 24
Finished Jan 21 04:03:14 PM PST 24
Peak memory 201176 kb
Host smart-0e44432f-3ecf-4f6c-8791-551fd70d86fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329974696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2329974696
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.745313344
Short name T563
Test name
Test status
Simulation time 108371315963 ps
CPU time 577.66 seconds
Started Jan 21 04:00:22 PM PST 24
Finished Jan 21 04:10:01 PM PST 24
Peak memory 201396 kb
Host smart-4731157c-c062-4428-bbec-21dac3f40b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745313344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.745313344
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1975479867
Short name T458
Test name
Test status
Simulation time 27772967314 ps
CPU time 60.03 seconds
Started Jan 21 04:00:20 PM PST 24
Finished Jan 21 04:01:22 PM PST 24
Peak memory 200932 kb
Host smart-bcc4dab5-2697-449d-9987-c4b58817d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975479867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1975479867
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2751585291
Short name T561
Test name
Test status
Simulation time 5189657869 ps
CPU time 13.57 seconds
Started Jan 21 04:00:15 PM PST 24
Finished Jan 21 04:00:30 PM PST 24
Peak memory 201020 kb
Host smart-3f954e4e-1a2a-4689-b527-ec05d0f0dab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751585291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2751585291
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2746502214
Short name T841
Test name
Test status
Simulation time 5767413010 ps
CPU time 7.95 seconds
Started Jan 21 05:06:53 PM PST 24
Finished Jan 21 05:07:02 PM PST 24
Peak memory 201032 kb
Host smart-c5e0fadb-a185-405d-b79f-0f2d6ab1c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746502214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2746502214
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1440257368
Short name T503
Test name
Test status
Simulation time 274137432240 ps
CPU time 858.43 seconds
Started Jan 21 04:00:20 PM PST 24
Finished Jan 21 04:14:40 PM PST 24
Peak memory 201524 kb
Host smart-cc36b0e4-5057-4231-838c-178743026bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440257368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1440257368
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3000836415
Short name T631
Test name
Test status
Simulation time 13630818570 ps
CPU time 77.45 seconds
Started Jan 21 04:00:24 PM PST 24
Finished Jan 21 04:01:42 PM PST 24
Peak memory 217948 kb
Host smart-8d537bfd-0e95-4b52-a5ea-e2a2f88420a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000836415 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3000836415
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.607374171
Short name T828
Test name
Test status
Simulation time 425118656 ps
CPU time 1.76 seconds
Started Jan 21 04:26:17 PM PST 24
Finished Jan 21 04:26:20 PM PST 24
Peak memory 200936 kb
Host smart-c1cfdec5-58b6-4208-a3af-fe49813745ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607374171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.607374171
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1894904333
Short name T155
Test name
Test status
Simulation time 488096187331 ps
CPU time 309.56 seconds
Started Jan 21 04:32:49 PM PST 24
Finished Jan 21 04:38:03 PM PST 24
Peak memory 201248 kb
Host smart-2b745842-223d-44e7-a519-a8424d2fbd12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894904333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1894904333
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.912581131
Short name T313
Test name
Test status
Simulation time 333608266163 ps
CPU time 830.1 seconds
Started Jan 21 05:18:59 PM PST 24
Finished Jan 21 05:32:52 PM PST 24
Peak memory 201284 kb
Host smart-8a554ca9-9b31-45fb-9d0a-8313c7070406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912581131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.912581131
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3530291499
Short name T216
Test name
Test status
Simulation time 496693231321 ps
CPU time 1174.39 seconds
Started Jan 21 04:56:02 PM PST 24
Finished Jan 21 05:15:37 PM PST 24
Peak memory 201276 kb
Host smart-d7f08f7c-32a4-4a41-bdd0-3d959fc66dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530291499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3530291499
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4183879152
Short name T492
Test name
Test status
Simulation time 485555443520 ps
CPU time 641.23 seconds
Started Jan 21 04:50:06 PM PST 24
Finished Jan 21 05:00:50 PM PST 24
Peak memory 201128 kb
Host smart-258777ee-c4dc-4c6a-ab31-a5e0769fa5d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183879152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.4183879152
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.54874685
Short name T673
Test name
Test status
Simulation time 164626900037 ps
CPU time 234.6 seconds
Started Jan 21 04:53:01 PM PST 24
Finished Jan 21 04:56:58 PM PST 24
Peak memory 201168 kb
Host smart-c60bcd7c-ae0f-4b37-ae6b-591f5ede8791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54874685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.54874685
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3350979295
Short name T654
Test name
Test status
Simulation time 162021357329 ps
CPU time 389.19 seconds
Started Jan 21 04:00:28 PM PST 24
Finished Jan 21 04:06:58 PM PST 24
Peak memory 201196 kb
Host smart-12ced185-19de-4fef-9742-e5c8e36526d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350979295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3350979295
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2146620487
Short name T326
Test name
Test status
Simulation time 494679537394 ps
CPU time 1163.95 seconds
Started Jan 21 04:26:12 PM PST 24
Finished Jan 21 04:45:37 PM PST 24
Peak memory 201216 kb
Host smart-dedeb8f5-2d23-4409-9e95-aa9dad9b8074
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146620487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2146620487
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3504370613
Short name T174
Test name
Test status
Simulation time 484076717149 ps
CPU time 317.49 seconds
Started Jan 21 04:44:27 PM PST 24
Finished Jan 21 04:49:45 PM PST 24
Peak memory 201172 kb
Host smart-ed410bf2-e9d5-417a-8987-8b91257bf3bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504370613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3504370613
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3763122053
Short name T184
Test name
Test status
Simulation time 125736901304 ps
CPU time 582.37 seconds
Started Jan 21 04:00:32 PM PST 24
Finished Jan 21 04:10:16 PM PST 24
Peak memory 201452 kb
Host smart-f1f0ce47-b6aa-40c8-b361-190f535fcb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763122053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3763122053
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1712875366
Short name T437
Test name
Test status
Simulation time 25463291421 ps
CPU time 34.72 seconds
Started Jan 21 05:02:59 PM PST 24
Finished Jan 21 05:03:37 PM PST 24
Peak memory 201028 kb
Host smart-2737dbce-d69b-41c2-992d-49d90fa3fa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712875366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1712875366
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.4095335295
Short name T733
Test name
Test status
Simulation time 4128716237 ps
CPU time 2.97 seconds
Started Jan 21 04:00:25 PM PST 24
Finished Jan 21 04:00:29 PM PST 24
Peak memory 201040 kb
Host smart-1e8c10b1-9c08-4e00-9ac6-0cb9f1519df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095335295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.4095335295
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3416736880
Short name T773
Test name
Test status
Simulation time 5799238927 ps
CPU time 4.11 seconds
Started Jan 21 04:00:21 PM PST 24
Finished Jan 21 04:00:27 PM PST 24
Peak memory 201040 kb
Host smart-73166281-5e3f-47f7-81bc-b3da4d227a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416736880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3416736880
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.686661404
Short name T588
Test name
Test status
Simulation time 195665126951 ps
CPU time 485.53 seconds
Started Jan 21 04:27:18 PM PST 24
Finished Jan 21 04:35:25 PM PST 24
Peak memory 201312 kb
Host smart-3890843e-bbfa-4b21-9f26-98fce331a950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686661404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
686661404
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.589664740
Short name T585
Test name
Test status
Simulation time 459755449 ps
CPU time 0.85 seconds
Started Jan 21 05:07:22 PM PST 24
Finished Jan 21 05:07:24 PM PST 24
Peak memory 200916 kb
Host smart-5299003a-384b-455c-8e93-6a34338a506d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589664740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.589664740
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.4163831459
Short name T837
Test name
Test status
Simulation time 497954903287 ps
CPU time 252.91 seconds
Started Jan 21 04:00:50 PM PST 24
Finished Jan 21 04:05:05 PM PST 24
Peak memory 201116 kb
Host smart-05cc3e36-c9c5-44b0-8603-aaec6114e608
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163831459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.4163831459
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3695782378
Short name T259
Test name
Test status
Simulation time 166250024608 ps
CPU time 383.96 seconds
Started Jan 21 04:43:14 PM PST 24
Finished Jan 21 04:49:38 PM PST 24
Peak memory 201276 kb
Host smart-5c6a3e92-8bed-4431-aa9a-90f0967aa649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695782378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3695782378
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.289323598
Short name T146
Test name
Test status
Simulation time 485994821150 ps
CPU time 216.92 seconds
Started Jan 21 04:57:12 PM PST 24
Finished Jan 21 05:00:49 PM PST 24
Peak memory 201280 kb
Host smart-6f057ac6-a170-4bfa-832b-7c4e722a450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289323598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.289323598
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.24510085
Short name T478
Test name
Test status
Simulation time 167296611022 ps
CPU time 215.05 seconds
Started Jan 21 05:25:11 PM PST 24
Finished Jan 21 05:28:49 PM PST 24
Peak memory 201176 kb
Host smart-00c0b668-0192-4c32-b5d9-e4b67c3b0400
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=24510085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt
_fixed.24510085
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1390767719
Short name T231
Test name
Test status
Simulation time 325405374112 ps
CPU time 683.7 seconds
Started Jan 21 04:00:33 PM PST 24
Finished Jan 21 04:11:58 PM PST 24
Peak memory 201080 kb
Host smart-451b8cb7-334c-4bdd-bcc5-79bba6fc8771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390767719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1390767719
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1706932329
Short name T449
Test name
Test status
Simulation time 331316417357 ps
CPU time 141.62 seconds
Started Jan 21 04:00:39 PM PST 24
Finished Jan 21 04:03:03 PM PST 24
Peak memory 201212 kb
Host smart-348f3ab7-b3c5-41b0-bdd7-9358f04eb17b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706932329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1706932329
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2626992979
Short name T318
Test name
Test status
Simulation time 331394234375 ps
CPU time 804.59 seconds
Started Jan 21 04:00:39 PM PST 24
Finished Jan 21 04:14:06 PM PST 24
Peak memory 201108 kb
Host smart-6d00450e-90ad-443a-8e9b-5e8ad7c2493c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626992979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2626992979
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2978172809
Short name T780
Test name
Test status
Simulation time 489347918812 ps
CPU time 611.46 seconds
Started Jan 21 04:34:39 PM PST 24
Finished Jan 21 04:44:54 PM PST 24
Peak memory 201124 kb
Host smart-80f98cc4-430f-4c09-b596-16ec9dc70229
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978172809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2978172809
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3233184089
Short name T194
Test name
Test status
Simulation time 95988033680 ps
CPU time 299.24 seconds
Started Jan 21 04:00:48 PM PST 24
Finished Jan 21 04:05:51 PM PST 24
Peak memory 201492 kb
Host smart-d19b60cf-c305-48e7-a6fc-79be99310a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233184089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3233184089
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1173667015
Short name T414
Test name
Test status
Simulation time 27679966842 ps
CPU time 16.46 seconds
Started Jan 21 04:00:49 PM PST 24
Finished Jan 21 04:01:08 PM PST 24
Peak memory 200968 kb
Host smart-34751786-82b3-4711-8c76-4d417bd466cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173667015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1173667015
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1241938505
Short name T600
Test name
Test status
Simulation time 3555637180 ps
CPU time 2.12 seconds
Started Jan 21 04:00:47 PM PST 24
Finished Jan 21 04:00:52 PM PST 24
Peak memory 200984 kb
Host smart-f1172ecf-f96b-40c8-a517-cd4a0a0df7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241938505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1241938505
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2565232667
Short name T547
Test name
Test status
Simulation time 5964877719 ps
CPU time 6.27 seconds
Started Jan 21 04:00:32 PM PST 24
Finished Jan 21 04:00:40 PM PST 24
Peak memory 200956 kb
Host smart-727ac0fe-2818-4e5b-a5b4-cd768ddebe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565232667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2565232667
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2999561699
Short name T298
Test name
Test status
Simulation time 413521107835 ps
CPU time 699.96 seconds
Started Jan 21 04:00:56 PM PST 24
Finished Jan 21 04:12:37 PM PST 24
Peak memory 211916 kb
Host smart-c914d11b-5d8e-44a6-8200-5ef7a6a5009a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999561699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2999561699
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2815237945
Short name T510
Test name
Test status
Simulation time 437520015 ps
CPU time 1.42 seconds
Started Jan 21 04:01:08 PM PST 24
Finished Jan 21 04:01:12 PM PST 24
Peak memory 200948 kb
Host smart-1bba2186-8b08-4626-9a51-d8e2da544596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815237945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2815237945
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1732805077
Short name T100
Test name
Test status
Simulation time 336262522890 ps
CPU time 250.63 seconds
Started Jan 21 04:29:47 PM PST 24
Finished Jan 21 04:34:00 PM PST 24
Peak memory 201236 kb
Host smart-738ab4de-8c19-41bb-b5e3-01afb12225c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732805077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1732805077
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4250256627
Short name T277
Test name
Test status
Simulation time 480955442602 ps
CPU time 1038.02 seconds
Started Jan 21 04:01:08 PM PST 24
Finished Jan 21 04:18:29 PM PST 24
Peak memory 201168 kb
Host smart-168912fb-1d07-4605-a432-f634f0bd1ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250256627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4250256627
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.32051507
Short name T594
Test name
Test status
Simulation time 491510802393 ps
CPU time 605.99 seconds
Started Jan 21 04:27:12 PM PST 24
Finished Jan 21 04:37:19 PM PST 24
Peak memory 201196 kb
Host smart-e61f4b7c-158e-4c3a-a2f4-34f7450b8736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32051507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.32051507
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2834959423
Short name T603
Test name
Test status
Simulation time 497648142290 ps
CPU time 332.6 seconds
Started Jan 21 06:05:14 PM PST 24
Finished Jan 21 06:10:47 PM PST 24
Peak memory 201176 kb
Host smart-4ee5f3a8-c730-4c74-9d45-b72b2998a788
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834959423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2834959423
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3914275593
Short name T278
Test name
Test status
Simulation time 492091329905 ps
CPU time 276.52 seconds
Started Jan 21 06:15:54 PM PST 24
Finished Jan 21 06:20:32 PM PST 24
Peak memory 201112 kb
Host smart-357c9176-6c1b-4bc4-81be-e2b47fc1fc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914275593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3914275593
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4108808366
Short name T643
Test name
Test status
Simulation time 490224273647 ps
CPU time 548.24 seconds
Started Jan 21 04:01:01 PM PST 24
Finished Jan 21 04:10:11 PM PST 24
Peak memory 201176 kb
Host smart-f1a709d7-2d1a-4517-baea-31512b940a5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108808366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4108808366
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1723031871
Short name T517
Test name
Test status
Simulation time 162602810950 ps
CPU time 382.45 seconds
Started Jan 21 04:00:58 PM PST 24
Finished Jan 21 04:07:22 PM PST 24
Peak memory 201200 kb
Host smart-e20d4e3c-ee69-4b00-8e56-47856f9a17bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723031871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1723031871
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2742401021
Short name T565
Test name
Test status
Simulation time 161879881992 ps
CPU time 364.52 seconds
Started Jan 21 04:00:59 PM PST 24
Finished Jan 21 04:07:06 PM PST 24
Peak memory 201140 kb
Host smart-8ebd7981-32c5-44c9-bfe4-4910cacc9382
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742401021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2742401021
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1355698188
Short name T162
Test name
Test status
Simulation time 34877796130 ps
CPU time 87.52 seconds
Started Jan 21 05:12:18 PM PST 24
Finished Jan 21 05:13:47 PM PST 24
Peak memory 201004 kb
Host smart-894586c6-5318-4f13-bc11-8d5355a5e7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355698188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1355698188
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1442703596
Short name T783
Test name
Test status
Simulation time 3980929875 ps
CPU time 10.38 seconds
Started Jan 21 04:01:08 PM PST 24
Finished Jan 21 04:01:21 PM PST 24
Peak memory 201036 kb
Host smart-0ae9941a-f6e5-4a8d-9bb3-10c0840def32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442703596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1442703596
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.246015071
Short name T633
Test name
Test status
Simulation time 5599670730 ps
CPU time 13.4 seconds
Started Jan 21 04:01:00 PM PST 24
Finished Jan 21 04:01:15 PM PST 24
Peak memory 201064 kb
Host smart-f90bd896-9ed4-40ba-919f-d6e31f926e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246015071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.246015071
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3213448036
Short name T260
Test name
Test status
Simulation time 58228495558 ps
CPU time 162.27 seconds
Started Jan 21 05:11:00 PM PST 24
Finished Jan 21 05:13:44 PM PST 24
Peak memory 209692 kb
Host smart-b20ac13c-a1a4-4e67-8ce4-3b7adaf276ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213448036 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3213448036
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2016978948
Short name T36
Test name
Test status
Simulation time 298173112 ps
CPU time 0.92 seconds
Started Jan 21 03:50:37 PM PST 24
Finished Jan 21 03:50:39 PM PST 24
Peak memory 200964 kb
Host smart-f3f3a871-5436-40d1-b499-5ab069d35b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016978948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2016978948
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3797363190
Short name T843
Test name
Test status
Simulation time 165770365459 ps
CPU time 180.15 seconds
Started Jan 21 03:50:49 PM PST 24
Finished Jan 21 03:53:50 PM PST 24
Peak memory 201220 kb
Host smart-605230a8-967f-4f82-9274-fe533a4d650e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797363190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3797363190
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3194727186
Short name T636
Test name
Test status
Simulation time 167940973648 ps
CPU time 368.89 seconds
Started Jan 21 03:50:29 PM PST 24
Finished Jan 21 03:56:39 PM PST 24
Peak memory 201256 kb
Host smart-455d551e-d62a-46c2-9cf8-34fa49003d4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194727186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3194727186
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3056519133
Short name T299
Test name
Test status
Simulation time 326347970405 ps
CPU time 757.64 seconds
Started Jan 21 03:50:34 PM PST 24
Finished Jan 21 04:03:13 PM PST 24
Peak memory 201280 kb
Host smart-85c82814-f797-4a12-8f62-c4c7ef770848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056519133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3056519133
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2866450766
Short name T571
Test name
Test status
Simulation time 160547823473 ps
CPU time 69.23 seconds
Started Jan 21 03:50:29 PM PST 24
Finished Jan 21 03:51:39 PM PST 24
Peak memory 201220 kb
Host smart-8fb4a388-3ad4-4244-adb4-0034929ee986
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866450766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2866450766
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2366545769
Short name T245
Test name
Test status
Simulation time 162244312383 ps
CPU time 108.19 seconds
Started Jan 21 03:50:31 PM PST 24
Finished Jan 21 03:52:20 PM PST 24
Peak memory 201140 kb
Host smart-05c17b82-7a5a-4634-b005-9b2bbac36636
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366545769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2366545769
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4230181449
Short name T646
Test name
Test status
Simulation time 325268483842 ps
CPU time 185.92 seconds
Started Jan 21 03:50:39 PM PST 24
Finished Jan 21 03:53:46 PM PST 24
Peak memory 201196 kb
Host smart-41ffc065-80fa-4381-8fac-b8e26ee24d21
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230181449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4230181449
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.743830776
Short name T698
Test name
Test status
Simulation time 119163768741 ps
CPU time 509.76 seconds
Started Jan 21 03:50:37 PM PST 24
Finished Jan 21 03:59:08 PM PST 24
Peak memory 201476 kb
Host smart-690505ba-3359-4c41-9454-041010f141cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743830776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.743830776
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.293086784
Short name T745
Test name
Test status
Simulation time 41508206340 ps
CPU time 29.49 seconds
Started Jan 21 03:50:41 PM PST 24
Finished Jan 21 03:51:12 PM PST 24
Peak memory 200984 kb
Host smart-192fe086-1e54-4e2d-8792-c9511f74409d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293086784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.293086784
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2400831591
Short name T149
Test name
Test status
Simulation time 3078024936 ps
CPU time 8.04 seconds
Started Jan 21 03:50:42 PM PST 24
Finished Jan 21 03:50:51 PM PST 24
Peak memory 201000 kb
Host smart-0776c183-e6fc-406a-a4b0-de1802b3f158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400831591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2400831591
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.422299036
Short name T511
Test name
Test status
Simulation time 5960679778 ps
CPU time 2.73 seconds
Started Jan 21 03:50:31 PM PST 24
Finished Jan 21 03:50:34 PM PST 24
Peak memory 200968 kb
Host smart-2218736a-aa3f-4b8c-87cc-59f87219cce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422299036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.422299036
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2923120252
Short name T704
Test name
Test status
Simulation time 325219741585 ps
CPU time 188.77 seconds
Started Jan 21 03:50:44 PM PST 24
Finished Jan 21 03:53:53 PM PST 24
Peak memory 201152 kb
Host smart-f5123e54-53d0-4824-94ad-91e1a5edc1d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923120252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2923120252
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.4094372666
Short name T242
Test name
Test status
Simulation time 32959209231 ps
CPU time 70.92 seconds
Started Jan 21 03:50:38 PM PST 24
Finished Jan 21 03:51:50 PM PST 24
Peak memory 209456 kb
Host smart-d35f8b34-9b5f-49b8-978f-e9746f00caeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094372666 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.4094372666
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1880478272
Short name T784
Test name
Test status
Simulation time 415716382 ps
CPU time 0.84 seconds
Started Jan 21 03:50:41 PM PST 24
Finished Jan 21 03:50:43 PM PST 24
Peak memory 200724 kb
Host smart-7a7c4dc8-3a13-462b-b6cb-f3bcf69720e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880478272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1880478272
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3001823712
Short name T689
Test name
Test status
Simulation time 165243864317 ps
CPU time 391.58 seconds
Started Jan 21 04:02:38 PM PST 24
Finished Jan 21 04:09:17 PM PST 24
Peak memory 201152 kb
Host smart-2b056618-574e-4cc6-aa9d-87c35b17da94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001823712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3001823712
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2876485015
Short name T506
Test name
Test status
Simulation time 168670071245 ps
CPU time 204.27 seconds
Started Jan 21 04:08:47 PM PST 24
Finished Jan 21 04:12:12 PM PST 24
Peak memory 201204 kb
Host smart-d2fa31a7-0d76-42dc-9058-1b5a5eb42420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876485015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2876485015
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2457336354
Short name T640
Test name
Test status
Simulation time 164303708076 ps
CPU time 387.34 seconds
Started Jan 21 04:10:46 PM PST 24
Finished Jan 21 04:17:14 PM PST 24
Peak memory 201248 kb
Host smart-93164483-93c5-4421-89e4-f82b16dad0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457336354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2457336354
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.288335928
Short name T569
Test name
Test status
Simulation time 488771017884 ps
CPU time 1077.03 seconds
Started Jan 21 03:50:47 PM PST 24
Finished Jan 21 04:08:45 PM PST 24
Peak memory 201176 kb
Host smart-820fbbac-0350-4dbe-a9fa-f669f4e34268
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=288335928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.288335928
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.342044257
Short name T838
Test name
Test status
Simulation time 323812239913 ps
CPU time 382.26 seconds
Started Jan 21 03:50:37 PM PST 24
Finished Jan 21 03:57:00 PM PST 24
Peak memory 201224 kb
Host smart-01be78d4-5d4a-4551-91da-c11427546d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342044257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.342044257
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1979967375
Short name T613
Test name
Test status
Simulation time 501037172487 ps
CPU time 320.28 seconds
Started Jan 21 03:50:41 PM PST 24
Finished Jan 21 03:56:02 PM PST 24
Peak memory 201240 kb
Host smart-d2de9607-2168-442d-945a-49e41fe48e60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979967375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1979967375
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3569158815
Short name T474
Test name
Test status
Simulation time 499412748406 ps
CPU time 1100.84 seconds
Started Jan 21 06:16:33 PM PST 24
Finished Jan 21 06:34:55 PM PST 24
Peak memory 201260 kb
Host smart-2d0ab717-d7a2-4e77-9689-c1242528e92a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569158815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3569158815
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.670198837
Short name T191
Test name
Test status
Simulation time 126102679012 ps
CPU time 540.86 seconds
Started Jan 21 03:50:41 PM PST 24
Finished Jan 21 03:59:43 PM PST 24
Peak memory 201388 kb
Host smart-399834d0-5407-48aa-9a84-bb90c5f8ab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670198837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.670198837
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1774885966
Short name T473
Test name
Test status
Simulation time 25200102998 ps
CPU time 30.59 seconds
Started Jan 21 03:50:39 PM PST 24
Finished Jan 21 03:51:11 PM PST 24
Peak memory 200976 kb
Host smart-18212105-2b22-49b7-a4f3-03869405f99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774885966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1774885966
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1910717228
Short name T804
Test name
Test status
Simulation time 2759521998 ps
CPU time 6.63 seconds
Started Jan 21 03:50:41 PM PST 24
Finished Jan 21 03:50:49 PM PST 24
Peak memory 200976 kb
Host smart-43b6d516-2731-492d-805a-8c7ecbb16eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910717228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1910717228
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.958837666
Short name T514
Test name
Test status
Simulation time 5769464524 ps
CPU time 4.06 seconds
Started Jan 21 03:50:41 PM PST 24
Finished Jan 21 03:50:46 PM PST 24
Peak memory 200972 kb
Host smart-ec183aba-52fd-4c7e-8637-6ddb0d58d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958837666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.958837666
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1103499991
Short name T323
Test name
Test status
Simulation time 323297111680 ps
CPU time 95.98 seconds
Started Jan 21 03:50:41 PM PST 24
Finished Jan 21 03:52:18 PM PST 24
Peak memory 201100 kb
Host smart-1ba9081c-9122-47d3-aafc-d8f060ccbac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103499991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1103499991
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3576845834
Short name T642
Test name
Test status
Simulation time 209655250715 ps
CPU time 126.89 seconds
Started Jan 21 03:50:47 PM PST 24
Finished Jan 21 03:52:55 PM PST 24
Peak memory 209432 kb
Host smart-d4b0f925-febe-4bf6-8c70-cd705adf60bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576845834 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3576845834
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3722396799
Short name T731
Test name
Test status
Simulation time 497017167 ps
CPU time 0.87 seconds
Started Jan 21 03:50:53 PM PST 24
Finished Jan 21 03:50:55 PM PST 24
Peak memory 200876 kb
Host smart-7cd938d0-f559-40e6-aa5c-da2e574fe2e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722396799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3722396799
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2095401512
Short name T218
Test name
Test status
Simulation time 326531537366 ps
CPU time 189.5 seconds
Started Jan 21 03:50:54 PM PST 24
Finished Jan 21 03:54:05 PM PST 24
Peak memory 201232 kb
Host smart-3fc88d92-6bc2-4d5b-a61c-2222bdfac4fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095401512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2095401512
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2662306266
Short name T556
Test name
Test status
Simulation time 164419498970 ps
CPU time 88.63 seconds
Started Jan 21 03:50:52 PM PST 24
Finished Jan 21 03:52:21 PM PST 24
Peak memory 201160 kb
Host smart-a3dc55e6-dcf0-4be7-a36f-09be3844ddbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662306266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2662306266
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.180132729
Short name T254
Test name
Test status
Simulation time 491234513119 ps
CPU time 1157.23 seconds
Started Jan 21 03:50:46 PM PST 24
Finished Jan 21 04:10:04 PM PST 24
Peak memory 201184 kb
Host smart-4527d26b-c444-4642-b464-c8432779ff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180132729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.180132729
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3764999059
Short name T139
Test name
Test status
Simulation time 478262105087 ps
CPU time 134.09 seconds
Started Jan 21 03:50:51 PM PST 24
Finished Jan 21 03:53:06 PM PST 24
Peak memory 201236 kb
Host smart-9e1fdb95-4ca5-4857-a29c-4cd00b627d6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764999059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3764999059
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3018542916
Short name T702
Test name
Test status
Simulation time 325255503281 ps
CPU time 280.41 seconds
Started Jan 21 03:50:42 PM PST 24
Finished Jan 21 03:55:23 PM PST 24
Peak memory 201128 kb
Host smart-175541f4-38fc-45eb-baf9-b8f11f04703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018542916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3018542916
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1556319955
Short name T609
Test name
Test status
Simulation time 329178770957 ps
CPU time 721.84 seconds
Started Jan 21 03:50:41 PM PST 24
Finished Jan 21 04:02:44 PM PST 24
Peak memory 201404 kb
Host smart-67c5ba8a-ba4c-421f-8fea-2ce263d157b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556319955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1556319955
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1297211740
Short name T148
Test name
Test status
Simulation time 165610610338 ps
CPU time 104.06 seconds
Started Jan 21 03:50:56 PM PST 24
Finished Jan 21 03:52:46 PM PST 24
Peak memory 201248 kb
Host smart-5f146694-c0ad-49b1-a840-8be3ac486ee3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297211740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1297211740
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2640892753
Short name T710
Test name
Test status
Simulation time 488823318063 ps
CPU time 291.33 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:55:59 PM PST 24
Peak memory 200756 kb
Host smart-b6e6c583-ab21-451a-9409-91164cbbd0c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640892753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2640892753
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1631729544
Short name T653
Test name
Test status
Simulation time 114426391228 ps
CPU time 479.81 seconds
Started Jan 21 03:50:50 PM PST 24
Finished Jan 21 03:58:51 PM PST 24
Peak memory 201484 kb
Host smart-e56091b7-cbb2-4899-a6e0-492058c8a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631729544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1631729544
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2950625516
Short name T541
Test name
Test status
Simulation time 28923269560 ps
CPU time 63.12 seconds
Started Jan 21 03:50:50 PM PST 24
Finished Jan 21 03:51:54 PM PST 24
Peak memory 201004 kb
Host smart-2b172626-2454-4958-b4f4-21d7563cb1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950625516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2950625516
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3848665985
Short name T420
Test name
Test status
Simulation time 5041524514 ps
CPU time 12.82 seconds
Started Jan 21 03:50:55 PM PST 24
Finished Jan 21 03:51:10 PM PST 24
Peak memory 201028 kb
Host smart-cefd72f7-c6a4-4a02-a5ea-d0c505241356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848665985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3848665985
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1469381461
Short name T668
Test name
Test status
Simulation time 5972639722 ps
CPU time 7.54 seconds
Started Jan 21 03:50:46 PM PST 24
Finished Jan 21 03:50:54 PM PST 24
Peak memory 200976 kb
Host smart-a328de80-a7d7-4333-9d2a-a3c8652661be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469381461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1469381461
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.523333296
Short name T743
Test name
Test status
Simulation time 170464172778 ps
CPU time 95.66 seconds
Started Jan 21 03:50:50 PM PST 24
Finished Jan 21 03:52:27 PM PST 24
Peak memory 201072 kb
Host smart-ab3cb0de-7b61-450c-9219-6933265d7cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523333296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.523333296
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3922829692
Short name T296
Test name
Test status
Simulation time 348013532317 ps
CPU time 102.25 seconds
Started Jan 21 03:50:55 PM PST 24
Finished Jan 21 03:52:39 PM PST 24
Peak memory 209500 kb
Host smart-29b3ade1-1fbd-4ddf-ba4e-abc124658a89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922829692 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3922829692
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4226031846
Short name T26
Test name
Test status
Simulation time 463857625 ps
CPU time 0.87 seconds
Started Jan 21 03:50:57 PM PST 24
Finished Jan 21 03:51:05 PM PST 24
Peak memory 200952 kb
Host smart-2f5415c6-0d1f-40ee-ab50-978c52a0a40b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226031846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4226031846
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1272961016
Short name T790
Test name
Test status
Simulation time 322109948761 ps
CPU time 749.2 seconds
Started Jan 21 03:50:53 PM PST 24
Finished Jan 21 04:03:25 PM PST 24
Peak memory 201152 kb
Host smart-993dec2f-8f0f-424a-840e-d5afb8063700
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272961016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1272961016
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2699686964
Short name T334
Test name
Test status
Simulation time 331515548079 ps
CPU time 142.61 seconds
Started Jan 21 03:50:53 PM PST 24
Finished Jan 21 03:53:18 PM PST 24
Peak memory 201204 kb
Host smart-a5b2de8f-8327-47b2-a8c7-4c3291865bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699686964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2699686964
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1257325952
Short name T533
Test name
Test status
Simulation time 165263318389 ps
CPU time 97.26 seconds
Started Jan 21 03:50:53 PM PST 24
Finished Jan 21 03:52:33 PM PST 24
Peak memory 201316 kb
Host smart-80f0dd82-8c0d-474b-8dfc-13c31e12e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257325952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1257325952
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.894817751
Short name T451
Test name
Test status
Simulation time 492139574289 ps
CPU time 1183.32 seconds
Started Jan 21 03:50:52 PM PST 24
Finished Jan 21 04:10:36 PM PST 24
Peak memory 201036 kb
Host smart-976ce19d-dfad-49d9-b03b-b430cfa42699
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=894817751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.894817751
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2226083253
Short name T793
Test name
Test status
Simulation time 163818349190 ps
CPU time 90.68 seconds
Started Jan 21 03:50:52 PM PST 24
Finished Jan 21 03:52:23 PM PST 24
Peak memory 201092 kb
Host smart-e3cf3d5f-0236-49cf-8525-b1a650ef5d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226083253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2226083253
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2520131201
Short name T442
Test name
Test status
Simulation time 333996536592 ps
CPU time 760.78 seconds
Started Jan 21 03:50:54 PM PST 24
Finished Jan 21 04:03:37 PM PST 24
Peak memory 201176 kb
Host smart-98ea6240-eb3a-4f9a-849a-7ad57106a73d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520131201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2520131201
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2520258829
Short name T627
Test name
Test status
Simulation time 167575065041 ps
CPU time 363.1 seconds
Started Jan 21 03:50:53 PM PST 24
Finished Jan 21 03:56:59 PM PST 24
Peak memory 201276 kb
Host smart-f74164f6-ecb9-4713-afcc-a5a3f4b4533d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520258829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2520258829
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1338962618
Short name T435
Test name
Test status
Simulation time 499258920442 ps
CPU time 1094.13 seconds
Started Jan 21 03:50:57 PM PST 24
Finished Jan 21 04:09:19 PM PST 24
Peak memory 201104 kb
Host smart-6e1da6cc-1503-4e77-b54b-75ed49a03555
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338962618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1338962618
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2867159877
Short name T341
Test name
Test status
Simulation time 115271198087 ps
CPU time 456.77 seconds
Started Jan 21 03:50:50 PM PST 24
Finished Jan 21 03:58:28 PM PST 24
Peak memory 201316 kb
Host smart-e5d59b30-3ea3-4e20-a418-ceec71b3b7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867159877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2867159877
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2191500652
Short name T160
Test name
Test status
Simulation time 32847108432 ps
CPU time 72.48 seconds
Started Jan 21 03:50:55 PM PST 24
Finished Jan 21 03:52:09 PM PST 24
Peak memory 201012 kb
Host smart-05bed0ef-e8d6-4093-81f0-706bc4e6e199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191500652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2191500652
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1522855167
Short name T9
Test name
Test status
Simulation time 3255100926 ps
CPU time 7.8 seconds
Started Jan 21 03:50:50 PM PST 24
Finished Jan 21 03:50:59 PM PST 24
Peak memory 201016 kb
Host smart-9fc6987e-c4c3-405a-aa64-fdfa80b3b1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522855167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1522855167
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3261595727
Short name T714
Test name
Test status
Simulation time 5758980357 ps
CPU time 7.51 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:51:15 PM PST 24
Peak memory 200964 kb
Host smart-d2acef29-4d26-45db-a756-8540d3fb1ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261595727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3261595727
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3652788407
Short name T620
Test name
Test status
Simulation time 171386032835 ps
CPU time 202.11 seconds
Started Jan 21 03:50:52 PM PST 24
Finished Jan 21 03:54:15 PM PST 24
Peak memory 201184 kb
Host smart-40eb70a0-ec65-4836-b074-9ce0c398d6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652788407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3652788407
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1100131418
Short name T767
Test name
Test status
Simulation time 479083254 ps
CPU time 0.92 seconds
Started Jan 21 03:51:00 PM PST 24
Finished Jan 21 03:51:05 PM PST 24
Peak memory 200924 kb
Host smart-a2bc2a5f-731e-4e55-9902-114fd3d40399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100131418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1100131418
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.264804715
Short name T166
Test name
Test status
Simulation time 492448722137 ps
CPU time 288.47 seconds
Started Jan 21 03:50:58 PM PST 24
Finished Jan 21 03:55:53 PM PST 24
Peak memory 201192 kb
Host smart-605cc850-ceaf-4f41-990d-f408c208a44b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264804715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.264804715
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.4693228
Short name T309
Test name
Test status
Simulation time 162518215429 ps
CPU time 255.97 seconds
Started Jan 21 03:50:55 PM PST 24
Finished Jan 21 03:55:13 PM PST 24
Peak memory 201228 kb
Host smart-e04a2029-dc8e-4b58-a845-4e5b75fce45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4693228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.4693228
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4249688054
Short name T460
Test name
Test status
Simulation time 164759419958 ps
CPU time 202.28 seconds
Started Jan 21 03:50:55 PM PST 24
Finished Jan 21 03:54:19 PM PST 24
Peak memory 201140 kb
Host smart-0f0167e2-952d-4764-b7cb-8e2b9fccb15e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249688054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4249688054
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1660717419
Short name T761
Test name
Test status
Simulation time 164006818075 ps
CPU time 294.05 seconds
Started Jan 21 03:50:55 PM PST 24
Finished Jan 21 03:55:55 PM PST 24
Peak memory 201224 kb
Host smart-307c25c6-53f8-4f10-abb7-6a490e58de70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660717419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1660717419
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2295141804
Short name T622
Test name
Test status
Simulation time 486497421307 ps
CPU time 1129.7 seconds
Started Jan 21 03:50:55 PM PST 24
Finished Jan 21 04:09:47 PM PST 24
Peak memory 201256 kb
Host smart-5180e538-c102-4044-a146-24d0ca478b23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295141804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2295141804
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2765882182
Short name T172
Test name
Test status
Simulation time 184659542241 ps
CPU time 74.8 seconds
Started Jan 21 03:50:52 PM PST 24
Finished Jan 21 03:52:08 PM PST 24
Peak memory 201172 kb
Host smart-266b43d3-34ab-4881-89f7-ea5d43b92e62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765882182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2765882182
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1925695385
Short name T651
Test name
Test status
Simulation time 328457256439 ps
CPU time 205 seconds
Started Jan 21 03:50:56 PM PST 24
Finished Jan 21 03:54:27 PM PST 24
Peak memory 201140 kb
Host smart-54f9b1fb-01f5-4049-b0e6-5080dca2a38e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925695385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1925695385
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2348243517
Short name T182
Test name
Test status
Simulation time 97101972369 ps
CPU time 451.59 seconds
Started Jan 21 03:50:53 PM PST 24
Finished Jan 21 03:58:27 PM PST 24
Peak memory 201460 kb
Host smart-8ccd44c0-ab9c-4bee-b23e-a5bc666a860b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348243517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2348243517
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.235410455
Short name T439
Test name
Test status
Simulation time 28011694819 ps
CPU time 58.52 seconds
Started Jan 21 03:50:56 PM PST 24
Finished Jan 21 03:52:02 PM PST 24
Peak memory 200992 kb
Host smart-6b65a0fe-b5bb-4802-91cb-8582de0a22c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235410455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.235410455
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.675010322
Short name T670
Test name
Test status
Simulation time 3274290120 ps
CPU time 8.37 seconds
Started Jan 21 03:50:54 PM PST 24
Finished Jan 21 03:51:05 PM PST 24
Peak memory 201064 kb
Host smart-531ce653-d5f8-4176-b756-a86786a323ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675010322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.675010322
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1970993639
Short name T16
Test name
Test status
Simulation time 5906086099 ps
CPU time 4.95 seconds
Started Jan 21 03:51:03 PM PST 24
Finished Jan 21 03:51:13 PM PST 24
Peak memory 200928 kb
Host smart-9444c24b-0365-4932-b3af-4e770d75f520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970993639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1970993639
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.793683946
Short name T725
Test name
Test status
Simulation time 335417712771 ps
CPU time 208.69 seconds
Started Jan 21 03:50:56 PM PST 24
Finished Jan 21 03:54:31 PM PST 24
Peak memory 201248 kb
Host smart-5410a74c-9e61-4d0f-9852-3c600037772c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793683946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.793683946
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.352230200
Short name T102
Test name
Test status
Simulation time 181949388589 ps
CPU time 40.23 seconds
Started Jan 21 03:50:59 PM PST 24
Finished Jan 21 03:51:45 PM PST 24
Peak memory 200784 kb
Host smart-a45d81e8-1391-44ce-842a-e6efcdb6d9c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352230200 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.352230200
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%